From: Mark Brown <broonie@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor.dooley@microchip.com, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Valentina.FernandezAlanis@microchip.com
Subject: Re: [PATCH v3 4/4] MAINTAINERS: add qspi to Polarfire SoC entry
Date: Fri, 5 Aug 2022 12:04:39 +0100 [thread overview]
Message-ID: <Yuz5RzEhwWa7xqlR@sirena.org.uk> (raw)
In-Reply-To: <9e3dbc0f-b04d-c67e-7f39-9cf936ec7252@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 446 bytes --]
On Fri, Aug 05, 2022 at 08:50:37AM +0200, Krzysztof Kozlowski wrote:
> On 05/08/2022 07:30, Naga Sureshkumar Relli wrote:
> > Add the qspi driver to existing Polarfire SoC entry.
> >
> > Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> This should be squashed with previous patch.
It's perfectly fine to have a separate patch for MAINTAINERS like this.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
next prev parent reply other threads:[~2022-08-05 11:04 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 5:30 [PATCH v3 0/4] Add support for Microchip QSPI controller Naga Sureshkumar Relli
2022-08-05 5:30 ` [PATCH v3 1/4] spi: dt-binding: document microchip coreQSPI Naga Sureshkumar Relli
2022-08-05 6:46 ` Krzysztof Kozlowski
2022-08-05 5:30 ` [PATCH v3 2/4] spi: dt-binding: add coreqspi as a fallback for mpfs-qspi Naga Sureshkumar Relli
2022-08-05 6:47 ` Krzysztof Kozlowski
2022-08-05 6:49 ` Krzysztof Kozlowski
2022-08-05 7:34 ` Conor.Dooley
2022-08-05 8:12 ` Krzysztof Kozlowski
2022-08-05 8:44 ` Conor.Dooley
2022-08-05 8:47 ` Krzysztof Kozlowski
2022-08-05 14:14 ` Rob Herring
2022-08-05 5:30 ` [PATCH v3 3/4] spi: microchip-core-qspi: Add support for microchip fpga qspi controllers Naga Sureshkumar Relli
2022-08-05 6:50 ` Krzysztof Kozlowski
2022-08-05 5:30 ` [PATCH v3 4/4] MAINTAINERS: add qspi to Polarfire SoC entry Naga Sureshkumar Relli
2022-08-05 6:50 ` Krzysztof Kozlowski
2022-08-05 11:04 ` Mark Brown [this message]
2022-08-05 11:05 ` Mark Brown
2022-08-05 12:07 ` Conor.Dooley
2022-08-05 12:11 ` Mark Brown
2022-08-05 9:14 ` [PATCH v3 0/4] Add support for Microchip QSPI controller Conor.Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Yuz5RzEhwWa7xqlR@sirena.org.uk \
--to=broonie@kernel.org \
--cc=Valentina.FernandezAlanis@microchip.com \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=nagasuresh.relli@microchip.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).