From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>,
broonie@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor.dooley@microchip.com
Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Valentina.FernandezAlanis@microchip.com
Subject: Re: [PATCH v3 3/4] spi: microchip-core-qspi: Add support for microchip fpga qspi controllers
Date: Fri, 5 Aug 2022 08:50:17 +0200 [thread overview]
Message-ID: <fa9fca3b-4b8b-1a51-3e8b-45f1ae2e15df@linaro.org> (raw)
In-Reply-To: <20220805053019.996484-4-nagasuresh.relli@microchip.com>
On 05/08/2022 07:30, Naga Sureshkumar Relli wrote:
> Add a driver for Microchip FPGA QSPI controllers. This driver also
> supports "hard" QSPI controllers on Polarfire SoC.
>
Thank you for your patch. There is something to discuss/improve.
> + ret = clk_prepare_enable(qspi->clk);
> + if (ret)
> + return dev_err_probe(&pdev->dev, ret,
> + "failed to enable clock\n");
> +
> + init_completion(&qspi->data_completion);
> + mutex_init(&qspi->op_lock);
> +
> + qspi->irq = platform_get_irq(pdev, 0);
> + if (qspi->irq <= 0) {
< 0
Why did you change it to <=?
> + ret = qspi->irq;
> + goto out;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr,
> + IRQF_SHARED, pdev->name, qspi);
> + if (ret) {
> + dev_err(&pdev->dev, "request_irq failed %d\n", ret);
> + goto out;
> + }
> +
> + ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
> + ctlr->mem_ops = &mchp_coreqspi_mem_ops;
> + ctlr->setup = mchp_coreqspi_setup_op;
> + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
> + SPI_TX_DUAL | SPI_TX_QUAD;
> + ctlr->dev.of_node = np;
> +
> + ret = devm_spi_register_controller(&pdev->dev, ctlr);
> + if (ret) {
> + dev_err_probe(&pdev->dev, ret,
> + "spi_register_controller failed\n");
> + goto out;
> + }
> +
> + return 0;
> +
> +out:
> + clk_disable_unprepare(qspi->clk);
> +
> + return ret;
> +}
> +
> +static int mchp_coreqspi_remove(struct platform_device *pdev)
> +{
> + struct mchp_coreqspi *qspi = platform_get_drvdata(pdev);
> + u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
> +
> + mchp_coreqspi_disable_ints(qspi);
> + control &= ~CONTROL_ENABLE;
> + writel_relaxed(control, qspi->regs + REG_CONTROL);
> + clk_disable_unprepare(qspi->clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mchp_coreqspi_of_match[] = {
> + { .compatible = "microchip,mpfs-qspi" },
> + { .compatible = "microchip,coreqspi-rtl-v2" },
This is not what the binding is saying.
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-08-05 6:50 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 5:30 [PATCH v3 0/4] Add support for Microchip QSPI controller Naga Sureshkumar Relli
2022-08-05 5:30 ` [PATCH v3 1/4] spi: dt-binding: document microchip coreQSPI Naga Sureshkumar Relli
2022-08-05 6:46 ` Krzysztof Kozlowski
2022-08-05 5:30 ` [PATCH v3 2/4] spi: dt-binding: add coreqspi as a fallback for mpfs-qspi Naga Sureshkumar Relli
2022-08-05 6:47 ` Krzysztof Kozlowski
2022-08-05 6:49 ` Krzysztof Kozlowski
2022-08-05 7:34 ` Conor.Dooley
2022-08-05 8:12 ` Krzysztof Kozlowski
2022-08-05 8:44 ` Conor.Dooley
2022-08-05 8:47 ` Krzysztof Kozlowski
2022-08-05 14:14 ` Rob Herring
2022-08-05 5:30 ` [PATCH v3 3/4] spi: microchip-core-qspi: Add support for microchip fpga qspi controllers Naga Sureshkumar Relli
2022-08-05 6:50 ` Krzysztof Kozlowski [this message]
2022-08-05 5:30 ` [PATCH v3 4/4] MAINTAINERS: add qspi to Polarfire SoC entry Naga Sureshkumar Relli
2022-08-05 6:50 ` Krzysztof Kozlowski
2022-08-05 11:04 ` Mark Brown
2022-08-05 11:05 ` Mark Brown
2022-08-05 12:07 ` Conor.Dooley
2022-08-05 12:11 ` Mark Brown
2022-08-05 9:14 ` [PATCH v3 0/4] Add support for Microchip QSPI controller Conor.Dooley
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