From: Sergey Suloev <ssuloev@orpaltech.com>
To: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Mark Brown <broonie@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/6] spi: sun6i: restrict transfer length in PIO-mode
Date: Wed, 4 Apr 2018 14:35:14 +0300 [thread overview]
Message-ID: <a6044902-8977-3ce1-d7d5-c6797341a5d0@orpaltech.com> (raw)
In-Reply-To: <20180404065048.n76r3ytuznd6fqsl@flea>
On 04/04/2018 09:50 AM, Maxime Ripard wrote:
> On Tue, Apr 03, 2018 at 06:44:46PM +0300, Sergey Suloev wrote:
>> There is no need to handle 3/4 empty interrupt as the maximum
>> supported transfer length in PIO mode is equal to FIFO depth,
>> i.e. 128 bytes for sun6i and 64 bytes for sun8i SoCs.
>>
>> Changes in v3:
>> 1) Restored processing of 3/4 FIFO full interrupt.
>>
>> Signed-off-by: Sergey Suloev <ssuloev@orpaltech.com>
>> ---
>> drivers/spi/spi-sun6i.c | 41 +++++++++++++++++------------------------
>> 1 file changed, 17 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
>> index 78acc1f..c09ad10 100644
>> --- a/drivers/spi/spi-sun6i.c
>> +++ b/drivers/spi/spi-sun6i.c
>> @@ -207,7 +207,10 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
>>
>> static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
>> {
>> - return SUN6I_MAX_XFER_SIZE - 1;
>> + struct spi_master *master = spi->master;
>> + struct sun6i_spi *sspi = spi_master_get_devdata(master);
>> +
>> + return sspi->fifo_depth;
> Doesn't that effectively revert 3288d5cb40c0 ?
>
> Why do you need to do so?
Need what?
Change is supposed to restrict max transfer size for PIO mode otherwise
it will fail.
The maximum transfer length = FIFO depth for PIO mode.
>
>> }
>>
>> static int sun6i_spi_prepare_message(struct spi_master *master,
>> @@ -255,8 +258,14 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
>> int ret = 0;
>> u32 reg;
>>
>> - if (tfr->len > SUN6I_MAX_XFER_SIZE)
>> - return -EINVAL;
>> + /* A zero length transfer never finishes if programmed
>> + in the hardware */
> Improper comment style here. Please make sure to run checkpatch before
> sending your patches.
ok
>
>> + if (!tfr->len)
>> + return 0;
> Can that case even happen?
Not sure, just for safety.
>
>> + /* Don't support transfer larger than the FIFO */
>> + if (tfr->len > sspi->fifo_depth)
>> + return -EMSGSIZE;
> You're changing the return type, why?
As a more appropriate one
>
>> reinit_completion(&sspi->done);
>> sspi->tx_buf = tfr->tx_buf;
>> @@ -278,8 +287,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
>> */
>> trig_level = sspi->fifo_depth / 4 * 3;
>> sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
>> - (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
>> - (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
>> + (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS));
>>
>>
>> reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
>> @@ -343,11 +351,8 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
>> sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
>>
>> /* Enable the interrupts */
>> - sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
>> sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC |
>> SUN6I_INT_CTL_RF_RDY);
>> - if (tx_len > sspi->fifo_depth)
>> - sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
> This would also need to be explained in your commit log.
What exactly and in what way ?
>
>>
>> /* Start the transfer */
>> reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
>> @@ -376,7 +381,9 @@ out:
>> static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
>> {
>> struct sun6i_spi *sspi = dev_id;
>> - u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
>> + u32 status;
>> +
>> + status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
> Why is this change needed?
A minor one, for readability.
>
> Maxime
>
next prev parent reply other threads:[~2018-04-04 11:35 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-03 15:44 [PATCH v3 0/6] spi: Add support for DMA transfers in sun6i SPI driver Sergey Suloev
2018-04-03 15:44 ` [PATCH v3 1/6] spi: sun6i: coding style/readability improvements Sergey Suloev
2018-04-04 6:45 ` Maxime Ripard
2018-04-03 15:44 ` [PATCH v3 2/6] spi: sun6i: handle chip select polarity flag Sergey Suloev
2018-04-03 15:44 ` [PATCH v3 3/6] spi: sun6i: restrict transfer length in PIO-mode Sergey Suloev
2018-04-04 6:50 ` Maxime Ripard
2018-04-04 11:35 ` Sergey Suloev [this message]
2018-04-05 9:19 ` Maxime Ripard
2018-04-05 9:59 ` Sergey Suloev
2018-04-05 13:17 ` Mark Brown
2018-04-05 13:44 ` Sergey Suloev
2018-04-06 7:34 ` Maxime Ripard
2018-04-06 15:48 ` Sergey Suloev
2018-04-09 9:27 ` Maxime Ripard
2018-04-09 10:26 ` Sergey Suloev
2018-04-09 10:50 ` Mark Brown
2018-04-09 11:10 ` Sergey Suloev
2018-04-09 11:27 ` Mark Brown
2018-04-09 11:36 ` Maxime Ripard
2018-04-09 11:59 ` Sergey Suloev
2018-04-10 14:05 ` Maxime Ripard
2018-04-06 15:54 ` Sergey Suloev
2018-04-05 10:07 ` Mark Brown
2018-04-03 15:44 ` [PATCH v3 4/6] spi: sun6i: use completion provided by SPI core Sergey Suloev
2018-04-04 6:53 ` Maxime Ripard
2018-04-03 15:44 ` [PATCH v3 5/6] spi: sun6i: introduce register set/unset helpers Sergey Suloev
2018-04-04 1:32 ` kbuild test robot
2018-04-04 7:02 ` Maxime Ripard
2018-04-03 15:44 ` [PATCH v3 6/6] spi: sun6i: add DMA transfers support Sergey Suloev
2018-04-04 7:00 ` Maxime Ripard
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