[PATCH 0/3] perf: disable sampled events if no PMU interrupt

[PATCH 0/3] perf: disable sampled events if no PMU interrupt

[Vince Weaver]

Hello

This patch series adds a common shared interface for returning ENOTSUPP
if a user tries to create a sampled event (one with sample_period set)
on a machine that has no usable PMU interrupt.

Currently only x86 and ARM are implemented but if the patch is accepted
then we can move other architectures over to use the interface.

This patch also has the side effect of enabling perf to work on 
raspberry-pi machines.

Consideration should also be given to disabling sampling support on 
machines with buggy PMU interrupts (such as Cortex-A8 and Cortex-A9
ARM platforms).

Vince

[PATCH 1/3] perf: disable sampled events if no PMU interrupt

[Vince Weaver]

Add common code to generate ENOTSUPP at event creation time if an 
architecture attempts to create a sampled event and PERF_PMU_NO_INTERRUPT
is set.

This adds a new pmu->capabilities flag.  
Initially we only support PERF_PMU_NO_INTERRUPT (to indicate a PMU
has no support for generating hardware interrupts) but there are 
other capabilities that can be added later.

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>

diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 3356abc..2164763 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -251,9 +251,20 @@ struct pmu {
 	 * flush branch stack on context-switches (needed in cpu-wide mode)
 	 */
 	void (*flush_branch_stack)	(void);
+
+	/*
+	 * various common per-pmu feature flags
+	 */
+	int capabilities;
+
 };
 
 /**
+ * struct pmu->capabilites flags
+ */
+#define PERF_PMU_NO_INTERRUPT		1
+
+/**
  * enum perf_event_active_state - the states of a event
  */
 enum perf_event_active_state {
diff --git a/kernel/events/core.c b/kernel/events/core.c
index f83a71a..f5d8554 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -7072,6 +7072,13 @@ SYSCALL_DEFINE5(perf_event_open,
 		}
 	}
 
+	if (is_sampling_event(event)) {
+		if (event->pmu->capabilities & PERF_PMU_NO_INTERRUPT) {
+			err = -ENOTSUPP;
+			goto err_alloc;
+		}
+	}
+
 	account_event(event);
 
 	/*

[PATCH 2/3] perf, ARM: use common PMU interrupt disabled code

[Vince Weaver]

Make the ARM perf code use the new common PMU interrupt disabled code.

This allows perf to work on ARM machines without a working PMU
interrupt (for example, raspberry pi).

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index a6bc431..4238bcb 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -410,7 +410,7 @@ __hw_perf_event_init(struct perf_event *event)
 	 */
 	hwc->config_base	    |= (unsigned long)mapping;
 
-	if (!hwc->sample_period) {
+	if (!is_sampling_event(event)) {
 		/*
 		 * For non-sampling runs, limit the sample_period to half
 		 * of the counter width. That way, the new counter value
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 51798d7..63d95fa 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -126,8 +126,8 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
 
 	irqs = min(pmu_device->num_resources, num_possible_cpus());
 	if (irqs < 1) {
-		pr_err("no irqs for PMUs defined\n");
-		return -ENODEV;
+		printk_once("no irqs for PMU defined, sampled events not supported\n");
+		return 0;
 	}
 
 	irq = platform_get_irq(pmu_device, 0);
@@ -191,6 +191,11 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
 	/* Ensure the PMU has sane values out of reset. */
 	if (cpu_pmu->reset)
 		on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
+
+	/* If no interrupts available, set the corresponding capability flag */
+	if (platform_get_irq(cpu_pmu->plat_device, 0) <= 0) {
+		cpu_pmu->pmu.capabilities |= PERF_PMU_NO_INTERRUPT;
+	}
 }
 
 /*

[PATCH 3/3] perf,x86: use common PMU interrupt disabled code

[Vince Weaver]

Make the x86 perf code use the new common PMU interrupt disabled code.

Typically most x86 machines have working PMU interrupts, although
some older p6-class machines had this problem.

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>

diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index ae407f7..adba966 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -303,15 +303,6 @@ int x86_setup_perfctr(struct perf_event *event)
 		hwc->sample_period = x86_pmu.max_period;
 		hwc->last_period = hwc->sample_period;
 		local64_set(&hwc->period_left, hwc->sample_period);
-	} else {
-		/*
-		 * If we have a PMU initialized but no APIC
-		 * interrupts, we cannot sample hardware
-		 * events (user-space has to fall back and
-		 * sample via a hrtimer based software event):
-		 */
-		if (!x86_pmu.apic)
-			return -EOPNOTSUPP;
 	}
 
 	if (attr->type == PERF_TYPE_RAW)
@@ -1365,6 +1356,15 @@ static void __init pmu_check_apic(void)
 	x86_pmu.apic = 0;
 	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
 	pr_info("no hardware sampling interrupt available.\n");
+
+	/*
+	 * If we have a PMU initialized but no APIC
+	 * interrupts, we cannot sample hardware
+	 * events (user-space has to fall back and
+	 * sample via a hrtimer based software event):
+	 */
+	pmu.capabilities |= PERF_PMU_NO_INTERRUPT;
+
 }
 
 static struct attribute_group x86_pmu_format_group = {

Re: [PATCH 2/3] perf, ARM: use common PMU interrupt disabled code

[Will Deacon]

On Fri, May 16, 2014 at 10:15:49PM +0100, Vince Weaver wrote:
> 
> Make the ARM perf code use the new common PMU interrupt disabled code.
> 
> This allows perf to work on ARM machines without a working PMU
> interrupt (for example, raspberry pi).
> 
> Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
> 
> diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
> index a6bc431..4238bcb 100644
> --- a/arch/arm/kernel/perf_event.c
> +++ b/arch/arm/kernel/perf_event.c
> @@ -410,7 +410,7 @@ __hw_perf_event_init(struct perf_event *event)
>  	 */
>  	hwc->config_base	    |= (unsigned long)mapping;
>  
> -	if (!hwc->sample_period) {
> +	if (!is_sampling_event(event)) {
>  		/*
>  		 * For non-sampling runs, limit the sample_period to half
>  		 * of the counter width. That way, the new counter value
> diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
> index 51798d7..63d95fa 100644
> --- a/arch/arm/kernel/perf_event_cpu.c
> +++ b/arch/arm/kernel/perf_event_cpu.c
> @@ -126,8 +126,8 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
>  
>  	irqs = min(pmu_device->num_resources, num_possible_cpus());
>  	if (irqs < 1) {
> -		pr_err("no irqs for PMUs defined\n");
> -		return -ENODEV;
> +		printk_once("no irqs for PMU defined, sampled events not supported\n");

s/sampled/sampling/

> +		return 0;
>  	}
>  
>  	irq = platform_get_irq(pmu_device, 0);
> @@ -191,6 +191,11 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
>  	/* Ensure the PMU has sane values out of reset. */
>  	if (cpu_pmu->reset)
>  		on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
> +
> +	/* If no interrupts available, set the corresponding capability flag */
> +	if (platform_get_irq(cpu_pmu->plat_device, 0) <= 0) {

I think you can just do if (!platform_get_irq(cpu_pmu->plat_device, 0))
here (I appreciate the ARM perf code isn't consistent here).

Anyway, with those minor changes:

  Acked-by: Will Deacon <will.deacon@arm.com>

Thanks,

Will

Re: [PATCH 1/3] perf: disable sampled events if no PMU interrupt

[Will Deacon]

On Fri, May 16, 2014 at 10:12:12PM +0100, Vince Weaver wrote:
> 
> Add common code to generate ENOTSUPP at event creation time if an 
> architecture attempts to create a sampled event and PERF_PMU_NO_INTERRUPT
> is set.
> 
> This adds a new pmu->capabilities flag.  
> Initially we only support PERF_PMU_NO_INTERRUPT (to indicate a PMU
> has no support for generating hardware interrupts) but there are 
> other capabilities that can be added later.
> 
> Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
> 
> diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> index 3356abc..2164763 100644
> --- a/include/linux/perf_event.h
> +++ b/include/linux/perf_event.h
> @@ -251,9 +251,20 @@ struct pmu {
>  	 * flush branch stack on context-switches (needed in cpu-wide mode)
>  	 */
>  	void (*flush_branch_stack)	(void);
> +
> +	/*
> +	 * various common per-pmu feature flags
> +	 */
> +	int capabilities;

Move this to the top of the struct, along with the other data fields?

Anyway, this looks really useful to me and I'd really like to use it for
ARM!

 Acked-by: Will Deacon <will.deacon@arm.com>

Will


> +
>  };
>  
>  /**
> + * struct pmu->capabilites flags
> + */
> +#define PERF_PMU_NO_INTERRUPT		1
> +
> +/**
>   * enum perf_event_active_state - the states of a event
>   */
>  enum perf_event_active_state {
> diff --git a/kernel/events/core.c b/kernel/events/core.c
> index f83a71a..f5d8554 100644
> --- a/kernel/events/core.c
> +++ b/kernel/events/core.c
> @@ -7072,6 +7072,13 @@ SYSCALL_DEFINE5(perf_event_open,
>  		}
>  	}
>  
> +	if (is_sampling_event(event)) {
> +		if (event->pmu->capabilities & PERF_PMU_NO_INTERRUPT) {
> +			err = -ENOTSUPP;
> +			goto err_alloc;
> +		}
> +	}
> +
>  	account_event(event);
>  
>  	/*
> 

Re: [PATCH 1/3] perf: disable sampled events if no PMU interrupt

[Peter Zijlstra]

On Fri, May 16, 2014 at 05:12:12PM -0400, Vince Weaver wrote:
> 
> Add common code to generate ENOTSUPP at event creation time if an 
> architecture attempts to create a sampled event and PERF_PMU_NO_INTERRUPT
> is set.
> 
> This adds a new pmu->capabilities flag.  
> Initially we only support PERF_PMU_NO_INTERRUPT (to indicate a PMU
> has no support for generating hardware interrupts) but there are 
> other capabilities that can be added later.
> 
> Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
> 
> diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> index 3356abc..2164763 100644
> --- a/include/linux/perf_event.h
> +++ b/include/linux/perf_event.h
> @@ -251,9 +251,20 @@ struct pmu {
>  	 * flush branch stack on context-switches (needed in cpu-wide mode)
>  	 */
>  	void (*flush_branch_stack)	(void);
> +
> +	/*
> +	 * various common per-pmu feature flags
> +	 */
> +	int capabilities;

As suggested by Will, I've put it in a 4 byte hole earlier in the
structure.

>  };
>  
>  /**
> + * struct pmu->capabilites flags

Due to braindamage from years of C++ coding, many other comments refer
to members using the C++ :: notation, so I've changed that to be
consistent and read: pmu::capabilities.

> + */
> +#define PERF_PMU_NO_INTERRUPT		1

Are you ok with me making that:

#define PERF_PMU_CAP_NO_INTERRUPT		0x01

Re: [PATCH 2/3] perf, ARM: use common PMU interrupt disabled code

[Peter Zijlstra]

On Mon, May 19, 2014 at 04:57:10PM +0100, Will Deacon wrote:
> On Fri, May 16, 2014 at 10:15:49PM +0100, Vince Weaver wrote:
> > 
> > Make the ARM perf code use the new common PMU interrupt disabled code.
> > 
> > This allows perf to work on ARM machines without a working PMU
> > interrupt (for example, raspberry pi).
> > 
> > Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
> > 
> > diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
> > index a6bc431..4238bcb 100644
> > --- a/arch/arm/kernel/perf_event.c
> > +++ b/arch/arm/kernel/perf_event.c
> > @@ -410,7 +410,7 @@ __hw_perf_event_init(struct perf_event *event)
> >  	 */
> >  	hwc->config_base	    |= (unsigned long)mapping;
> >  
> > -	if (!hwc->sample_period) {
> > +	if (!is_sampling_event(event)) {
> >  		/*
> >  		 * For non-sampling runs, limit the sample_period to half
> >  		 * of the counter width. That way, the new counter value
> > diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
> > index 51798d7..63d95fa 100644
> > --- a/arch/arm/kernel/perf_event_cpu.c
> > +++ b/arch/arm/kernel/perf_event_cpu.c
> > @@ -126,8 +126,8 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
> >  
> >  	irqs = min(pmu_device->num_resources, num_possible_cpus());
> >  	if (irqs < 1) {
> > -		pr_err("no irqs for PMUs defined\n");
> > -		return -ENODEV;
> > +		printk_once("no irqs for PMU defined, sampled events not supported\n");
> 
> s/sampled/sampling/
> 
> > +		return 0;
> >  	}
> >  
> >  	irq = platform_get_irq(pmu_device, 0);
> > @@ -191,6 +191,11 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
> >  	/* Ensure the PMU has sane values out of reset. */
> >  	if (cpu_pmu->reset)
> >  		on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
> > +
> > +	/* If no interrupts available, set the corresponding capability flag */
> > +	if (platform_get_irq(cpu_pmu->plat_device, 0) <= 0) {
> 
> I think you can just do if (!platform_get_irq(cpu_pmu->plat_device, 0))
> here (I appreciate the ARM perf code isn't consistent here).
> 
> Anyway, with those minor changes:
> 
>   Acked-by: Will Deacon <will.deacon@arm.com>

I did those two changes (and one of my own), thanks!

Re: [PATCH 1/3] perf: disable sampled events if no PMU interrupt

[Vince Weaver]

On Tue, 20 May 2014, Peter Zijlstra wrote:

> > +#define PERF_PMU_NO_INTERRUPT		1
> 
> Are you ok with me making that:
> 
> #define PERF_PMU_CAP_NO_INTERRUPT		0x01

sounds good.  All my recent fuzzing has made me paranoid enough to 
double check that yes indeed we don't need to slap an ULL on the end of 
that.

Though I hope 32-bits is enough for this, I feel like we've just added the 
feature and suddenly all kinds of uses are coming out of the woodwork.

Vince

Re: [PATCH 1/3] perf: disable sampled events if no PMU interrupt

[Peter Zijlstra]

[-- Attachment #1: Type: text/plain, Size: 681 bytes --]

On Tue, May 20, 2014 at 09:19:27AM -0400, Vince Weaver wrote:
> On Tue, 20 May 2014, Peter Zijlstra wrote:
> 
> > > +#define PERF_PMU_NO_INTERRUPT		1
> > 
> > Are you ok with me making that:
> > 
> > #define PERF_PMU_CAP_NO_INTERRUPT		0x01
> 
> sounds good.  All my recent fuzzing has made me paranoid enough to 
> double check that yes indeed we don't need to slap an ULL on the end of 
> that.

Thanks!

> Though I hope 32-bits is enough for this, I feel like we've just added the 
> feature and suddenly all kinds of uses are coming out of the woodwork.

If we run out of bits we can always grow this thing, its not exposed to
userspace so no A[BP]I issues.

[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]

[tip:perf/core] perf: Disable sampled events if no PMU interrupt

[tip-bot for Vince Weaver]

Commit-ID:  53b25335dd60981ad608da7890420898a34469a6
Gitweb:     http://git.kernel.org/tip/53b25335dd60981ad608da7890420898a34469a6
Author:     Vince Weaver <vincent.weaver@maine.edu>
AuthorDate: Fri, 16 May 2014 17:12:12 -0400
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 5 Jun 2014 12:29:55 +0200

perf: Disable sampled events if no PMU interrupt

Add common code to generate -ENOTSUPP at event creation time if an
architecture attempts to create a sampled event and
PERF_PMU_NO_INTERRUPT is set.

This adds a new pmu->capabilities flag.  Initially we only support
PERF_PMU_NO_INTERRUPT (to indicate a PMU has no support for generating
hardware interrupts) but there are other capabilities that can be
added later.

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Acked-by: Will Deacon <will.deacon@arm.com>
[peterz: rename to PERF_PMU_CAP_* and moved the pmu::capabilities word into a hole]
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: http://lkml.kernel.org/r/alpine.DEB.2.10.1405161708060.11099@vincent-weaver-1.umelst.maine.edu
Signed-off-by: Ingo Molnar <mingo@kernel.org>

Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 include/linux/perf_event.h | 10 ++++++++++
 kernel/events/core.c       |  7 +++++++
 2 files changed, 17 insertions(+)

diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index af6dcf1..267c8f3 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -167,6 +167,11 @@ struct perf_event;
 #define PERF_EVENT_TXN 0x1
 
 /**
+ * pmu::capabilities flags
+ */
+#define PERF_PMU_CAP_NO_INTERRUPT		0x01
+
+/**
  * struct pmu - generic performance monitoring unit
  */
 struct pmu {
@@ -178,6 +183,11 @@ struct pmu {
 	const char			*name;
 	int				type;
 
+	/*
+	 * various common per-pmu feature flags
+	 */
+	int				capabilities;
+
 	int * __percpu			pmu_disable_count;
 	struct perf_cpu_context * __percpu pmu_cpu_context;
 	int				task_ctx_nr;
diff --git a/kernel/events/core.c b/kernel/events/core.c
index a62d142..e9ef0c6 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -7120,6 +7120,13 @@ SYSCALL_DEFINE5(perf_event_open,
 		}
 	}
 
+	if (is_sampling_event(event)) {
+		if (event->pmu->capabilities & PERF_PMU_CAP_NO_INTERRUPT) {
+			err = -ENOTSUPP;
+			goto err_alloc;
+		}
+	}
+
 	account_event(event);
 
 	/*

[tip:perf/core] perf/ARM: Use common PMU interrupt disabled code

[tip-bot for Vince Weaver]

Commit-ID:  edcb4d3c36a6429caa03ddfeab4cbb153c7002b2
Gitweb:     http://git.kernel.org/tip/edcb4d3c36a6429caa03ddfeab4cbb153c7002b2
Author:     Vince Weaver <vincent.weaver@maine.edu>
AuthorDate: Fri, 16 May 2014 17:15:49 -0400
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 5 Jun 2014 12:30:00 +0200

perf/ARM: Use common PMU interrupt disabled code

Make the ARM perf code use the new common PMU interrupt disabled code.

This allows perf to work on ARM machines without a working PMU
interrupt (for example, raspberry pi).

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
[peterz: applied changes suggested by Will]
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/alpine.DEB.2.10.1405161712190.11099@vincent-weaver-1.umelst.maine.edu
[ Small readability tweaks to the code. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>

Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/arm/kernel/perf_event.c     | 2 +-
 arch/arm/kernel/perf_event_cpu.c | 8 ++++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index a6bc431..4238bcb 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -410,7 +410,7 @@ __hw_perf_event_init(struct perf_event *event)
 	 */
 	hwc->config_base	    |= (unsigned long)mapping;
 
-	if (!hwc->sample_period) {
+	if (!is_sampling_event(event)) {
 		/*
 		 * For non-sampling runs, limit the sample_period to half
 		 * of the counter width. That way, the new counter value
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 51798d7..bbdbffd 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -126,8 +126,8 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
 
 	irqs = min(pmu_device->num_resources, num_possible_cpus());
 	if (irqs < 1) {
-		pr_err("no irqs for PMUs defined\n");
-		return -ENODEV;
+		printk_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
+		return 0;
 	}
 
 	irq = platform_get_irq(pmu_device, 0);
@@ -191,6 +191,10 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
 	/* Ensure the PMU has sane values out of reset. */
 	if (cpu_pmu->reset)
 		on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
+
+	/* If no interrupts available, set the corresponding capability flag */
+	if (!platform_get_irq(cpu_pmu->plat_device, 0))
+		cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
 }
 
 /*

[tip:perf/core] perf/x86: Use common PMU interrupt disabled code

[tip-bot for Vince Weaver]

Commit-ID:  c184c980de30dc5f6fec4b281928aa6743708da9
Gitweb:     http://git.kernel.org/tip/c184c980de30dc5f6fec4b281928aa6743708da9
Author:     Vince Weaver <vincent.weaver@maine.edu>
AuthorDate: Fri, 16 May 2014 17:18:07 -0400
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 5 Jun 2014 12:30:03 +0200

perf/x86: Use common PMU interrupt disabled code

Make the x86 perf code use the new common PMU interrupt disabled code.

Typically most x86 machines have working PMU interrupts, although
some older p6-class machines had this problem.

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: http://lkml.kernel.org/r/alpine.DEB.2.10.1405161715560.11099@vincent-weaver-1.umelst.maine.edu
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/kernel/cpu/perf_event.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 32029e3..2bdfbff 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -303,15 +303,6 @@ int x86_setup_perfctr(struct perf_event *event)
 		hwc->sample_period = x86_pmu.max_period;
 		hwc->last_period = hwc->sample_period;
 		local64_set(&hwc->period_left, hwc->sample_period);
-	} else {
-		/*
-		 * If we have a PMU initialized but no APIC
-		 * interrupts, we cannot sample hardware
-		 * events (user-space has to fall back and
-		 * sample via a hrtimer based software event):
-		 */
-		if (!x86_pmu.apic)
-			return -EOPNOTSUPP;
 	}
 
 	if (attr->type == PERF_TYPE_RAW)
@@ -1367,6 +1358,15 @@ static void __init pmu_check_apic(void)
 	x86_pmu.apic = 0;
 	pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
 	pr_info("no hardware sampling interrupt available.\n");
+
+	/*
+	 * If we have a PMU initialized but no APIC
+	 * interrupts, we cannot sample hardware
+	 * events (user-space has to fall back and
+	 * sample via a hrtimer based software event):
+	 */
+	pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
+
 }
 
 static struct attribute_group x86_pmu_format_group = {