* Broadwell perf support
@ 2014-08-25 22:43 Andi Kleen
2014-08-25 22:43 ` [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen
` (4 more replies)
0 siblings, 5 replies; 22+ messages in thread
From: Andi Kleen @ 2014-08-25 22:43 UTC (permalink / raw)
To: peterz; +Cc: linux-kernel, mingo, eranian
Updated version of the perf Broadwell patchkit. This also has some fixes
for Haswell.
This addresses all earlier feedback. Too low user specified periods
on INST_RETIRED.ALL are now rejected with an error. The Haswell
models are documented. The event matches use the perf macros.
-Andi
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf 2014-08-25 22:43 Broadwell perf support Andi Kleen @ 2014-08-25 22:43 ` Andi Kleen 2014-08-26 21:27 ` Thomas Gleixner 2014-08-25 22:43 ` [PATCH 2/5] perf, x86: Document all Haswell models Andi Kleen ` (3 subsequent siblings) 4 siblings, 1 reply; 22+ messages in thread From: Andi Kleen @ 2014-08-25 22:43 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, mingo, eranian, Andi Kleen From: Andi Kleen <ak@linux.intel.com> Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 89bc750..e280a86 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2541,10 +2541,9 @@ __init int intel_pmu_init(void) case 60: /* 22nm Haswell */ + case 70: case 63: case 69: - case 70: - case 71: x86_pmu.late_ack = true; memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); -- 1.9.3 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf 2014-08-25 22:43 ` [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen @ 2014-08-26 21:27 ` Thomas Gleixner 2014-08-26 21:29 ` Andi Kleen 0 siblings, 1 reply; 22+ messages in thread From: Thomas Gleixner @ 2014-08-26 21:27 UTC (permalink / raw) To: Andi Kleen; +Cc: peterz, linux-kernel, mingo, eranian, Andi Kleen On Mon, 25 Aug 2014, Andi Kleen wrote: > From: Andi Kleen <ak@linux.intel.com> > > Signed-off-by: Andi Kleen <ak@linux.intel.com> > --- > arch/x86/kernel/cpu/perf_event_intel.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c > index 89bc750..e280a86 100644 > --- a/arch/x86/kernel/cpu/perf_event_intel.c > +++ b/arch/x86/kernel/cpu/perf_event_intel.c > @@ -2541,10 +2541,9 @@ __init int intel_pmu_init(void) > > > case 60: /* 22nm Haswell */ > + case 70: > case 63: > case 69: > - case 70: > - case 71: So what's the point of making the obvious onliner patch - case 71: into something which reorders the sorted case numbers? And of course, this patch is missing any explanation WHY 71 is incorrect and how it got there in the first place. Thanks, tglx ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf 2014-08-26 21:27 ` Thomas Gleixner @ 2014-08-26 21:29 ` Andi Kleen 2014-08-26 22:29 ` Thomas Gleixner 0 siblings, 1 reply; 22+ messages in thread From: Andi Kleen @ 2014-08-26 21:29 UTC (permalink / raw) To: Thomas Gleixner Cc: Andi Kleen, peterz, linux-kernel, mingo, eranian, Andi Kleen > So what's the point of making the obvious onliner patch > > - case 71: > > into something which reorders the sorted case numbers? This was a merging mistake. I'll fix it to be a one liner. > And of course, this patch is missing any explanation WHY 71 is > incorrect and how it got there in the first place. 71 is a Broadwell, as you would know if you had read the next patch. -Andi ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf 2014-08-26 21:29 ` Andi Kleen @ 2014-08-26 22:29 ` Thomas Gleixner 2014-08-27 9:53 ` Thomas Gleixner 0 siblings, 1 reply; 22+ messages in thread From: Thomas Gleixner @ 2014-08-26 22:29 UTC (permalink / raw) To: Andi Kleen; +Cc: peterz, linux-kernel, mingo, eranian, Andi Kleen On Tue, 26 Aug 2014, Andi Kleen wrote: > > So what's the point of making the obvious onliner patch > > > > - case 71: > > > > into something which reorders the sorted case numbers? > > This was a merging mistake. I'll fix it to be a one liner. > > > And of course, this patch is missing any explanation WHY 71 is > > incorrect and how it got there in the first place. > > 71 is a Broadwell, as you would know if you had read the next patch. And why on earth do I need to read the next patch to figure out what the heck this patch is doing? Just because it's written by someone who gives a shit? Your unwillingness to cooperate and your advisory resistance are slowly approaching the Krause level... Thanks, tglx ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf 2014-08-26 22:29 ` Thomas Gleixner @ 2014-08-27 9:53 ` Thomas Gleixner 2014-08-27 16:37 ` Andi Kleen 0 siblings, 1 reply; 22+ messages in thread From: Thomas Gleixner @ 2014-08-27 9:53 UTC (permalink / raw) To: Andi Kleen; +Cc: peterz, linux-kernel, mingo, eranian, Andi Kleen On Wed, 27 Aug 2014, Thomas Gleixner wrote: > On Tue, 26 Aug 2014, Andi Kleen wrote: > > > > So what's the point of making the obvious onliner patch > > > > > > - case 71: > > > > > > into something which reorders the sorted case numbers? > > > > This was a merging mistake. I'll fix it to be a one liner. > > > > > And of course, this patch is missing any explanation WHY 71 is > > > incorrect and how it got there in the first place. > > > > 71 is a Broadwell, as you would know if you had read the next patch. > > And why on earth do I need to read the next patch to figure out what > the heck this patch is doing? > > Just because it's written by someone who gives a shit? > > Your unwillingness to cooperate and your advisory resistance are > slowly approaching the Krause level... And after reading the next patch I still can't see that 71 is a broadwell, because the next patch merily adds haswell names to the numbers. Neither of the following patches has the magic 71 incorporated. The only model number related to broadwell is 61 in patch 3/5. Try again when you figured yourself out what number means what and why 71 is bogus. Thanks, tglx ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf 2014-08-27 9:53 ` Thomas Gleixner @ 2014-08-27 16:37 ` Andi Kleen 2014-08-27 18:50 ` Thomas Gleixner 0 siblings, 1 reply; 22+ messages in thread From: Andi Kleen @ 2014-08-27 16:37 UTC (permalink / raw) To: Thomas Gleixner Cc: Andi Kleen, peterz, linux-kernel, mingo, eranian, Andi Kleen On Wed, Aug 27, 2014 at 11:53:57AM +0200, Thomas Gleixner wrote: > On Wed, 27 Aug 2014, Thomas Gleixner wrote: > > > On Tue, 26 Aug 2014, Andi Kleen wrote: > > > > > > So what's the point of making the obvious onliner patch > > > > > > > > - case 71: > > > > > > > > into something which reorders the sorted case numbers? > > > > > > This was a merging mistake. I'll fix it to be a one liner. > > > > > > > And of course, this patch is missing any explanation WHY 71 is > > > > incorrect and how it got there in the first place. > > > > > > 71 is a Broadwell, as you would know if you had read the next patch. > > > > And why on earth do I need to read the next patch to figure out what > > the heck this patch is doing? > > > > Just because it's written by someone who gives a shit? > > > > Your unwillingness to cooperate and your advisory resistance are > > slowly approaching the Krause level... > > And after reading the next patch I still can't see that 71 is a > broadwell, because the next patch merily adds haswell names to the > numbers. Neither of the following patches has the magic 71 > incorporated. The only model number related to broadwell is 61 in > patch 3/5. Ok fair enough. It was true for v1, but not for v2. > Try again when you figured yourself out what number means what and why > 71 is bogus. 71 is definitely not a Haswell, but a Broadwell. However it was removed from the Broadwell patch based on Peter's feedback. So technically the patch is not needed right now because there would be no duplicates (unless 71 was readded), so the compiler would not complain. However it's still incorrect for Haswell, so I maintain removing it is the right thing to do. -Andi ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf 2014-08-27 16:37 ` Andi Kleen @ 2014-08-27 18:50 ` Thomas Gleixner 0 siblings, 0 replies; 22+ messages in thread From: Thomas Gleixner @ 2014-08-27 18:50 UTC (permalink / raw) To: Andi Kleen; +Cc: peterz, linux-kernel, mingo, eranian, Andi Kleen On Wed, 27 Aug 2014, Andi Kleen wrote: > On Wed, Aug 27, 2014 at 11:53:57AM +0200, Thomas Gleixner wrote: > > Try again when you figured yourself out what number means what and why > > 71 is bogus. > > 71 is definitely not a Haswell, but a Broadwell. Fine. So the changelog should tell so. > However it was removed from the Broadwell patch based on Peter's > feedback. > > So technically the patch is not needed right now because there > would be no duplicates (unless 71 was readded), so the compiler > would not complain. It's very well technically needed simply because its not a haswell and if it's run on real model 71 hardware we'll get some interesting stuff to debug. > However it's still incorrect for Haswell, so I maintain removing > it is the right thing to do. I did not argue against the removal itself. That's fine and obviously correct if model 71 is not a haswell. All I want is a proper patch (1 line) and a proper changelog explaining WHY this is the right thing to do. Thanks, tglx ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 2/5] perf, x86: Document all Haswell models 2014-08-25 22:43 Broadwell perf support Andi Kleen 2014-08-25 22:43 ` [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen @ 2014-08-25 22:43 ` Andi Kleen 2014-09-01 13:50 ` Peter Zijlstra 2014-08-25 22:43 ` [PATCH 3/5] perf, x86: Add Broadwell core support Andi Kleen ` (2 subsequent siblings) 4 siblings, 1 reply; 22+ messages in thread From: Andi Kleen @ 2014-08-25 22:43 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, mingo, eranian, Andi Kleen From: Andi Kleen <ak@linux.intel.com> Add names for each Haswell model as requested by Peter. v2: Remove Crystall Well name. Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index e280a86..0e9c272 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2540,10 +2540,10 @@ __init int intel_pmu_init(void) break; - case 60: /* 22nm Haswell */ - case 70: - case 63: - case 69: + case 60: /* 22nm Haswell Client */ + case 70: /* 22nm Haswell Client */ + case 63: /* 22nm Haswell Server */ + case 69: /* 22nm Haswell ULT */ x86_pmu.late_ack = true; memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); -- 1.9.3 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 2/5] perf, x86: Document all Haswell models 2014-08-25 22:43 ` [PATCH 2/5] perf, x86: Document all Haswell models Andi Kleen @ 2014-09-01 13:50 ` Peter Zijlstra 0 siblings, 0 replies; 22+ messages in thread From: Peter Zijlstra @ 2014-09-01 13:50 UTC (permalink / raw) To: Andi Kleen; +Cc: linux-kernel, mingo, eranian, Andi Kleen On Mon, Aug 25, 2014 at 03:43:28PM -0700, Andi Kleen wrote: > From: Andi Kleen <ak@linux.intel.com> > > Add names for each Haswell model as requested by Peter. > > v2: Remove Crystall Well name. > + case 60: /* 22nm Haswell Client */ > + case 70: /* 22nm Haswell Client */ > + case 63: /* 22nm Haswell Server */ > + case 69: /* 22nm Haswell ULT */ That's inconsistent with all the others. I gave you one that makes sense, why not use it? ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/5] perf, x86: Add Broadwell core support 2014-08-25 22:43 Broadwell perf support Andi Kleen 2014-08-25 22:43 ` [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen 2014-08-25 22:43 ` [PATCH 2/5] perf, x86: Document all Haswell models Andi Kleen @ 2014-08-25 22:43 ` Andi Kleen 2014-09-01 13:51 ` Peter Zijlstra 2014-08-25 22:43 ` [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds Andi Kleen 2014-08-25 22:43 ` [PATCH 5/5] perf, x86: Use Broadwell cache event list for Haswell Andi Kleen 4 siblings, 1 reply; 22+ messages in thread From: Andi Kleen @ 2014-08-25 22:43 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, mingo, eranian, Andi Kleen From: Andi Kleen <ak@linux.intel.com> Add Broadwell support for Broadwell Client to perf. This is very similar to Haswell. It uses a new cache event table, because there were various changes there. The constraint list has one new event that needs to be handled over Haswell. The PEBS event list is the same, so we reuse Haswell's. v2: Remove unnamed model numbers. Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel.c | 150 +++++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 0e9c272..1cca4ae 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -220,6 +220,15 @@ static struct event_constraint intel_hsw_event_constraints[] = { EVENT_CONSTRAINT_END }; +struct event_constraint intel_bdw_event_constraints[] = { + FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ + FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ + FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ + INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ + INTEL_EVENT_CONSTRAINT(0xa3, 0x4), /* CYCLE_ACTIVITY.* */ + EVENT_CONSTRAINT_END +}; + static u64 intel_pmu_event_map(int hw_event) { return intel_perfmon_event_map[hw_event]; @@ -415,6 +424,126 @@ static __initconst const u64 snb_hw_cache_event_ids }; +static __initconst const u64 bdw_hw_cache_event_ids + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = +{ + [ C(L1D ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ + [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ + [ C(RESULT_MISS) ] = 0x0, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0x0, + [ C(RESULT_MISS) ] = 0x0, + }, + }, + [ C(L1I ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x0, + [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0x0, + [ C(RESULT_MISS) ] = 0x0, + }, + }, + [ C(LL ) ] = { + [ C(OP_READ) ] = { + /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD */ + [ C(RESULT_ACCESS) ] = 0x1b7, + /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD|SUPPLIER_NONE| + L3_MISS|ANY_SNOOP */ + [ C(RESULT_MISS) ] = 0x1b7, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE:ALL_RFO */ + /* OFFCORE_RESPONSE:ALL_RFO|SUPPLIER_NONE|L3_MISS|ANY_SNOOP */ + [ C(RESULT_MISS) ] = 0x1b7, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0x0, + [ C(RESULT_MISS) ] = 0x0, + }, + }, + [ C(DTLB) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */ + [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */ + [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0x0, + [ C(RESULT_MISS) ] = 0x0, + }, + }, + [ C(ITLB) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */ + [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, + [ C(BPU ) ] = { + [ C(OP_READ) ] = { + [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */ + [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */ + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = -1, + [ C(RESULT_MISS) ] = -1, + }, + }, +}; + +static __initconst const u64 bdw_hw_cache_extra_regs + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] = +{ + [ C(LL ) ] = { + [ C(OP_READ) ] = { + /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD */ + [ C(RESULT_ACCESS) ] = 0x2d5, + /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD|SUPPLIER_NONE| + L3_MISS|ANY_SNOOP */ + [ C(RESULT_MISS) ] = 0x3fbc0202d5, + }, + [ C(OP_WRITE) ] = { + [ C(RESULT_ACCESS) ] = 0x122, /* OFFCORE_RESPONSE:ALL_RFO */ + /* OFFCORE_RESPONSE:ALL_RFO|SUPPLIER_NONE|L3_MISS|ANY_SNOOP */ + [ C(RESULT_MISS) ] = 0x3fbc020122, + }, + [ C(OP_PREFETCH) ] = { + [ C(RESULT_ACCESS) ] = 0x0, + [ C(RESULT_MISS) ] = 0x0, + }, + }, +}; + static __initconst const u64 westmere_hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] @@ -2565,6 +2694,27 @@ __init int intel_pmu_init(void) pr_cont("Haswell events, "); break; + case 61: /* Broadwell Client */ + x86_pmu.late_ack = true; + memcpy(hw_cache_event_ids, bdw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); + memcpy(hw_cache_extra_regs, bdw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); + + intel_pmu_lbr_init_snb(); + + x86_pmu.event_constraints = intel_bdw_event_constraints; + x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; + x86_pmu.extra_regs = intel_snbep_extra_regs; + x86_pmu.pebs_aliases = intel_pebs_aliases_snb; + /* all extra regs are per-cpu when HT is on */ + x86_pmu.er_flags |= ERF_HAS_RSP_1; + x86_pmu.er_flags |= ERF_NO_HT_SHARING; + + x86_pmu.hw_config = hsw_hw_config; + x86_pmu.get_event_constraints = hsw_get_event_constraints; + x86_pmu.cpu_events = hsw_events_attrs; + pr_cont("Broadwell events, "); + break; + default: switch (x86_pmu.version) { case 1: -- 1.9.3 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 3/5] perf, x86: Add Broadwell core support 2014-08-25 22:43 ` [PATCH 3/5] perf, x86: Add Broadwell core support Andi Kleen @ 2014-09-01 13:51 ` Peter Zijlstra 2014-11-04 13:14 ` Stephane Eranian 0 siblings, 1 reply; 22+ messages in thread From: Peter Zijlstra @ 2014-09-01 13:51 UTC (permalink / raw) To: Andi Kleen; +Cc: linux-kernel, mingo, eranian, Andi Kleen On Mon, Aug 25, 2014 at 03:43:29PM -0700, Andi Kleen wrote: > + case 61: /* Broadwell Client */ Again, no other description has "Client" in. ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/5] perf, x86: Add Broadwell core support 2014-09-01 13:51 ` Peter Zijlstra @ 2014-11-04 13:14 ` Stephane Eranian 2014-11-04 13:20 ` Peter Zijlstra 0 siblings, 1 reply; 22+ messages in thread From: Stephane Eranian @ 2014-11-04 13:14 UTC (permalink / raw) To: Peter Zijlstra; +Cc: Andi Kleen, LKML, Ingo Molnar, Andi Kleen Hi, What's happening with Broadwell support? I don't see any support in 3.18-rc2. We need this ASAP now. On Mon, Sep 1, 2014 at 3:51 PM, Peter Zijlstra <peterz@infradead.org> wrote: > On Mon, Aug 25, 2014 at 03:43:29PM -0700, Andi Kleen wrote: > >> + case 61: /* Broadwell Client */ > > Again, no other description has "Client" in. ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/5] perf, x86: Add Broadwell core support 2014-11-04 13:14 ` Stephane Eranian @ 2014-11-04 13:20 ` Peter Zijlstra 0 siblings, 0 replies; 22+ messages in thread From: Peter Zijlstra @ 2014-11-04 13:20 UTC (permalink / raw) To: Stephane Eranian; +Cc: Andi Kleen, LKML, Ingo Molnar, Andi Kleen On Tue, Nov 04, 2014 at 02:14:59PM +0100, Stephane Eranian wrote: > What's happening with Broadwell support? > I don't see any support in 3.18-rc2. We need > this ASAP now. lkml.kernel.org/r/tip-1776b10627e486dd431fe72d8d47e5a865cf65d1@git.kernel.org ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds 2014-08-25 22:43 Broadwell perf support Andi Kleen ` (2 preceding siblings ...) 2014-08-25 22:43 ` [PATCH 3/5] perf, x86: Add Broadwell core support Andi Kleen @ 2014-08-25 22:43 ` Andi Kleen 2014-09-01 13:41 ` Peter Zijlstra 2014-08-25 22:43 ` [PATCH 5/5] perf, x86: Use Broadwell cache event list for Haswell Andi Kleen 4 siblings, 1 reply; 22+ messages in thread From: Andi Kleen @ 2014-08-25 22:43 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, mingo, eranian, Andi Kleen From: Andi Kleen <ak@linux.intel.com> On Broadwell INST_RETIRED.ALL cannot be used with any period that doesn't have the lowest 6 bits cleared. And the period should not be smaller than 128. Add a new callback to enforce this, and set it for Broadwell. This is erratum BDM57 and BDM11. v2: Use correct event name in description. Use EVENT() macro. v3: Use INTEL_ARCH_EVENT_MASK. Error out for events with too small period. Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event.c | 9 +++++++++ arch/x86/kernel/cpu/perf_event.h | 1 + arch/x86/kernel/cpu/perf_event_intel.c | 19 +++++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index 0adc5e3..a6e4724 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c @@ -443,6 +443,12 @@ int x86_pmu_hw_config(struct perf_event *event) if (event->attr.type == PERF_TYPE_RAW) event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; + if (event->attr.sample_period && x86_pmu.limit_period) { + if (x86_pmu.limit_period(event, event->attr.sample_period) > + event->attr.sample_period) + return -EINVAL; + } + return x86_setup_perfctr(event); } @@ -980,6 +986,9 @@ int x86_perf_event_set_period(struct perf_event *event) if (left > x86_pmu.max_period) left = x86_pmu.max_period; + if (x86_pmu.limit_period) + left = x86_pmu.limit_period(event, left); + per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; /* diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h index de81627..a46e391 100644 --- a/arch/x86/kernel/cpu/perf_event.h +++ b/arch/x86/kernel/cpu/perf_event.h @@ -456,6 +456,7 @@ struct x86_pmu { struct x86_pmu_quirk *quirks; int perfctr_second_write; bool late_ack; + unsigned (*limit_period)(struct perf_event *event, unsigned l); /* * sysfs attrs diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 1cca4ae..53bd98d 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2034,6 +2034,24 @@ hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) return c; } +/* + * Broadwell: + * The INST_RETIRED.ALL period always needs to have lowest + * 6bits cleared (BDM57). It shall not use a period smaller + * than 100 (BDM11). We combine the two to enforce + * a min-period of 128. + */ +static unsigned bdw_limit_period(struct perf_event *event, unsigned left) +{ + if ((event->hw.config & INTEL_ARCH_EVENT_MASK) == + X86_CONFIG(.event=0xc0, .umask=0x01)) { + if (left < 128) + left = 128; + left &= ~0x3fu; + } + return left; +} + PMU_FORMAT_ATTR(event, "config:0-7" ); PMU_FORMAT_ATTR(umask, "config:8-15" ); PMU_FORMAT_ATTR(edge, "config:18" ); @@ -2712,6 +2730,7 @@ __init int intel_pmu_init(void) x86_pmu.hw_config = hsw_hw_config; x86_pmu.get_event_constraints = hsw_get_event_constraints; x86_pmu.cpu_events = hsw_events_attrs; + x86_pmu.limit_period = bdw_limit_period; pr_cont("Broadwell events, "); break; -- 1.9.3 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds 2014-08-25 22:43 ` [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds Andi Kleen @ 2014-09-01 13:41 ` Peter Zijlstra 0 siblings, 0 replies; 22+ messages in thread From: Peter Zijlstra @ 2014-09-01 13:41 UTC (permalink / raw) To: Andi Kleen; +Cc: linux-kernel, mingo, eranian, Andi Kleen On Mon, Aug 25, 2014 at 03:43:30PM -0700, Andi Kleen wrote: > From: Andi Kleen <ak@linux.intel.com> > > On Broadwell INST_RETIRED.ALL cannot be used with any period > that doesn't have the lowest 6 bits cleared. And the period > should not be smaller than 128. > > Add a new callback to enforce this, and set it for Broadwell. > > This is erratum BDM57 and BDM11. This changelog could do with more words on the solution, esp. such that you answer Stephanes question. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 5/5] perf, x86: Use Broadwell cache event list for Haswell 2014-08-25 22:43 Broadwell perf support Andi Kleen ` (3 preceding siblings ...) 2014-08-25 22:43 ` [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds Andi Kleen @ 2014-08-25 22:43 ` Andi Kleen 2014-09-01 13:52 ` Peter Zijlstra 4 siblings, 1 reply; 22+ messages in thread From: Andi Kleen @ 2014-08-25 22:43 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, mingo, eranian, Andi Kleen From: Andi Kleen <ak@linux.intel.com> Use the newly added Broadwell cache event list for Haswell too. They are identical, but Haswell is very different from the Sandy Bridge list that was used previously. That fixes a wide range of mis-counting cache events. The node events are now only for retired memory events. The prefetch events are gone now. They way the hardware counts them is very misleading (some prefetches included, others not), so it seemed best to leave them out. Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 53bd98d..190b29e 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2692,8 +2692,8 @@ __init int intel_pmu_init(void) case 63: /* 22nm Haswell Server */ case 69: /* 22nm Haswell ULT */ x86_pmu.late_ack = true; - memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); - memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); + memcpy(hw_cache_event_ids, bdw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); + memcpy(hw_cache_extra_regs, bdw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); intel_pmu_lbr_init_snb(); -- 1.9.3 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 5/5] perf, x86: Use Broadwell cache event list for Haswell 2014-08-25 22:43 ` [PATCH 5/5] perf, x86: Use Broadwell cache event list for Haswell Andi Kleen @ 2014-09-01 13:52 ` Peter Zijlstra 0 siblings, 0 replies; 22+ messages in thread From: Peter Zijlstra @ 2014-09-01 13:52 UTC (permalink / raw) To: Andi Kleen; +Cc: linux-kernel, mingo, eranian, Andi Kleen On Mon, Aug 25, 2014 at 03:43:31PM -0700, Andi Kleen wrote: > From: Andi Kleen <ak@linux.intel.com> > > Use the newly added Broadwell cache event list for Haswell too. > They are identical, but Haswell is very different from the Sandy Bridge > list that was used previously. That fixes a wide range of mis-counting > cache events. > > The node events are now only for retired memory events. > > The prefetch events are gone now. They way the hardware counts > them is very misleading (some prefetches included, others not), so > it seemed best to leave them out. > > Signed-off-by: Andi Kleen <ak@linux.intel.com> > --- > arch/x86/kernel/cpu/perf_event_intel.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c > index 53bd98d..190b29e 100644 > --- a/arch/x86/kernel/cpu/perf_event_intel.c > +++ b/arch/x86/kernel/cpu/perf_event_intel.c > @@ -2692,8 +2692,8 @@ __init int intel_pmu_init(void) > case 63: /* 22nm Haswell Server */ > case 69: /* 22nm Haswell ULT */ > x86_pmu.late_ack = true; > - memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); > - memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); > + memcpy(hw_cache_event_ids, bdw_hw_cache_event_ids, sizeof(hw_cache_event_ids)); > + memcpy(hw_cache_extra_regs, bdw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); We name things for the earliest chip they're valid for. This means this is inconsistent and 'wrong'. These tables should be called after haswell not broadwell. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf @ 2014-09-02 18:44 Andi Kleen 2014-09-18 22:42 ` Peter Zijlstra 0 siblings, 1 reply; 22+ messages in thread From: Andi Kleen @ 2014-09-02 18:44 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, mingo, eranian, tglx, Andi Kleen From: Andi Kleen <ak@linux.intel.com> 71 is a Broadwell, not a Haswell. The model number was added by mistake earlier. Remove it for now, until it can be re-added later with real Broadwell support. In practice it does not cause a lot of issues because the Broadwell PMU is very similar to Haswell, but some details were wrong, and it's better to handle it correctly. Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 89bc750..f962e26 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2544,7 +2544,6 @@ __init int intel_pmu_init(void) case 63: case 69: case 70: - case 71: x86_pmu.late_ack = true; memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); -- 1.9.3 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf 2014-09-02 18:44 [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen @ 2014-09-18 22:42 ` Peter Zijlstra 0 siblings, 0 replies; 22+ messages in thread From: Peter Zijlstra @ 2014-09-18 22:42 UTC (permalink / raw) To: Andi Kleen; +Cc: linux-kernel, mingo, eranian, tglx, Andi Kleen Thanks Andi ^ permalink raw reply [flat|nested] 22+ messages in thread
* perf, x86: Updated Broadwell patchkit @ 2014-08-27 21:03 Andi Kleen 2014-08-27 21:03 ` [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen 0 siblings, 1 reply; 22+ messages in thread From: Andi Kleen @ 2014-08-27 21:03 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, mingo, eranian, tglx Only minor changes to the last version. The Broadwell model number patch now has a more expansive change log and does not reorder case statements anymore. Some minor updates to commit logs. ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf 2014-08-27 21:03 perf, x86: Updated Broadwell patchkit Andi Kleen @ 2014-08-27 21:03 ` Andi Kleen 0 siblings, 0 replies; 22+ messages in thread From: Andi Kleen @ 2014-08-27 21:03 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, mingo, eranian, tglx, Andi Kleen From: Andi Kleen <ak@linux.intel.com> 71 is a Broadwell, not a Haswell. The model number was added by mistake earlier. Remove it for now, until it can be re-added later with real Broadwell support. In practice it does not cause a lot of issues because the Broadwell PMU is very similar to Haswell, but some details were wrong, and it's better to handle it correctly. Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 89bc750..f962e26 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2544,7 +2544,6 @@ __init int intel_pmu_init(void) case 63: case 69: case 70: - case 71: x86_pmu.late_ack = true; memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs)); -- 1.9.3 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Updated Broadwell perf patchkit @ 2014-08-14 1:17 Andi Kleen 2014-08-14 1:17 ` [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen 0 siblings, 1 reply; 22+ messages in thread From: Andi Kleen @ 2014-08-14 1:17 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, mingo, eranian Addressed the earlier review feedback. Also changed Haswell to use the Broadwell cache event list, which is far more correct for it than Sandy Bridge's. -Andi ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf 2014-08-14 1:17 Updated Broadwell perf patchkit Andi Kleen @ 2014-08-14 1:17 ` Andi Kleen 0 siblings, 0 replies; 22+ messages in thread From: Andi Kleen @ 2014-08-14 1:17 UTC (permalink / raw) To: peterz; +Cc: linux-kernel, mingo, eranian, Andi Kleen From: Andi Kleen <ak@linux.intel.com> Signed-off-by: Andi Kleen <ak@linux.intel.com> --- arch/x86/kernel/cpu/perf_event_intel.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 2502d0d..ef6c8b7 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2541,7 +2541,6 @@ __init int intel_pmu_init(void) case 60: /* Haswell Client */ case 70: - case 71: case 63: case 69: x86_pmu.late_ack = true; -- 1.9.3 ^ permalink raw reply related [flat|nested] 22+ messages in thread
end of thread, other threads:[~2014-11-04 13:20 UTC | newest] Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2014-08-25 22:43 Broadwell perf support Andi Kleen 2014-08-25 22:43 ` [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen 2014-08-26 21:27 ` Thomas Gleixner 2014-08-26 21:29 ` Andi Kleen 2014-08-26 22:29 ` Thomas Gleixner 2014-08-27 9:53 ` Thomas Gleixner 2014-08-27 16:37 ` Andi Kleen 2014-08-27 18:50 ` Thomas Gleixner 2014-08-25 22:43 ` [PATCH 2/5] perf, x86: Document all Haswell models Andi Kleen 2014-09-01 13:50 ` Peter Zijlstra 2014-08-25 22:43 ` [PATCH 3/5] perf, x86: Add Broadwell core support Andi Kleen 2014-09-01 13:51 ` Peter Zijlstra 2014-11-04 13:14 ` Stephane Eranian 2014-11-04 13:20 ` Peter Zijlstra 2014-08-25 22:43 ` [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds Andi Kleen 2014-09-01 13:41 ` Peter Zijlstra 2014-08-25 22:43 ` [PATCH 5/5] perf, x86: Use Broadwell cache event list for Haswell Andi Kleen 2014-09-01 13:52 ` Peter Zijlstra -- strict thread matches above, loose matches on Subject: below -- 2014-09-02 18:44 [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen 2014-09-18 22:42 ` Peter Zijlstra 2014-08-27 21:03 perf, x86: Updated Broadwell patchkit Andi Kleen 2014-08-27 21:03 ` [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen 2014-08-14 1:17 Updated Broadwell perf patchkit Andi Kleen 2014-08-14 1:17 ` [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen
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