RE: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit

[Thomas Gleixner <tglx@linutronix.de>]

On Fri, 4 Nov 2016, Andrejczuk, Grzegorz wrote:
> >>On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
> >>  
> >> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
> >
> > Oh well. I asked you to make that whole PHI thing go away. 
> >
> > This is a feature which has nothing to do with PHI. It just happens to
> > be implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI
> > specific.
> > It's all about a feature which enables ring 3 mwait/monitor.
> 
> This bit enables ring 3 MONITOR/MWAIT only on Xeon Phi. It is reserved
> for other architectures.  I think this will be confusing when I remove
> PHI.

It's reserved for other models simply because they do not implement it.

PHI is nothing special and the MSR is not PHI specific at all. It's used
for other features on other models, e.g. CPUID faulting (bit 0). That's
why PHI got bit 1.

Intel has so far been very consistent with MSRs which are implemented on
different models and it would be highly surprising if they would use a
different MSR/BIT when they bring that ring3 mwait feature to other models
than PHI. We make it PHI special when that happens, but for now there is
nothing PHI special, except that the only model which implements this is
PHI at the moment.

Thanks,

	tglx