From: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org
Cc: bp@suse.de, dave.hansen@linux.intel.com,
lukasz.daniluk@intel.com, james.h.cownie@intel.com,
jacob.jun.pan@intel.com, Piotr.Luc@intel.com,
linux-kernel@vger.kernel.org,
Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Subject: [PATCH v8 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features
Date: Thu, 3 Nov 2016 17:01:35 +0100 [thread overview]
Message-ID: <1478188895-13001-1-git-send-email-grzegorz.andrejczuk@intel.com> (raw)
In-Reply-To: <20161103145650.kl7glxcfatad5ium@pd.tnic>
Add Intel Xeon Phi x200 (KnightsLanding) CPU feature - ring 3 MONITOR/MWAIT.
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
arch/x86/include/asm/cpufeatures.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 92a8308..98414c5 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -100,7 +100,7 @@
#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
-/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
+#define X86_FEATURE_PHIR3MWAIT ( 3*32+25) /* Xeon Phi x200 ring 3 MONITOR/MWAIT */
#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
--
2.5.1
next prev parent reply other threads:[~2016-11-03 16:02 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-01 10:14 [PATCH v8: 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Grzegorz Andrejczuk
2016-11-03 14:54 ` Borislav Petkov
2016-11-03 17:00 ` Thomas Gleixner
2016-11-04 6:47 ` Andrejczuk, Grzegorz
2016-11-07 20:48 ` Thomas Gleixner
2016-11-01 10:14 ` [PATCH v8: 2/4] x86/elf: Use HWCAP2 to expose ring 3 MWAIT Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk
2016-11-03 14:56 ` Borislav Petkov
2016-11-03 16:01 ` Grzegorz Andrejczuk [this message]
2016-11-01 10:14 ` [PATCH v8: 4/4] x86/cpufeatures: Handle RING3MWAIT on Xeon Phi models Grzegorz Andrejczuk
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1478188895-13001-1-git-send-email-grzegorz.andrejczuk@intel.com \
--to=grzegorz.andrejczuk@intel.com \
--cc=Piotr.Luc@intel.com \
--cc=bp@suse.de \
--cc=dave.hansen@linux.intel.com \
--cc=hpa@zytor.com \
--cc=jacob.jun.pan@intel.com \
--cc=james.h.cownie@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=lukasz.daniluk@intel.com \
--cc=mingo@redhat.com \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).