From: Marc Zyngier <maz@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>
Cc: <tglx@linutronix.de>, <jason@lakedaemon.net>,
Christoph Hellwig <hch@lst.de>,
Palmer Dabbelt <palmer@sifive.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 01/12] riscv: abstract out CSR names for supervisor vs machine mode
Date: Tue, 05 Nov 2019 19:11:09 +0109 [thread overview]
Message-ID: <b1e60fb42bc057e9901187bb866b7077@www.loen.fr> (raw)
In-Reply-To: <alpine.DEB.2.21.9999.1911050956230.20606@viisi.sifive.com>
Hi Paul,
On 2019-11-05 19:06, Paul Walmsley wrote:
> Jason, Marc, Thomas,
>
> On Mon, 28 Oct 2019, Christoph Hellwig wrote:
>
>> Many of the privileged CSRs exist in a supervisor and machine
>> version
>> that are used very similarly. Provide versions of the CSR names and
>> fields that map to either the S-mode or M-mode variant depending on
>> a new CONFIG_RISCV_M_MODE kconfig symbol.
>>
>> Contains contributions from Damien Le Moal <Damien.LeMoal@wdc.com>
>> and Paul Walmsley <paul.walmsley@sifive.com>.
>>
>> Signed-off-by: Christoph Hellwig <hch@lst.de>
>
> Care to give a quick ack to the drivers/irqchip changes?
Sure, see below.
>
>
> thanks,
>
> - Paul
>
>
>> ---
>> arch/riscv/Kconfig | 4 ++
>> arch/riscv/include/asm/csr.h | 72
>> +++++++++++++++++++++++++----
>> arch/riscv/include/asm/irqflags.h | 12 ++---
>> arch/riscv/include/asm/processor.h | 2 +-
>> arch/riscv/include/asm/ptrace.h | 16 +++----
>> arch/riscv/include/asm/switch_to.h | 10 ++--
>> arch/riscv/kernel/asm-offsets.c | 8 ++--
>> arch/riscv/kernel/entry.S | 74
>> +++++++++++++++++-------------
>> arch/riscv/kernel/fpu.S | 8 ++--
>> arch/riscv/kernel/head.S | 12 ++---
>> arch/riscv/kernel/irq.c | 17 ++-----
>> arch/riscv/kernel/perf_callchain.c | 2 +-
>> arch/riscv/kernel/process.c | 17 +++----
>> arch/riscv/kernel/signal.c | 21 ++++-----
>> arch/riscv/kernel/smp.c | 2 +-
>> arch/riscv/kernel/traps.c | 16 +++----
>> arch/riscv/lib/uaccess.S | 12 ++---
>> arch/riscv/mm/extable.c | 4 +-
>> arch/riscv/mm/fault.c | 6 +--
>> drivers/clocksource/timer-riscv.c | 8 ++--
>> drivers/irqchip/irq-sifive-plic.c | 11 +++--
>> 21 files changed, 199 insertions(+), 135 deletions(-)
[...]
>> diff --git a/drivers/irqchip/irq-sifive-plic.c
>> b/drivers/irqchip/irq-sifive-plic.c
>> index 7d0a12fe2714..8df547d2d935 100644
>> --- a/drivers/irqchip/irq-sifive-plic.c
>> +++ b/drivers/irqchip/irq-sifive-plic.c
>> @@ -181,7 +181,7 @@ static void plic_handle_irq(struct pt_regs
>> *regs)
>>
>> WARN_ON_ONCE(!handler->present);
>>
>> - csr_clear(sie, SIE_SEIE);
>> + csr_clear(CSR_IE, IE_EIE);
>> while ((hwirq = readl(claim))) {
>> int irq = irq_find_mapping(plic_irqdomain, hwirq);
>>
>> @@ -191,7 +191,7 @@ static void plic_handle_irq(struct pt_regs
>> *regs)
>> else
>> generic_handle_irq(irq);
>> }
>> - csr_set(sie, SIE_SEIE);
>> + csr_set(CSR_IE, IE_EIE);
>> }
>>
>> /*
>> @@ -252,8 +252,11 @@ static int __init plic_init(struct device_node
>> *node,
>> continue;
>> }
>>
>> - /* skip contexts other than supervisor external interrupt */
>> - if (parent.args[0] != IRQ_S_EXT)
>> + /*
>> + * Skip contexts other than external interrupts for our
>> + * privilege level.
>> + */
>> + if (parent.args[0] != IRQ_EXT)
>> continue;
>>
>> hartid = plic_find_hart_id(parent.np);
For changes to this file:
Acked-by: Marc Zyngier <maz@kernel.org>
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2019-11-05 18:01 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 12:10 RISC-V nommu support v6 Christoph Hellwig
2019-10-28 12:10 ` [PATCH 01/12] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-11-05 17:56 ` Paul Walmsley
2019-11-05 17:57 ` Paul Walmsley
2019-11-05 18:02 ` Marc Zyngier [this message]
2019-11-12 10:38 ` Thomas Gleixner
2019-11-14 7:30 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 02/12] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-11-14 7:31 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 03/12] riscv: poison SBI calls " Christoph Hellwig
2019-10-31 23:55 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 04/12] riscv: cleanup the default power off implementation Christoph Hellwig
2019-10-31 20:49 ` Paul Walmsley
2019-10-31 23:56 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 05/12] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-10-31 23:57 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 06/12] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-11-05 18:01 ` Paul Walmsley
2019-11-12 10:39 ` Thomas Gleixner
2019-11-17 23:06 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 07/12] riscv: provide native clint access for M-mode Christoph Hellwig
2019-10-28 12:10 ` [PATCH 08/12] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-10-28 12:10 ` [PATCH 09/12] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-11-14 7:45 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 10/12] riscv: add nommu support Christoph Hellwig
2019-11-17 23:13 ` Paul Walmsley
2019-12-16 22:03 ` David Abdurachmanov
2019-12-17 3:18 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 11/12] riscv: provide a flat image loader Christoph Hellwig
2019-11-17 23:14 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 12/12] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-10-30 20:21 ` RISC-V nommu support v6 Paul Walmsley
2019-10-31 15:52 ` Christoph Hellwig
2019-10-31 20:13 ` Paul Walmsley
2019-11-23 2:19 ` Paul Walmsley
2019-12-11 8:42 ` Greentime Hu
2020-02-12 12:19 ` Greentime Hu
2019-11-11 9:47 ` Christoph Hellwig
2019-11-11 17:02 ` Paul Walmsley
2019-11-13 13:18 ` Christoph Hellwig
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