From: Sudeep Holla <sudeep.holla@arm.com>
To: Jeremy Linton <jeremy.linton@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>,
linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com,
rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com,
gregkh@linuxfoundation.org, viresh.kumar@linaro.org,
mark.rutland@arm.com, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, jhugo@codeaurora.org,
wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com,
ahs3@redhat.com, Jayachandran.Nair@cavium.com,
austinwc@codeaurora.org, lenb@kernel.org, vkilari@codeaurora.org,
morten.rasmussen@arm.com, Palmer Dabbelt <palmer@sifive.com>,
Albert Ou <albert@sifive.com>
Subject: Re: [PATCH v6 02/12] drivers: base: cacheinfo: setup DT cache properties early
Date: Wed, 17 Jan 2018 18:20:25 +0000 [thread overview]
Message-ID: <ca64334c-9345-705c-80d8-f2deb924a679@arm.com> (raw)
In-Reply-To: <65f78c99-8b86-0098-7ced-899840a4bf16@arm.com>
On 16/01/18 21:07, Jeremy Linton wrote:
> Hi,
>
> On 01/15/2018 06:33 AM, Sudeep Holla wrote:
>> On Fri, Jan 12, 2018 at 06:59:10PM -0600, Jeremy Linton wrote:
>>> The original intent in cacheinfo was that an architecture
>>> specific populate_cache_leaves() would probe the hardware
>>> and then cache_shared_cpu_map_setup() and
>>> cache_override_properties() would provide firmware help to
>>> extend/expand upon what was probed. Arm64 was really
>>> the only architecture that was working this way, and
>>> with the removal of most of the hardware probing logic it
>>> became clear that it was possible to simplify the logic a bit.
>>>
>>> This patch combines the walk of the DT nodes with the
>>> code updating the cache size/line_size and nr_sets.
>>> cache_override_properties() (which was DT specific) is
>>> then removed. The result is that cacheinfo.of_node is
>>> no longer used as a temporary place to hold DT references
>>> for future calls that update cache properties. That change
>>> helps to clarify its one remaining use (matching
>>> cacheinfo nodes that represent shared caches) which
>>> will be used by the ACPI/PPTT code in the following patches.
>>>
>>> Cc: Palmer Dabbelt <palmer@sifive.com>
>>> Cc: Albert Ou <albert@sifive.com>
>>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>>> ---
>>> arch/riscv/kernel/cacheinfo.c | 1 +
>>> drivers/base/cacheinfo.c | 65
>>> +++++++++++++++++++------------------------
>>> include/linux/cacheinfo.h | 1 +
>>> 3 files changed, 31 insertions(+), 36 deletions(-)
>>>
>>> diff --git a/arch/riscv/kernel/cacheinfo.c
>>> b/arch/riscv/kernel/cacheinfo.c
>>> index 10ed2749e246..6f4500233cf8 100644
>>> --- a/arch/riscv/kernel/cacheinfo.c
>>> +++ b/arch/riscv/kernel/cacheinfo.c
>>> @@ -30,6 +30,7 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
>>> CACHE_WRITE_BACK
>>> | CACHE_READ_ALLOCATE
>>> | CACHE_WRITE_ALLOCATE;
>>> + cache_of_set_props(this_leaf, node);
>>
>> This may be necessary but can it be done as later patch ? So far nothing
>> is added that may break riscv IIUC.
>
> Well I think you have a bisection issue where the additional information
> will disappear between this patch and wherever we put this code back in.
>
Hmm, I am sorry but I fail to see the issue. Before this change,
populate_cache_leaves just populated the info as per ci_leaf_init in
arch/riscv/kernel/cacheinfo.c and cache_override_properties used to fill
the remaining.
After this patch, the same is achieved in cache_shared_cpu_map_setup.
In both case, it was by the end of detect_cache_attributes, so I see no
issue.
--
Regards,
Sudeep
next prev parent reply other threads:[~2018-01-17 18:20 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-13 0:59 [PATCH v6 00/12] Support PPTT for ARM64 Jeremy Linton
2018-01-13 0:59 ` [PATCH v6 01/12] drivers: base: cacheinfo: move cache_setup_of_node() Jeremy Linton
2018-01-15 12:23 ` Sudeep Holla
2018-01-13 0:59 ` [PATCH v6 02/12] drivers: base: cacheinfo: setup DT cache properties early Jeremy Linton
2018-01-15 12:33 ` Sudeep Holla
2018-01-15 16:07 ` Palmer Dabbelt
2018-01-16 21:26 ` Jeremy Linton
2018-01-17 18:08 ` Sudeep Holla
2018-01-18 17:36 ` Palmer Dabbelt
2018-01-16 21:07 ` Jeremy Linton
2018-01-17 18:20 ` Sudeep Holla [this message]
2018-01-17 18:51 ` Jeremy Linton
2018-01-18 10:14 ` Sudeep Holla
2018-01-19 23:27 ` Jeremy Linton
2018-01-13 0:59 ` [PATCH v6 03/12] cacheinfo: rename of_node to fw_unique Jeremy Linton
2018-01-15 12:36 ` Sudeep Holla
2018-01-13 0:59 ` [PATCH v6 04/12] arm64/acpi: Create arch specific cpu to acpi id helper Jeremy Linton
2018-01-15 13:46 ` Sudeep Holla
2018-01-13 0:59 ` [PATCH v6 05/12] ACPI/PPTT: Add Processor Properties Topology Table parsing Jeremy Linton
2018-01-15 14:58 ` Sudeep Holla
2018-01-16 20:55 ` Jeremy Linton
2018-01-17 17:58 ` Sudeep Holla
2018-01-15 15:48 ` Sudeep Holla
2018-01-16 20:22 ` Jeremy Linton
2018-01-17 18:00 ` Sudeep Holla
2018-01-13 0:59 ` [PATCH v6 06/12] ACPI: Enable PPTT support on ARM64 Jeremy Linton
2018-01-15 13:52 ` Sudeep Holla
2018-01-13 0:59 ` [PATCH v6 07/12] drivers: base cacheinfo: Add support for ACPI based firmware tables Jeremy Linton
2018-01-15 15:06 ` Sudeep Holla
2018-01-22 15:50 ` Greg KH
2018-01-22 21:14 ` Jeremy Linton
2018-01-23 0:11 ` Rafael J. Wysocki
2018-01-13 0:59 ` [PATCH v6 08/12] arm64: " Jeremy Linton
2018-01-15 13:54 ` Sudeep Holla
2018-01-13 0:59 ` [PATCH v6 09/12] ACPI/PPTT: Add topology parsing code Jeremy Linton
2018-01-13 0:59 ` [PATCH v6 10/12] arm64: topology: rename cluster_id Jeremy Linton
2018-01-13 0:59 ` [PATCH v6 11/12] arm64: topology: enable ACPI/PPTT based CPU topology Jeremy Linton
2018-01-25 12:15 ` Xiongfeng Wang
2018-01-25 15:56 ` Jeremy Linton
2018-01-26 4:21 ` Xiongfeng Wang
2018-02-23 11:02 ` Lorenzo Pieralisi
2018-02-24 3:05 ` Xiongfeng Wang
2018-02-25 6:17 ` vkilari
2018-03-01 14:19 ` Morten Rasmussen
2018-02-24 4:37 ` Jeremy Linton
2018-03-01 11:51 ` Morten Rasmussen
2018-01-13 0:59 ` [PATCH v6 12/12] ACPI: Add PPTT to injectable table list Jeremy Linton
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