* [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI
2014-09-09 9:13 [PATCH V1 0/3] refine the ssi clock for imx6sl, and update dts file Shengjiu Wang
@ 2014-09-09 9:13 ` Shengjiu Wang
2014-09-12 16:35 ` Fabio Estevam
2014-09-09 9:13 ` [PATCH V1 2/3] ARM: dts: imx6qdl: add baud clock and clock-names for ssi Shengjiu Wang
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Shengjiu Wang @ 2014-09-09 9:13 UTC (permalink / raw)
To: shawn.guo, kernel, linux, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak
Cc: shengjiu.wang, linux-arm-kernel, linux-kernel
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
arch/arm/mach-imx/clk-imx6sl.c | 13 ++++++++++---
include/dt-bindings/clock/imx6sl-clock.h | 5 ++++-
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 6791ff3..c8de87b 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -95,6 +95,10 @@ static struct clk_div_table video_div_table[] = {
{ }
};
+static unsigned int share_count_ssi1;
+static unsigned int share_count_ssi2;
+static unsigned int share_count_ssi3;
+
static struct clk *clks[IMX6SL_CLK_END];
static struct clk_onecell_data clk_data;
static void __iomem *ccm_base;
@@ -392,9 +396,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
- clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
- clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
- clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
+ clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
+ clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
+ clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
+ clks[IMX6SL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
+ clks[IMX6SL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
+ clks[IMX6SL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24);
clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26);
clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
index f10a928..9ce4e42 100644
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -171,6 +171,9 @@
#define IMX6SL_PLL5_BYPASS 158
#define IMX6SL_PLL6_BYPASS 159
#define IMX6SL_PLL7_BYPASS 160
-#define IMX6SL_CLK_END 161
+#define IMX6SL_CLK_SSI1_IPG 161
+#define IMX6SL_CLK_SSI2_IPG 162
+#define IMX6SL_CLK_SSI3_IPG 163
+#define IMX6SL_CLK_END 164
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI
2014-09-09 9:13 ` [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI Shengjiu Wang
@ 2014-09-12 16:35 ` Fabio Estevam
2014-09-12 16:43 ` Fabio Estevam
0 siblings, 1 reply; 10+ messages in thread
From: Fabio Estevam @ 2014-09-12 16:35 UTC (permalink / raw)
To: Shengjiu Wang
Cc: Shawn Guo, Sascha Hauer, Russell King, robh+dt, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, linux-kernel,
linux-arm-kernel
On Tue, Sep 9, 2014 at 6:13 AM, Shengjiu Wang
<shengjiu.wang@freescale.com> wrote:
> Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
This patch breaks audio playback on imx6q-sabresd:
root@freescale /$ aplay /home/clarinet.wav
Playing WAVE '/home/clarinet.wav' : Signed 16 bit Little Endian, Rate 44100 Hz,
Mono
underrun!!! (at least -1585992.581 ms long)
underrun!!! (at least -1585992.585 ms long)
underrun!!! (at least -1585992.586 ms long)
underrun!!! (at least -1585992.586 ms long)
underrun!!! (at least -1585992.586 ms long)
underrun!!! (at least -1585992.586 ms long)
underrun!!! (at least -1585992.586 ms long)
underrun!!! (at least -1585992.586 ms long)
underrun!!! (at least -1585992.586 ms long)
underrun!!! (at least -1585992.586 ms long)
If I revert this commit, then I am able to play it well again.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI
2014-09-12 16:35 ` Fabio Estevam
@ 2014-09-12 16:43 ` Fabio Estevam
2014-09-15 11:58 ` Shengjiu Wang
0 siblings, 1 reply; 10+ messages in thread
From: Fabio Estevam @ 2014-09-12 16:43 UTC (permalink / raw)
To: Shengjiu Wang
Cc: Shawn Guo, Sascha Hauer, Russell King, robh+dt, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, linux-kernel,
linux-arm-kernel
On Fri, Sep 12, 2014 at 1:35 PM, Fabio Estevam <festevam@gmail.com> wrote:
> On Tue, Sep 9, 2014 at 6:13 AM, Shengjiu Wang
> <shengjiu.wang@freescale.com> wrote:
>> Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
>>
>> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
>
> This patch breaks audio playback on imx6q-sabresd:
>
> root@freescale /$ aplay /home/clarinet.wav
> Playing WAVE '/home/clarinet.wav' : Signed 16 bit Little Endian, Rate 44100 Hz,
> Mono
> underrun!!! (at least -1585992.581 ms long)
> underrun!!! (at least -1585992.585 ms long)
> underrun!!! (at least -1585992.586 ms long)
> underrun!!! (at least -1585992.586 ms long)
> underrun!!! (at least -1585992.586 ms long)
> underrun!!! (at least -1585992.586 ms long)
> underrun!!! (at least -1585992.586 ms long)
> underrun!!! (at least -1585992.586 ms long)
> underrun!!! (at least -1585992.586 ms long)
> underrun!!! (at least -1585992.586 ms long)
>
> If I revert this commit, then I am able to play it well again.
Ops, I replied in the wrong patch.
The one that breaks imx6q-sabresd is:
commit 48e1c2255 "ARM: clk-imx6q: refine clock tree for SSI"
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI
2014-09-12 16:43 ` Fabio Estevam
@ 2014-09-15 11:58 ` Shengjiu Wang
2014-09-15 14:48 ` Shawn Guo
0 siblings, 1 reply; 10+ messages in thread
From: Shengjiu Wang @ 2014-09-15 11:58 UTC (permalink / raw)
To: Fabio Estevam
Cc: Shawn Guo, Sascha Hauer, Russell King, robh+dt, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, linux-kernel,
linux-arm-kernel
Hi fabio, shawn.
On Fri, Sep 12, 2014 at 01:43:39PM -0300, Fabio Estevam wrote:
> On Fri, Sep 12, 2014 at 1:35 PM, Fabio Estevam <festevam@gmail.com> wrote:
> > On Tue, Sep 9, 2014 at 6:13 AM, Shengjiu Wang
> > <shengjiu.wang@freescale.com> wrote:
> >> Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
> >>
> >> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
> >
> > This patch breaks audio playback on imx6q-sabresd:
> >
> > root@freescale /$ aplay /home/clarinet.wav
> > Playing WAVE '/home/clarinet.wav' : Signed 16 bit Little Endian, Rate 44100 Hz,
> > Mono
> > underrun!!! (at least -1585992.581 ms long)
> > underrun!!! (at least -1585992.585 ms long)
> > underrun!!! (at least -1585992.586 ms long)
> > underrun!!! (at least -1585992.586 ms long)
> > underrun!!! (at least -1585992.586 ms long)
> > underrun!!! (at least -1585992.586 ms long)
> > underrun!!! (at least -1585992.586 ms long)
> > underrun!!! (at least -1585992.586 ms long)
> > underrun!!! (at least -1585992.586 ms long)
> > underrun!!! (at least -1585992.586 ms long)
> >
> > If I revert this commit, then I am able to play it well again.
>
> Ops, I replied in the wrong patch.
>
> The one that breaks imx6q-sabresd is:
>
> commit 48e1c2255 "ARM: clk-imx6q: refine clock tree for SSI"
I add IMX6QDL_CLK_SSIx in this patch, which use share count with
IMX6QDL_CLK_SSIx_IPG. The SSI driver sound/soc/fsl/fsl_ssi.c will enable
IMX6QDL_CLK_SSIx_IPG clock in probe, but don't disable it. In the end of kernel
boot up, some one(it is not ssi driver, maybe is the clock tree) will disable
the IMX6QDL_CLK_SSIx clock, which is not enabled. IMX6QDL_CLK_SSIx_IPG share
the enable/disable bit with IMX6QDL_CLK_SSIx, So IMX6QDL_CLK_SSIx_IPG is
disabled, the aplay will fail.
Is this the issue of imx_clk_gate2_shared()? When we want to disable IMX6QDL_CLK_SSIx,
but IMX6QDL_CLK_SSIx_IPG is enabled, can IMX6QDL_CLK_SSIx be disabled?
Shawn
How do you think about this?
best regards
wang shengjiu
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI
2014-09-15 11:58 ` Shengjiu Wang
@ 2014-09-15 14:48 ` Shawn Guo
2014-09-15 15:09 ` Fabio Estevam
0 siblings, 1 reply; 10+ messages in thread
From: Shawn Guo @ 2014-09-15 14:48 UTC (permalink / raw)
To: Shengjiu Wang
Cc: Fabio Estevam, Sascha Hauer, Russell King, robh+dt, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, linux-kernel,
linux-arm-kernel
On Mon, Sep 15, 2014 at 07:58:56PM +0800, Shengjiu Wang wrote:
> I add IMX6QDL_CLK_SSIx in this patch, which use share count with
> IMX6QDL_CLK_SSIx_IPG. The SSI driver sound/soc/fsl/fsl_ssi.c will enable
> IMX6QDL_CLK_SSIx_IPG clock in probe, but don't disable it. In the end of kernel
> boot up, some one(it is not ssi driver, maybe is the clock tree) will disable
> the IMX6QDL_CLK_SSIx clock, which is not enabled. IMX6QDL_CLK_SSIx_IPG share
> the enable/disable bit with IMX6QDL_CLK_SSIx, So IMX6QDL_CLK_SSIx_IPG is
> disabled, the aplay will fail.
>
> Is this the issue of imx_clk_gate2_shared()? When we want to disable IMX6QDL_CLK_SSIx,
> but IMX6QDL_CLK_SSIx_IPG is enabled, can IMX6QDL_CLK_SSIx be disabled?
>
>
> Shawn
>
> How do you think about this?
Shengjiu,
Your analysis is right. I hope the following change will get the shared
gate clock code eventually does the right thing.
Shawn
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index 84acdfd1d715..89abdf738dc9 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -97,7 +97,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
struct clk_gate2 *gate = to_clk_gate2(hw);
if (gate->share_count)
- return !!(*gate->share_count);
+ return !!__clk_get_enable_count(hw->clk);
else
return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
}
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI
2014-09-15 14:48 ` Shawn Guo
@ 2014-09-15 15:09 ` Fabio Estevam
0 siblings, 0 replies; 10+ messages in thread
From: Fabio Estevam @ 2014-09-15 15:09 UTC (permalink / raw)
To: Shawn Guo
Cc: Shengjiu Wang, Sascha Hauer, Russell King, robh+dt, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, linux-kernel,
linux-arm-kernel
On Mon, Sep 15, 2014 at 11:48 AM, Shawn Guo <shawn.guo@freescale.com> wrote:
> Shengjiu,
>
> Your analysis is right. I hope the following change will get the shared
> gate clock code eventually does the right thing.
>
> Shawn
>
> diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
> index 84acdfd1d715..89abdf738dc9 100644
> --- a/arch/arm/mach-imx/clk-gate2.c
> +++ b/arch/arm/mach-imx/clk-gate2.c
> @@ -97,7 +97,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw)
> struct clk_gate2 *gate = to_clk_gate2(hw);
>
> if (gate->share_count)
> - return !!(*gate->share_count);
> + return !!__clk_get_enable_count(hw->clk);
> else
> return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
This fixes the audio playback, thanks. Tested on a mx6qsabresd and
also on mx6sx sdb:
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH V1 2/3] ARM: dts: imx6qdl: add baud clock and clock-names for ssi
2014-09-09 9:13 [PATCH V1 0/3] refine the ssi clock for imx6sl, and update dts file Shengjiu Wang
2014-09-09 9:13 ` [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI Shengjiu Wang
@ 2014-09-09 9:13 ` Shengjiu Wang
2014-09-09 9:13 ` [PATCH V1 3/3] ARM: dts: imx6sl: " Shengjiu Wang
2014-09-10 3:10 ` [PATCH V1 0/3] refine the ssi clock for imx6sl, and update dts file Shawn Guo
3 siblings, 0 replies; 10+ messages in thread
From: Shengjiu Wang @ 2014-09-09 9:13 UTC (permalink / raw)
To: shawn.guo, kernel, linux, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak
Cc: shengjiu.wang, linux-arm-kernel, linux-kernel
Baud clock is used for bit clock generation in master mode. Ipg clock
is peripheral clock and peripheral access clock.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 70d7207..0de8806 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -280,7 +280,9 @@
"fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
+ clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
+ <&clks IMX6QDL_CLK_SSI1>;
+ clock-names = "ipg", "baud";
dmas = <&sdma 37 1 0>,
<&sdma 38 1 0>;
dma-names = "rx", "tx";
@@ -294,7 +296,9 @@
"fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
+ clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
+ <&clks IMX6QDL_CLK_SSI2>;
+ clock-names = "ipg", "baud";
dmas = <&sdma 41 1 0>,
<&sdma 42 1 0>;
dma-names = "rx", "tx";
@@ -308,7 +312,9 @@
"fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;
+ clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
+ <&clks IMX6QDL_CLK_SSI3>;
+ clock-names = "ipg", "baud";
dmas = <&sdma 45 1 0>,
<&sdma 46 1 0>;
dma-names = "rx", "tx";
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V1 3/3] ARM: dts: imx6sl: add baud clock and clock-names for ssi
2014-09-09 9:13 [PATCH V1 0/3] refine the ssi clock for imx6sl, and update dts file Shengjiu Wang
2014-09-09 9:13 ` [PATCH V1 1/3] ARM: clk-imx6sl: refine clock tree for SSI Shengjiu Wang
2014-09-09 9:13 ` [PATCH V1 2/3] ARM: dts: imx6qdl: add baud clock and clock-names for ssi Shengjiu Wang
@ 2014-09-09 9:13 ` Shengjiu Wang
2014-09-10 3:10 ` [PATCH V1 0/3] refine the ssi clock for imx6sl, and update dts file Shawn Guo
3 siblings, 0 replies; 10+ messages in thread
From: Shengjiu Wang @ 2014-09-09 9:13 UTC (permalink / raw)
To: shawn.guo, kernel, linux, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak
Cc: shengjiu.wang, linux-arm-kernel, linux-kernel
Baud clock is used for bit clock generation in master mode. Ipg clock
is peripheral clock and peripheral access clock.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
arch/arm/boot/dts/imx6sl.dtsi | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ba67714..dfd83e6 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -231,7 +231,9 @@
"fsl,imx51-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_SSI1>;
+ clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
+ <&clks IMX6SL_CLK_SSI1>;
+ clock-names = "ipg", "baud";
dmas = <&sdma 37 1 0>,
<&sdma 38 1 0>;
dma-names = "rx", "tx";
@@ -245,7 +247,9 @@
"fsl,imx51-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_SSI2>;
+ clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
+ <&clks IMX6SL_CLK_SSI2>;
+ clock-names = "ipg", "baud";
dmas = <&sdma 41 1 0>,
<&sdma 42 1 0>;
dma-names = "rx", "tx";
@@ -259,7 +263,9 @@
"fsl,imx51-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6SL_CLK_SSI3>;
+ clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
+ <&clks IMX6SL_CLK_SSI3>;
+ clock-names = "ipg", "baud";
dmas = <&sdma 45 1 0>,
<&sdma 46 1 0>;
dma-names = "rx", "tx";
--
1.7.9.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH V1 0/3] refine the ssi clock for imx6sl, and update dts file.
2014-09-09 9:13 [PATCH V1 0/3] refine the ssi clock for imx6sl, and update dts file Shengjiu Wang
` (2 preceding siblings ...)
2014-09-09 9:13 ` [PATCH V1 3/3] ARM: dts: imx6sl: " Shengjiu Wang
@ 2014-09-10 3:10 ` Shawn Guo
3 siblings, 0 replies; 10+ messages in thread
From: Shawn Guo @ 2014-09-10 3:10 UTC (permalink / raw)
To: Shengjiu Wang
Cc: kernel, linux, robh+dt, pawel.moll, mark.rutland, ijc+devicetree,
galak, linux-arm-kernel, linux-kernel
On Tue, Sep 09, 2014 at 05:13:24PM +0800, Shengjiu Wang wrote:
> This serial patch is for refining the ssi clock tree for imx6sl,
> and update imx6qdl and imx6sl dts file.
>
> Shengjiu Wang (3):
> ARM: clk-imx6sl: refine clock tree for SSI
> ARM: dts: imx6qdl: add baud clock and clock-names for ssi
> ARM: dts: imx6sl: add baud clock and clock-names for ssi
Applied all, thanks.
^ permalink raw reply [flat|nested] 10+ messages in thread