[PATCH V2 0/5] Update pcie-tegra194 driver

[PATCH V2 0/5] Update pcie-tegra194 driver

[Om Prakash Singh]

Update pcie-tegra194 driver with bug fixing and cleanup

Changes from V1->V2
  PCI: tegra: Fix handling BME_CHGED event
	- Update variable naming
  PCI: tegra: Fix MSI-X programming
	- No change
  PCI: tegra: Disable interrupts before entering L2
	- Rephrase the commit message
  PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode
	- Update return value to -ENOTSUPP.
  PCI: tegra: Cleanup unused code
	- No Change

V1:
http://patchwork.ozlabs.org/project/linux-pci/patch/20210527115246.20509-2-omp@nvidia.com/

Om Prakash Singh (5):
  PCI: tegra: Fix handling BME_CHGED event
  PCI: tegra: Fix MSI-X programming
  PCI: tegra: Disable interrupts before entering L2
  PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode
  PCI: tegra: Cleanup unused code

 drivers/pci/controller/dwc/pcie-tegra194.c | 36 +++++++++++++---------
 1 file changed, 22 insertions(+), 14 deletions(-)

-- 
2.17.1

[PATCH V2 1/5] PCI: tegra: Fix handling BME_CHGED event

[Om Prakash Singh]

In tegra_pcie_ep_hard_irq(), APPL_INTR_STATUS_L0 is stored in val and again
APPL_INTR_STATUS_L1_0_0 is also stored in val. So when execution reaches
"if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT)", val is not correct.

Signed-off-by: Om Prakash Singh <omp@nvidia.com>
---

Changes in V2:
	- Update variable naming as per comment from Bjorn Helgaas

 drivers/pci/controller/dwc/pcie-tegra194.c | 30 +++++++++++-----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index bafd2c6ab3c2..6f388523bffe 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -615,19 +615,19 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
 	struct tegra_pcie_dw *pcie = arg;
 	struct dw_pcie_ep *ep = &pcie->pci.ep;
 	int spurious = 1;
-	u32 val, tmp;
+	u32 status_l0, status_l1, link_status;
 
-	val = appl_readl(pcie, APPL_INTR_STATUS_L0);
-	if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
-		val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
-		appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
+	status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
+	if (status_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
+		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
+		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
 
-		if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)
+		if (status_l1 & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)
 			pex_ep_event_hot_rst_done(pcie);
 
-		if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {
-			tmp = appl_readl(pcie, APPL_LINK_STATUS);
-			if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) {
+		if (status_l1 & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {
+			link_status = appl_readl(pcie, APPL_LINK_STATUS);
+			if (link_status & APPL_LINK_STATUS_RDLH_LINK_UP) {
 				dev_dbg(pcie->dev, "Link is up with Host\n");
 				dw_pcie_ep_linkup(ep);
 			}
@@ -636,11 +636,11 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
 		spurious = 0;
 	}
 
-	if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
-		val = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
-		appl_writel(pcie, val, APPL_INTR_STATUS_L1_15);
+	if (status_l0 & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
+		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
+		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15);
 
-		if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)
+		if (status_l1 & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)
 			return IRQ_WAKE_THREAD;
 
 		spurious = 0;
@@ -648,8 +648,8 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
 
 	if (spurious) {
 		dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
-			 val);
-		appl_writel(pcie, val, APPL_INTR_STATUS_L0);
+			 status_l0);
+		appl_writel(pcie, status_l0, APPL_INTR_STATUS_L0);
 	}
 
 	return IRQ_HANDLED;
-- 
2.17.1

Re: [PATCH V2 1/5] PCI: tegra: Fix handling BME_CHGED event

[Vidya Sagar]

Acked-by: Vidya Sagar <vidyas@nvidia.com>

On 6/6/2021 1:52 PM, Om Prakash Singh wrote:
> In tegra_pcie_ep_hard_irq(), APPL_INTR_STATUS_L0 is stored in val and again
> APPL_INTR_STATUS_L1_0_0 is also stored in val. So when execution reaches
> "if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT)", val is not correct.
> 
> Signed-off-by: Om Prakash Singh <omp@nvidia.com>
> ---
> 
> Changes in V2:
> 	- Update variable naming as per comment from Bjorn Helgaas
> 
>   drivers/pci/controller/dwc/pcie-tegra194.c | 30 +++++++++++-----------
>   1 file changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index bafd2c6ab3c2..6f388523bffe 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -615,19 +615,19 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>   	struct tegra_pcie_dw *pcie = arg;
>   	struct dw_pcie_ep *ep = &pcie->pci.ep;
>   	int spurious = 1;
> -	u32 val, tmp;
> +	u32 status_l0, status_l1, link_status;
>   
> -	val = appl_readl(pcie, APPL_INTR_STATUS_L0);
> -	if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
> -		val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
> -		appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
> +	status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
> +	if (status_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
> +		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
> +		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
>   
> -		if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)
> +		if (status_l1 & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)
>   			pex_ep_event_hot_rst_done(pcie);
>   
> -		if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {
> -			tmp = appl_readl(pcie, APPL_LINK_STATUS);
> -			if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) {
> +		if (status_l1 & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {
> +			link_status = appl_readl(pcie, APPL_LINK_STATUS);
> +			if (link_status & APPL_LINK_STATUS_RDLH_LINK_UP) {
>   				dev_dbg(pcie->dev, "Link is up with Host\n");
>   				dw_pcie_ep_linkup(ep);
>   			}
> @@ -636,11 +636,11 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>   		spurious = 0;
>   	}
>   
> -	if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
> -		val = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
> -		appl_writel(pcie, val, APPL_INTR_STATUS_L1_15);
> +	if (status_l0 & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
> +		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
> +		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15);
>   
> -		if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)
> +		if (status_l1 & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)
>   			return IRQ_WAKE_THREAD;
>   
>   		spurious = 0;
> @@ -648,8 +648,8 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>   
>   	if (spurious) {
>   		dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
> -			 val);
> -		appl_writel(pcie, val, APPL_INTR_STATUS_L0);
> +			 status_l0);
> +		appl_writel(pcie, status_l0, APPL_INTR_STATUS_L0);
>   	}
>   
>   	return IRQ_HANDLED;
> 

[PATCH V2 2/5] PCI: tegra: Fix MSI-X programming

[Om Prakash Singh]

Lower order MSI-X address is programmed in MSIX_ADDR_MATCH_HIGH_OFF
DBI register instead of higher order address. This patch fixes this
programming mistake.

Signed-off-by: Om Prakash Singh <omp@nvidia.com>
---

Changes in V2:
	- No change

 drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 6f388523bffe..66e00b276cd3 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1863,7 +1863,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 	val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
 	val |= MSIX_ADDR_MATCH_LOW_OFF_EN;
 	dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val);
-	val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
+	val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
 	dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
 
 	ret = dw_pcie_ep_init_complete(ep);
-- 
2.17.1

Re: [PATCH V2 2/5] PCI: tegra: Fix MSI-X programming

[Vidya Sagar]

Acked-by: Vidya Sagar <vidyas@nvidia.com>

On 6/6/2021 1:52 PM, Om Prakash Singh wrote:
> Lower order MSI-X address is programmed in MSIX_ADDR_MATCH_HIGH_OFF
> DBI register instead of higher order address. This patch fixes this
> programming mistake.
> 
> Signed-off-by: Om Prakash Singh <omp@nvidia.com>
> ---
> 
> Changes in V2:
> 	- No change
> 
>   drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 6f388523bffe..66e00b276cd3 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1863,7 +1863,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>   	val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
>   	val |= MSIX_ADDR_MATCH_LOW_OFF_EN;
>   	dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_LOW_OFF, val);
> -	val = (lower_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
> +	val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
>   	dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
>   
>   	ret = dw_pcie_ep_init_complete(ep);
> 

[PATCH V2 3/5] PCI: tegra: Disable interrupts before entering L2

[Om Prakash Singh]

In suspend_noirq() call if link doesn't goto L2, PERST# is asserted
to bring link to detect state. However, this is causing surprise
link down AER error. Since Kernel is executing noirq suspend calls,
AER interrupt is not processed. PME and AER are shared interrupts
and PCIe subsystem driver enables wake capability of PME irq during
suspend. So this AER will cause suspend failure due to pending
AER interrupt.

After PCIe link is in L2, interrupts are not expected since PCIe
controller will be in reset state. Disable PCIe interrupts before
going to L2 state to avoid pending AER interrupt.

Signed-off-by: Om Prakash Singh <omp@nvidia.com>
---

Changes in V2:
	- Rephrase the commit message as per comment from Krzysztof Wilczyński

 drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 66e00b276cd3..64ec0da31b5b 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1593,6 +1593,16 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
 		return;
 	}
 
+	/*
+	 * PCIe controller exits from L2 only if reset is applied, so
+	 * controller doesn't handle interrupts. But in cases where
+	 * L2 entry fails, PERST# is asserted which can trigger surprise
+	 * link down AER. However this function call happens in
+	 * suspend_noirq(), so AER interrupt will not be processed.
+	 * Disable all interrupts to avoid such a scenario.
+	 */
+	appl_writel(pcie, 0x0, APPL_INTR_EN_L0_0);
+
 	if (tegra_pcie_try_link_l2(pcie)) {
 		dev_info(pcie->dev, "Link didn't transition to L2 state\n");
 		/*
-- 
2.17.1

Re: [PATCH V2 3/5] PCI: tegra: Disable interrupts before entering L2

[Vidya Sagar]

On 6/6/2021 1:52 PM, Om Prakash Singh wrote:
> In suspend_noirq() call if link doesn't goto L2, PERST# is asserted
> to bring link to detect state. However, this is causing surprise
> link down AER error. Since Kernel is executing noirq suspend calls,
> AER interrupt is not processed. PME and AER are shared interrupts
> and PCIe subsystem driver enables wake capability of PME irq during
> suspend. So this AER will cause suspend failure due to pending
> AER interrupt.
> 
> After PCIe link is in L2, interrupts are not expected since PCIe
> controller will be in reset state. Disable PCIe interrupts before
> going to L2 state to avoid pending AER interrupt.
> 
> Signed-off-by: Om Prakash Singh <omp@nvidia.com>
> ---
> 
> Changes in V2:
> 	- Rephrase the commit message as per comment from Krzysztof Wilczyński
> 
>   drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 66e00b276cd3..64ec0da31b5b 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1593,6 +1593,16 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
>   		return;
>   	}
>   
> +	/*
> +	 * PCIe controller exits from L2 only if reset is applied, so
> +	 * controller doesn't handle interrupts. But in cases where
> +	 * L2 entry fails, PERST# is asserted which can trigger surprise
> +	 * link down AER. However this function call happens in
> +	 * suspend_noirq(), so AER interrupt will not be processed.
> +	 * Disable all interrupts to avoid such a scenario.
> +	 */
> +	appl_writel(pcie, 0x0, APPL_INTR_EN_L0_0);
> +
>   	if (tegra_pcie_try_link_l2(pcie)) {
>   		dev_info(pcie->dev, "Link didn't transition to L2 state\n");
>   		/*
> 
Acked-by: Vidya Sagar <vidyas@nvidia.com>

[PATCH V2 4/5] PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode

[Om Prakash Singh]

When Tegra PCIe is in endpoint mode it should be available for root port.
PCIe link up by root port fails if it is in suspend state. So, don't allow
Tegra to suspend when endpoint mode is enabled.

Signed-off-by: Om Prakash Singh <omp@nvidia.com>
---

Changes in V2:
	- Update return value and error log as per comment from Krzysztof Wilczyński

 drivers/pci/controller/dwc/pcie-tegra194.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 64ec0da31b5b..ae4c0a29818d 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2276,6 +2276,11 @@ static int tegra_pcie_dw_suspend_late(struct device *dev)
 	struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
 	u32 val;
 
+	if (pcie->mode == DW_PCIE_EP_TYPE) {
+		dev_err(dev, "Suspend is not supported in EP mode");
+		return -ENOTSUPP;
+	}
+
 	if (!pcie->link_state)
 		return 0;
 
-- 
2.17.1

Re: [PATCH V2 4/5] PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode

[Vidya Sagar]

On 6/6/2021 1:52 PM, Om Prakash Singh wrote:
> When Tegra PCIe is in endpoint mode it should be available for root port.
> PCIe link up by root port fails if it is in suspend state. So, don't allow
> Tegra to suspend when endpoint mode is enabled.
> 
> Signed-off-by: Om Prakash Singh <omp@nvidia.com>
> ---
> 
> Changes in V2:
> 	- Update return value and error log as per comment from Krzysztof Wilczyński
> 
>   drivers/pci/controller/dwc/pcie-tegra194.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 64ec0da31b5b..ae4c0a29818d 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2276,6 +2276,11 @@ static int tegra_pcie_dw_suspend_late(struct device *dev)
>   	struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>   	u32 val;
>   
> +	if (pcie->mode == DW_PCIE_EP_TYPE) {
> +		dev_err(dev, "Suspend is not supported in EP mode");
> +		return -ENOTSUPP;
> +	}
> +
>   	if (!pcie->link_state)
>   		return 0;
>   
> 
Acked-by: Vidya Sagar <vidyas@nvidia.com>

[PATCH V2 5/5] PCI: tegra: Cleanup unused code

[Om Prakash Singh]

Remove unused code from function tegra_pcie_config_ep.

Signed-off-by: Om Prakash Singh <omp@nvidia.com>
---

Changes in V2:
	- No change

 drivers/pci/controller/dwc/pcie-tegra194.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index ae4c0a29818d..e9d573c850dd 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2045,13 +2045,6 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
 		return ret;
 	}
 
-	name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_ep_work",
-			      pcie->cid);
-	if (!name) {
-		dev_err(dev, "Failed to create PCIe EP work thread string\n");
-		return -ENOMEM;
-	}
-
 	pm_runtime_enable(dev);
 
 	ret = dw_pcie_ep_init(ep);
-- 
2.17.1

Re: [PATCH V2 5/5] PCI: tegra: Cleanup unused code

[Vidya Sagar]

On 6/6/2021 1:52 PM, Om Prakash Singh wrote:
> Remove unused code from function tegra_pcie_config_ep.
> 
> Signed-off-by: Om Prakash Singh <omp@nvidia.com>
> ---
> 
> Changes in V2:
> 	- No change
> 
>   drivers/pci/controller/dwc/pcie-tegra194.c | 7 -------
>   1 file changed, 7 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index ae4c0a29818d..e9d573c850dd 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2045,13 +2045,6 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
>   		return ret;
>   	}
>   
> -	name = devm_kasprintf(dev, GFP_KERNEL, "tegra_pcie_%u_ep_work",
> -			      pcie->cid);
> -	if (!name) {
> -		dev_err(dev, "Failed to create PCIe EP work thread string\n");
> -		return -ENOMEM;
> -	}
> -
>   	pm_runtime_enable(dev);
>   
>   	ret = dw_pcie_ep_init(ep);
> 
Acked-by: Vidya Sagar <vidyas@nvidia.com>

Re: [PATCH V2 0/5] Update pcie-tegra194 driver

[Om Prakash Singh]

Hi Lorenzo, Bjorn,
Can you help review this patch series please?

Thanks,
Om


On 6/6/2021 1:51 PM, Om Prakash Singh wrote:
> Update pcie-tegra194 driver with bug fixing and cleanup
> 
> Changes from V1->V2
>    PCI: tegra: Fix handling BME_CHGED event
> 	- Update variable naming
>    PCI: tegra: Fix MSI-X programming
> 	- No change
>    PCI: tegra: Disable interrupts before entering L2
> 	- Rephrase the commit message
>    PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode
> 	- Update return value to -ENOTSUPP.
>    PCI: tegra: Cleanup unused code
> 	- No Change
> 
> V1:
> http://patchwork.ozlabs.org/project/linux-pci/patch/20210527115246.20509-2-omp@nvidia.com/
> 
> Om Prakash Singh (5):
>    PCI: tegra: Fix handling BME_CHGED event
>    PCI: tegra: Fix MSI-X programming
>    PCI: tegra: Disable interrupts before entering L2
>    PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode
>    PCI: tegra: Cleanup unused code
> 
>   drivers/pci/controller/dwc/pcie-tegra194.c | 36 +++++++++++++---------
>   1 file changed, 22 insertions(+), 14 deletions(-)
> 

Re: [PATCH V2 0/5] Update pcie-tegra194 driver

[Bjorn Helgaas]

On Sun, Jun 06, 2021 at 01:51:59PM +0530, Om Prakash Singh wrote:
> Update pcie-tegra194 driver with bug fixing and cleanup
> 
> Changes from V1->V2
>   PCI: tegra: Fix handling BME_CHGED event
> 	- Update variable naming
>   PCI: tegra: Fix MSI-X programming
> 	- No change
>   PCI: tegra: Disable interrupts before entering L2
> 	- Rephrase the commit message
>   PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode
> 	- Update return value to -ENOTSUPP.
>   PCI: tegra: Cleanup unused code
> 	- No Change
> 
> V1:
> http://patchwork.ozlabs.org/project/linux-pci/patch/20210527115246.20509-2-omp@nvidia.com/
> 
> Om Prakash Singh (5):
>   PCI: tegra: Fix handling BME_CHGED event
>   PCI: tegra: Fix MSI-X programming
>   PCI: tegra: Disable interrupts before entering L2
>   PCI: tegra: Don't allow suspend when Tegra PCIe is in EP mode
>   PCI: tegra: Cleanup unused code

Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>

But please update the subject lines to be:

  PCI: tegra194: ...

to differentiate this driver from drivers/pci/controller/pci-tegra.c.
In the past we've used the "PCI: tegra:" prefix for both, but that's
confusing.

I think Lorenzo will take care of this series, but he's been away for
a week or so and will take a bit to catch up.

>  drivers/pci/controller/dwc/pcie-tegra194.c | 36 +++++++++++++---------
>  1 file changed, 22 insertions(+), 14 deletions(-)
> 
> -- 
> 2.17.1
>