[PATCH v2 0/8] MT8195 Acer Tomato - devicetrees Part 2

[PATCH v2 0/8] MT8195 Acer Tomato - devicetrees Part 2

[AngeloGioacchino Del Regno]

This series enables more functionality on the MT8195 Tomato Chromebooks,
bringing it to an almost usable state.

With this series, the device is able to boot from the MicroSD card
and is able to communicate with the EC for various functions,
including the enablement of the Chromebook's keyboard, battery
charging, fuel gauge and other standard ChromeOS EC functionality.

This also enables the Audio DSP, codec and sound card and adds support
for the regulators found on the SPMI bus.

What's missing (coming in the next part)?

* Format:    feature  (location)
*
* MediaTek vcodec enc/dec (mt8195.dtsi only)
* PCI-Express WiFi card (mt8195 and mt8195-cherry)
* VDOSYS1 (mt8195.dtsi and mediatek-drm/mmsys drivers)
* DP/eDP outputs for external/internal display (mt8195 and mt8195-cherry)
* LVTS Thermal Sensors (mt8195.dtsi, driver is missing)
* GPU support (comes later, clocks implementation is in the works)


### NOTE: ###

This series depends on MediaTek's MT8195 new device nodes [1] series

[1]: https://patchwork.kernel.org/project/linux-mediatek/list/?submitter=196333


Changes in v2:
 - Fixed *huge* mistake on patch [8/8] (truly sorry!!!)

AngeloGioacchino Del Regno (8):
  arm64: dts: mediatek: cherry: Enable the System Companion Processor
  arm64: dts: mediatek: cherry: Wire up the ChromeOS EC and GSC
  arm64: dts: mediatek: cherry: Add keyboard mapping for the top row
  arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller
  arm64: dts: mediatek: cherry: Enable Elantech eKTH3000 i2c trackpad
  arm64: dts: mediatek: cherry: Enable DSP, audio codec and sound card
  arm64: dts: mediatek: cherry: Enable keyboard PWM backlight
  arm64: dts: mediatek: cherry: Enable MT6315 regulators on SPMI bus

 .../dts/mediatek/mt8195-cherry-tomato-r1.dts  |  10 +
 .../dts/mediatek/mt8195-cherry-tomato-r2.dts  |  10 +
 .../dts/mediatek/mt8195-cherry-tomato-r3.dts  |  10 +
 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 403 ++++++++++++++++++
 4 files changed, 433 insertions(+)

-- 
2.35.1

[PATCH v2 1/8] arm64: dts: mediatek: cherry: Enable the System Companion Processor

[AngeloGioacchino Del Regno]

MT8195 features a SCP like some other older SoCs, and Cherry uses it
for various tasks. Add the required pin configuration and DMA pool
and enable the node.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 28 +++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index fcc600674339..feebbe367e93 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -104,6 +104,18 @@ usb_vbus: regulator-5v0-usb-vbus {
 		enable-active-high;
 		regulator-always-on;
 	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		scp_mem: memory@50000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x50000000 0 0x2900000>;
+			no-map;
+		};
+	};
 };
 
 &i2c0 {
@@ -600,6 +612,14 @@ pins-low-power-pupd {
 		};
 	};
 
+	scp_pins: scp-default-pins {
+		pins-vreq {
+			pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
+			bias-disable;
+			input-enable;
+		};
+	};
+
 	spi0_pins: spi0-default-pins {
 		pins-cs-mosi-clk {
 			pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
@@ -643,6 +663,14 @@ &pmic {
 	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&scp {
+	status = "okay";
+
+	memory-region = <&scp_mem>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&scp_pins>;
+};
+
 &spi0 {
 	status = "okay";
 
-- 
2.35.1

Re: [PATCH v2 1/8] arm64: dts: mediatek: cherry: Enable the System Companion Processor

[Chen-Yu Tsai]

On Thu, Jul 21, 2022 at 10:50 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> MT8195 features a SCP like some other older SoCs, and Cherry uses it
> for various tasks. Add the required pin configuration and DMA pool
> and enable the node.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../boot/dts/mediatek/mt8195-cherry.dtsi      | 28 +++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index fcc600674339..feebbe367e93 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -104,6 +104,18 @@ usb_vbus: regulator-5v0-usb-vbus {
>                 enable-active-high;
>                 regulator-always-on;
>         };
> +
> +       reserved_memory: reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               scp_mem: memory@50000000 {
> +                       compatible = "shared-dma-pool";
> +                       reg = <0 0x50000000 0 0x2900000>;
> +                       no-map;
> +               };
> +       };
>  };
>
>  &i2c0 {
> @@ -600,6 +612,14 @@ pins-low-power-pupd {
>                 };
>         };
>
> +       scp_pins: scp-default-pins {
> +               pins-vreq {
> +                       pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
> +                       bias-disable;
> +                       input-enable;
> +               };
> +       };
> +
>         spi0_pins: spi0-default-pins {
>                 pins-cs-mosi-clk {
>                         pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
> @@ -643,6 +663,14 @@ &pmic {
>         interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
>  };
>
> +&scp {
> +       status = "okay";
> +
> +       memory-region = <&scp_mem>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&scp_pins>;

firmware-name = "mediatek/mt8195/scp.img";

Or maybe this should be added to the base mt8195.dtsi?

The entry for mt8192 was added to mt8192-asurada.dtsi though.

Tinghan, could you ask internally whether the SCP firmware should be
tied to the SoC or the projects involving the SoC?

Thanks
ChenYu

> +};
> +
>  &spi0 {
>         status = "okay";
>
> --
> 2.35.1
>
>

Re: [PATCH v2 1/8] arm64: dts: mediatek: cherry: Enable the System Companion Processor

[AngeloGioacchino Del Regno]

Il 25/07/22 06:21, Chen-Yu Tsai ha scritto:
> On Thu, Jul 21, 2022 at 10:50 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> MT8195 features a SCP like some other older SoCs, and Cherry uses it
>> for various tasks. Add the required pin configuration and DMA pool
>> and enable the node.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   .../boot/dts/mediatek/mt8195-cherry.dtsi      | 28 +++++++++++++++++++
>>   1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> index fcc600674339..feebbe367e93 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> @@ -104,6 +104,18 @@ usb_vbus: regulator-5v0-usb-vbus {
>>                  enable-active-high;
>>                  regulator-always-on;
>>          };
>> +
>> +       reserved_memory: reserved-memory {
>> +               #address-cells = <2>;
>> +               #size-cells = <2>;
>> +               ranges;
>> +
>> +               scp_mem: memory@50000000 {
>> +                       compatible = "shared-dma-pool";
>> +                       reg = <0 0x50000000 0 0x2900000>;
>> +                       no-map;
>> +               };
>> +       };
>>   };
>>
>>   &i2c0 {
>> @@ -600,6 +612,14 @@ pins-low-power-pupd {
>>                  };
>>          };
>>
>> +       scp_pins: scp-default-pins {
>> +               pins-vreq {
>> +                       pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
>> +                       bias-disable;
>> +                       input-enable;
>> +               };
>> +       };
>> +
>>          spi0_pins: spi0-default-pins {
>>                  pins-cs-mosi-clk {
>>                          pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
>> @@ -643,6 +663,14 @@ &pmic {
>>          interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
>>   };
>>
>> +&scp {
>> +       status = "okay";
>> +
>> +       memory-region = <&scp_mem>;
>> +       pinctrl-names = "default";
>> +       pinctrl-0 = <&scp_pins>;
> 
> firmware-name = "mediatek/mt8195/scp.img";
> 

My intention was to actually add this line here. I must've erroneously
dropped it during cleanup/rebase...

> Or maybe this should be added to the base mt8195.dtsi?
> 
> The entry for mt8192 was added to mt8192-asurada.dtsi though.
> 
> Tinghan, could you ask internally whether the SCP firmware should be
> tied to the SoC or the projects involving the SoC?

In my opinion, even if that may be tied to the SoCs, we should still declare
it in the machine(/platform) devicetree as (even if *luckily* this is not the
case on Chromebooks), firmwares may be signed with a OEM key and may differ
just for that.

I'll send a v3 with that fix ASAP.

Cheers,
Angelo

> 
> Thanks
> ChenYu
> 
>> +};
>> +
>>   &spi0 {
>>          status = "okay";
>>
>> --
>> 2.35.1
>>
>>

[PATCH v2 2/8] arm64: dts: mediatek: cherry: Wire up the ChromeOS EC and GSC

[AngeloGioacchino Del Regno]

Wire up the ChromeOS Embedded Controller on SPI0 and its communication
channel via SCP RPMSG along with all of the offered functionality,
including Keyboard, Smart Battery Metrics (SBS), PWM controller, I2C
tunnel, regulators and Type-C connector management.

While at it, also add support for the Cr50 Google Security Chip (GSC)
found on this platform on I2C3 to support TPM and also use it as an
entropy source for the kernel.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 93 +++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index feebbe367e93..87ac2b4f9814 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -149,6 +149,14 @@ &i2c3 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c3_pins>;
+
+	cr50@50 {
+		compatible = "google,cr50";
+		reg = <0x50>;
+		interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cr50_int>;
+	};
 };
 
 &i2c4 {
@@ -426,6 +434,21 @@ &pio {
 		"AP_SPI_FLASH_MOSI",
 		"AP_SPI_FLASH_MISO";
 
+	cr50_int: cr50-irq-default-pins {
+		pins-gsc-ap-int-odl {
+			pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
+			input-enable;
+		};
+	};
+
+	cros_ec_int: cros-ec-irq-default-pins {
+		pins-ec-ap-int-odl {
+			pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+			input-enable;
+		};
+	};
+
 	i2c0_pins: i2c0-default-pins {
 		pins-bus {
 			pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
@@ -669,6 +692,11 @@ &scp {
 	memory-region = <&scp_mem>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&scp_pins>;
+
+	cros-ec-rpmsg {
+		compatible = "google,cros-ec-rpmsg";
+		mediatek,rpmsg-name = "cros-ec-rpmsg";
+	};
 };
 
 &spi0 {
@@ -677,6 +705,68 @@ &spi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi0_pins>;
 	mediatek,pad-select = <0>;
+
+	cros_ec: ec@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "google,cros-ec-spi";
+		reg = <0>;
+		interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&cros_ec_int>;
+		spi-max-frequency = <3000000>;
+
+		cros_ec_pwm: ec-pwm {
+			compatible = "google,cros-ec-pwm";
+			#pwm-cells = <1>;
+		};
+
+		i2c_tunnel: i2c-tunnel {
+			compatible = "google,cros-ec-i2c-tunnel";
+			google,remote-bus = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mt_pmic_vmc_ldo_reg: regulator@0 {
+			compatible = "google,cros-ec-regulator";
+			reg = <0>;
+			regulator-name = "mt_pmic_vmc_ldo";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <3600000>;
+		};
+
+		mt_pmic_vmch_ldo_reg: regulator@1 {
+			compatible = "google,cros-ec-regulator";
+			reg = <1>;
+			regulator-name = "mt_pmic_vmch_ldo";
+			regulator-min-microvolt = <2700000>;
+			regulator-max-microvolt = <3600000>;
+		};
+
+		typec {
+			compatible = "google,cros-ec-typec";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			usb_c0: connector@0 {
+				compatible = "usb-c-connector";
+				reg = <0>;
+				power-role = "dual";
+				data-role = "host";
+				try-power-role = "source";
+			};
+
+			usb_c1: connector@1 {
+				compatible = "usb-c-connector";
+				reg = <1>;
+				power-role = "dual";
+				data-role = "host";
+				try-power-role = "source";
+			};
+		};
+	};
 };
 
 &u3phy0 {
@@ -728,3 +818,6 @@ &xhci3 {
 	vusb33-supply = <&mt6359_vusb_ldo_reg>;
 	vbus-supply = <&usb_vbus>;
 };
+
+#include <arm/cros-ec-keyboard.dtsi>
+#include <arm/cros-ec-sbs.dtsi>
-- 
2.35.1

Re: [PATCH v2 2/8] arm64: dts: mediatek: cherry: Wire up the ChromeOS EC and GSC

[Chen-Yu Tsai]

On Thu, Jul 21, 2022 at 10:51 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Wire up the ChromeOS Embedded Controller on SPI0 and its communication
> channel via SCP RPMSG along with all of the offered functionality,
> including Keyboard, Smart Battery Metrics (SBS), PWM controller, I2C
> tunnel, regulators and Type-C connector management.
>
> While at it, also add support for the Cr50 Google Security Chip (GSC)
> found on this platform on I2C3 to support TPM and also use it as an
> entropy source for the kernel.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../boot/dts/mediatek/mt8195-cherry.dtsi      | 93 +++++++++++++++++++
>  1 file changed, 93 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index feebbe367e93..87ac2b4f9814 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -149,6 +149,14 @@ &i2c3 {
>         clock-frequency = <400000>;
>         pinctrl-names = "default";
>         pinctrl-0 = <&i2c3_pins>;
> +
> +       cr50@50 {

tpm?

Also I think the CR50 should be a separate patch. It is not related
to the EC.

> +               compatible = "google,cr50";
> +               reg = <0x50>;
> +               interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&cr50_int>;
> +       };
>  };
>
>  &i2c4 {
> @@ -426,6 +434,21 @@ &pio {
>                 "AP_SPI_FLASH_MOSI",
>                 "AP_SPI_FLASH_MISO";
>
> +       cr50_int: cr50-irq-default-pins {
> +               pins-gsc-ap-int-odl {
> +                       pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
> +                       input-enable;
> +               };
> +       };
> +
> +       cros_ec_int: cros-ec-irq-default-pins {
> +               pins-ec-ap-int-odl {
> +                       pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> +                       input-enable;
> +               };
> +       };
> +
>         i2c0_pins: i2c0-default-pins {
>                 pins-bus {
>                         pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
> @@ -669,6 +692,11 @@ &scp {
>         memory-region = <&scp_mem>;
>         pinctrl-names = "default";
>         pinctrl-0 = <&scp_pins>;
> +
> +       cros-ec-rpmsg {
> +               compatible = "google,cros-ec-rpmsg";
> +               mediatek,rpmsg-name = "cros-ec-rpmsg";
> +       };
>  };
>
>  &spi0 {
> @@ -677,6 +705,68 @@ &spi0 {
>         pinctrl-names = "default";
>         pinctrl-0 = <&spi0_pins>;
>         mediatek,pad-select = <0>;
> +
> +       cros_ec: ec@0 {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               compatible = "google,cros-ec-spi";
> +               reg = <0>;
> +               interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>;
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&cros_ec_int>;
> +               spi-max-frequency = <3000000>;
> +
> +               cros_ec_pwm: ec-pwm {
> +                       compatible = "google,cros-ec-pwm";
> +                       #pwm-cells = <1>;
> +               };

This only serves the keyboard backlight LED. However, we have a better
interface for that, described in

    Documentation/devicetree/bindings/chrome/google,cros-kbd-led-backlight.yaml

I think we should go with that one.


ChenYu

> +
> +               i2c_tunnel: i2c-tunnel {
> +                       compatible = "google,cros-ec-i2c-tunnel";
> +                       google,remote-bus = <0>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +
> +               mt_pmic_vmc_ldo_reg: regulator@0 {
> +                       compatible = "google,cros-ec-regulator";
> +                       reg = <0>;
> +                       regulator-name = "mt_pmic_vmc_ldo";
> +                       regulator-min-microvolt = <1200000>;
> +                       regulator-max-microvolt = <3600000>;
> +               };
> +
> +               mt_pmic_vmch_ldo_reg: regulator@1 {
> +                       compatible = "google,cros-ec-regulator";
> +                       reg = <1>;
> +                       regulator-name = "mt_pmic_vmch_ldo";
> +                       regulator-min-microvolt = <2700000>;
> +                       regulator-max-microvolt = <3600000>;
> +               };
> +
> +               typec {
> +                       compatible = "google,cros-ec-typec";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       usb_c0: connector@0 {
> +                               compatible = "usb-c-connector";
> +                               reg = <0>;
> +                               power-role = "dual";
> +                               data-role = "host";
> +                               try-power-role = "source";
> +                       };
> +
> +                       usb_c1: connector@1 {
> +                               compatible = "usb-c-connector";
> +                               reg = <1>;
> +                               power-role = "dual";
> +                               data-role = "host";
> +                               try-power-role = "source";
> +                       };
> +               };
> +       };
>  };
>
>  &u3phy0 {
> @@ -728,3 +818,6 @@ &xhci3 {
>         vusb33-supply = <&mt6359_vusb_ldo_reg>;
>         vbus-supply = <&usb_vbus>;
>  };
> +
> +#include <arm/cros-ec-keyboard.dtsi>
> +#include <arm/cros-ec-sbs.dtsi>
> --
> 2.35.1
>
>

[PATCH v2 3/8] arm64: dts: mediatek: cherry: Add keyboard mapping for the top row

[AngeloGioacchino Del Regno]

Chromebooks' embedded keyboards differ from standard layouts for the
top row, as this one doesn't have the standard function keys but
shortcuts instead: map these keys to achieve the functionality that
is pictured on the printouts.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 87ac2b4f9814..2853f7f76c90 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -821,3 +821,33 @@ &xhci3 {
 
 #include <arm/cros-ec-keyboard.dtsi>
 #include <arm/cros-ec-sbs.dtsi>
+
+&keyboard_controller {
+	function-row-physmap = <
+		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
+		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
+		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
+		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
+		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
+		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
+		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
+		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
+		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
+		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
+	>;
+
+	linux,keymap = <
+		MATRIX_KEY(0x00, 0x02, KEY_BACK)
+		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+		MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+		MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+		MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+
+		CROS_STD_MAIN_KEYMAP
+	>;
+};
-- 
2.35.1

Re: [PATCH v2 3/8] arm64: dts: mediatek: cherry: Add keyboard mapping for the top row

[Chen-Yu Tsai]

On Thu, Jul 21, 2022 at 10:52 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Chromebooks' embedded keyboards differ from standard layouts for the
> top row, as this one doesn't have the standard function keys but
> shortcuts instead: map these keys to achieve the functionality that
> is pictured on the printouts.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

> ---
>  .../boot/dts/mediatek/mt8195-cherry.dtsi      | 30 +++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index 87ac2b4f9814..2853f7f76c90 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -821,3 +821,33 @@ &xhci3 {
>
>  #include <arm/cros-ec-keyboard.dtsi>
>  #include <arm/cros-ec-sbs.dtsi>
> +
> +&keyboard_controller {
> +       function-row-physmap = <
> +               MATRIX_KEY(0x00, 0x02, 0)       /* T1 */
> +               MATRIX_KEY(0x03, 0x02, 0)       /* T2 */
> +               MATRIX_KEY(0x02, 0x02, 0)       /* T3 */
> +               MATRIX_KEY(0x01, 0x02, 0)       /* T4 */
> +               MATRIX_KEY(0x03, 0x04, 0)       /* T5 */
> +               MATRIX_KEY(0x02, 0x04, 0)       /* T6 */
> +               MATRIX_KEY(0x01, 0x04, 0)       /* T7 */
> +               MATRIX_KEY(0x02, 0x09, 0)       /* T8 */
> +               MATRIX_KEY(0x01, 0x09, 0)       /* T9 */
> +               MATRIX_KEY(0x00, 0x04, 0)       /* T10 */

I wonder if we want to add the sleep button to this list, since it is
technically part of the first row.

ChenYu

[PATCH v2 4/8] arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller

[AngeloGioacchino Del Regno]

As of now, all of the boards based on the cherry platform have a
usable secondary SD/MMC controller, usually for SD cards: enable
it to allow both booting from it and generally accessing external
storage.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 2853f7f76c90..8859957c7b27 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -17,6 +17,7 @@ aliases {
 		i2c5 = &i2c5;
 		i2c7 = &i2c7;
 		mmc0 = &mmc0;
+		mmc1 = &mmc1;
 		serial0 = &uart0;
 	};
 
@@ -227,6 +228,24 @@ &mmc0 {
 	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
 };
 
+&mmc1 {
+	status = "okay";
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
+	max-frequency = <200000000>;
+	no-mmc;
+	no-sdio;
+	pinctrl-names = "default", "state_uhs";
+	pinctrl-0 = <&mmc1_pins_default>;
+	pinctrl-1 = <&mmc1_pins_uhs>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
+	vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
+};
+
 /* for CPU-L */
 &mt6359_vcore_buck_reg {
 	regulator-always-on;
@@ -575,6 +594,49 @@ pins-rst {
 		};
 	};
 
+	mmc1_pins_default: mmc1-default-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
+				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
+				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
+				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
+				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+
+		pins-insert {
+			pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
+			bias-pull-up;
+		};
+	};
+
+	mmc1_pins_uhs: mmc1-uhs-pins {
+		pins-cmd-dat {
+			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
+				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
+				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
+				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
+				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
+			input-enable;
+			drive-strength = <8>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+
+		pins-clk {
+			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
+			drive-strength = <8>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+		};
+	};
+
 	nor_pins_default: nor-default-pins {
 		pins-ck-io {
 			pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
-- 
2.35.1

Re: [PATCH v2 4/8] arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller

[Chen-Yu Tsai]

On Thu, Jul 21, 2022 at 10:51 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> As of now, all of the boards based on the cherry platform have a
> usable secondary SD/MMC controller, usually for SD cards: enable
> it to allow both booting from it and generally accessing external
> storage.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../boot/dts/mediatek/mt8195-cherry.dtsi      | 62 +++++++++++++++++++
>  1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index 2853f7f76c90..8859957c7b27 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -17,6 +17,7 @@ aliases {
>                 i2c5 = &i2c5;
>                 i2c7 = &i2c7;
>                 mmc0 = &mmc0;
> +               mmc1 = &mmc1;
>                 serial0 = &uart0;
>         };
>
> @@ -227,6 +228,24 @@ &mmc0 {
>         vqmmc-supply = <&mt6359_vufs_ldo_reg>;
>  };
>
> +&mmc1 {
> +       status = "okay";
> +
> +       bus-width = <4>;
> +       cap-sd-highspeed;
> +       cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
> +       max-frequency = <200000000>;
> +       no-mmc;
> +       no-sdio;
> +       pinctrl-names = "default", "state_uhs";
> +       pinctrl-0 = <&mmc1_pins_default>;
> +       pinctrl-1 = <&mmc1_pins_uhs>;
> +       sd-uhs-sdr50;
> +       sd-uhs-sdr104;
> +       vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
> +       vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
> +};
> +
>  /* for CPU-L */
>  &mt6359_vcore_buck_reg {
>         regulator-always-on;
> @@ -575,6 +594,49 @@ pins-rst {
>                 };
>         };
>
> +       mmc1_pins_default: mmc1-default-pins {
> +               pins-cmd-dat {
> +                       pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
> +                                <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
> +                                <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
> +                                <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
> +                                <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
> +                       input-enable;
> +                       drive-strength = <8>;
> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> +               };
> +
> +               pins-clk {
> +                       pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
> +                       drive-strength = <8>;
> +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> +               };
> +
> +               pins-insert {
> +                       pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
> +                       bias-pull-up;
> +               };
> +       };
> +
> +       mmc1_pins_uhs: mmc1-uhs-pins {
> +               pins-cmd-dat {
> +                       pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
> +                                <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
> +                                <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
> +                                <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
> +                                <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
> +                       input-enable;
> +                       drive-strength = <8>;
> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> +               };
> +
> +               pins-clk {
> +                       pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
> +                       drive-strength = <8>;
> +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> +               };

I wonder if pins-insert should be duplicated here. And there's no
difference between the standard and UHS pinconfigs. One would expect
higher drive strength on the UHS set, if two sets were required.
So maybe we should just have one set, and use that one for both
the default and uhs states.

Otherwise,

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

> +       };
> +
>         nor_pins_default: nor-default-pins {
>                 pins-ck-io {
>                         pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
> --
> 2.35.1
>
>

Re: [PATCH v2 4/8] arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller

[AngeloGioacchino Del Regno]

Il 25/07/22 10:54, Chen-Yu Tsai ha scritto:
> On Thu, Jul 21, 2022 at 10:51 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> As of now, all of the boards based on the cherry platform have a
>> usable secondary SD/MMC controller, usually for SD cards: enable
>> it to allow both booting from it and generally accessing external
>> storage.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   .../boot/dts/mediatek/mt8195-cherry.dtsi      | 62 +++++++++++++++++++
>>   1 file changed, 62 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> index 2853f7f76c90..8859957c7b27 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> @@ -17,6 +17,7 @@ aliases {
>>                  i2c5 = &i2c5;
>>                  i2c7 = &i2c7;
>>                  mmc0 = &mmc0;
>> +               mmc1 = &mmc1;
>>                  serial0 = &uart0;
>>          };
>>
>> @@ -227,6 +228,24 @@ &mmc0 {
>>          vqmmc-supply = <&mt6359_vufs_ldo_reg>;
>>   };
>>
>> +&mmc1 {
>> +       status = "okay";
>> +
>> +       bus-width = <4>;
>> +       cap-sd-highspeed;
>> +       cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
>> +       max-frequency = <200000000>;
>> +       no-mmc;
>> +       no-sdio;
>> +       pinctrl-names = "default", "state_uhs";
>> +       pinctrl-0 = <&mmc1_pins_default>;
>> +       pinctrl-1 = <&mmc1_pins_uhs>;
>> +       sd-uhs-sdr50;
>> +       sd-uhs-sdr104;
>> +       vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
>> +       vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
>> +};
>> +
>>   /* for CPU-L */
>>   &mt6359_vcore_buck_reg {
>>          regulator-always-on;
>> @@ -575,6 +594,49 @@ pins-rst {
>>                  };
>>          };
>>
>> +       mmc1_pins_default: mmc1-default-pins {
>> +               pins-cmd-dat {
>> +                       pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
>> +                                <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
>> +                                <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
>> +                                <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
>> +                                <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
>> +                       input-enable;
>> +                       drive-strength = <8>;
>> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
>> +               };
>> +
>> +               pins-clk {
>> +                       pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
>> +                       drive-strength = <8>;
>> +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
>> +               };
>> +
>> +               pins-insert {
>> +                       pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
>> +                       bias-pull-up;
>> +               };
>> +       };
>> +
>> +       mmc1_pins_uhs: mmc1-uhs-pins {
>> +               pins-cmd-dat {
>> +                       pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
>> +                                <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
>> +                                <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
>> +                                <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
>> +                                <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
>> +                       input-enable;
>> +                       drive-strength = <8>;
>> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
>> +               };
>> +
>> +               pins-clk {
>> +                       pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
>> +                       drive-strength = <8>;
>> +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
>> +               };
> 
> I wonder if pins-insert should be duplicated here. And there's no
> difference between the standard and UHS pinconfigs. One would expect
> higher drive strength on the UHS set, if two sets were required.
> So maybe we should just have one set, and use that one for both
> the default and uhs states.
> 

I don't think that it would really make a lot of sense to duplicate the
insertion pin setup in the UHS-specific pinctrl set...

Whenever you remove the uSD card, the controller goes back to default,
as the first steps in card initialization are always happening at low
speed and only after that we can switch to UHS speeds... so we do expect
that the first-ever state is always `default` (by spec!), which means
that we are also ensuring that the insertion pin setup is always done.

Cheers,
Angelo

> Otherwise,
> 
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
> 
>> +       };
>> +
>>          nor_pins_default: nor-default-pins {
>>                  pins-ck-io {
>>                          pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
>> --
>> 2.35.1
>>
>>

Re: [PATCH v2 4/8] arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller

[Chen-Yu Tsai]

On Mon, Jul 25, 2022 at 6:20 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 25/07/22 10:54, Chen-Yu Tsai ha scritto:
> > On Thu, Jul 21, 2022 at 10:51 PM AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@collabora.com> wrote:
> >>
> >> As of now, all of the boards based on the cherry platform have a
> >> usable secondary SD/MMC controller, usually for SD cards: enable
> >> it to allow both booting from it and generally accessing external
> >> storage.
> >>
> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >> ---
> >>   .../boot/dts/mediatek/mt8195-cherry.dtsi      | 62 +++++++++++++++++++
> >>   1 file changed, 62 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> >> index 2853f7f76c90..8859957c7b27 100644
> >> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> >> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> >> @@ -17,6 +17,7 @@ aliases {
> >>                  i2c5 = &i2c5;
> >>                  i2c7 = &i2c7;
> >>                  mmc0 = &mmc0;
> >> +               mmc1 = &mmc1;
> >>                  serial0 = &uart0;
> >>          };
> >>
> >> @@ -227,6 +228,24 @@ &mmc0 {
> >>          vqmmc-supply = <&mt6359_vufs_ldo_reg>;
> >>   };
> >>
> >> +&mmc1 {
> >> +       status = "okay";
> >> +
> >> +       bus-width = <4>;
> >> +       cap-sd-highspeed;
> >> +       cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
> >> +       max-frequency = <200000000>;
> >> +       no-mmc;
> >> +       no-sdio;
> >> +       pinctrl-names = "default", "state_uhs";
> >> +       pinctrl-0 = <&mmc1_pins_default>;
> >> +       pinctrl-1 = <&mmc1_pins_uhs>;
> >> +       sd-uhs-sdr50;
> >> +       sd-uhs-sdr104;
> >> +       vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
> >> +       vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
> >> +};
> >> +
> >>   /* for CPU-L */
> >>   &mt6359_vcore_buck_reg {
> >>          regulator-always-on;
> >> @@ -575,6 +594,49 @@ pins-rst {
> >>                  };
> >>          };
> >>
> >> +       mmc1_pins_default: mmc1-default-pins {
> >> +               pins-cmd-dat {
> >> +                       pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
> >> +                                <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
> >> +                                <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
> >> +                                <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
> >> +                                <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
> >> +                       input-enable;
> >> +                       drive-strength = <8>;
> >> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> >> +               };
> >> +
> >> +               pins-clk {
> >> +                       pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
> >> +                       drive-strength = <8>;
> >> +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> >> +               };
> >> +
> >> +               pins-insert {
> >> +                       pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
> >> +                       bias-pull-up;
> >> +               };
> >> +       };
> >> +
> >> +       mmc1_pins_uhs: mmc1-uhs-pins {
> >> +               pins-cmd-dat {
> >> +                       pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
> >> +                                <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
> >> +                                <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
> >> +                                <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
> >> +                                <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
> >> +                       input-enable;
> >> +                       drive-strength = <8>;
> >> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> >> +               };
> >> +
> >> +               pins-clk {
> >> +                       pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
> >> +                       drive-strength = <8>;
> >> +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> >> +               };
> >
> > I wonder if pins-insert should be duplicated here. And there's no
> > difference between the standard and UHS pinconfigs. One would expect
> > higher drive strength on the UHS set, if two sets were required.
> > So maybe we should just have one set, and use that one for both
> > the default and uhs states.
> >
>
> I don't think that it would really make a lot of sense to duplicate the
> insertion pin setup in the UHS-specific pinctrl set...
>
> Whenever you remove the uSD card, the controller goes back to default,
> as the first steps in card initialization are always happening at low
> speed and only after that we can switch to UHS speeds... so we do expect
> that the first-ever state is always `default` (by spec!), which means
> that we are also ensuring that the insertion pin setup is always done.

Right. What I wanted to say was that, besides the insertion pin, there's
no difference between the default and uhs states here. So why have two
copies instead of one that is referenced twice? (the uhs state is required
by the binding).

ChenYu

> Cheers,
> Angelo
>
> > Otherwise,
> >
> > Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> > Tested-by: Chen-Yu Tsai <wenst@chromium.org>
> >
> >> +       };
> >> +
> >>          nor_pins_default: nor-default-pins {
> >>                  pins-ck-io {
> >>                          pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
> >> --
> >> 2.35.1
> >>
> >>
>

Re: [PATCH v2 4/8] arm64: dts: mediatek: cherry: Enable secondary SD/MMC controller

[AngeloGioacchino Del Regno]

Il 26/07/22 06:04, Chen-Yu Tsai ha scritto:
> On Mon, Jul 25, 2022 at 6:20 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Il 25/07/22 10:54, Chen-Yu Tsai ha scritto:
>>> On Thu, Jul 21, 2022 at 10:51 PM AngeloGioacchino Del Regno
>>> <angelogioacchino.delregno@collabora.com> wrote:
>>>>
>>>> As of now, all of the boards based on the cherry platform have a
>>>> usable secondary SD/MMC controller, usually for SD cards: enable
>>>> it to allow both booting from it and generally accessing external
>>>> storage.
>>>>
>>>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>>> ---
>>>>    .../boot/dts/mediatek/mt8195-cherry.dtsi      | 62 +++++++++++++++++++
>>>>    1 file changed, 62 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>>>> index 2853f7f76c90..8859957c7b27 100644
>>>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>>>> @@ -17,6 +17,7 @@ aliases {
>>>>                   i2c5 = &i2c5;
>>>>                   i2c7 = &i2c7;
>>>>                   mmc0 = &mmc0;
>>>> +               mmc1 = &mmc1;
>>>>                   serial0 = &uart0;
>>>>           };
>>>>
>>>> @@ -227,6 +228,24 @@ &mmc0 {
>>>>           vqmmc-supply = <&mt6359_vufs_ldo_reg>;
>>>>    };
>>>>
>>>> +&mmc1 {
>>>> +       status = "okay";
>>>> +
>>>> +       bus-width = <4>;
>>>> +       cap-sd-highspeed;
>>>> +       cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
>>>> +       max-frequency = <200000000>;
>>>> +       no-mmc;
>>>> +       no-sdio;
>>>> +       pinctrl-names = "default", "state_uhs";
>>>> +       pinctrl-0 = <&mmc1_pins_default>;
>>>> +       pinctrl-1 = <&mmc1_pins_uhs>;
>>>> +       sd-uhs-sdr50;
>>>> +       sd-uhs-sdr104;
>>>> +       vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
>>>> +       vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
>>>> +};
>>>> +
>>>>    /* for CPU-L */
>>>>    &mt6359_vcore_buck_reg {
>>>>           regulator-always-on;
>>>> @@ -575,6 +594,49 @@ pins-rst {
>>>>                   };
>>>>           };
>>>>
>>>> +       mmc1_pins_default: mmc1-default-pins {
>>>> +               pins-cmd-dat {
>>>> +                       pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
>>>> +                                <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
>>>> +                                <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
>>>> +                                <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
>>>> +                                <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
>>>> +                       input-enable;
>>>> +                       drive-strength = <8>;
>>>> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
>>>> +               };
>>>> +
>>>> +               pins-clk {
>>>> +                       pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
>>>> +                       drive-strength = <8>;
>>>> +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
>>>> +               };
>>>> +
>>>> +               pins-insert {
>>>> +                       pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
>>>> +                       bias-pull-up;
>>>> +               };
>>>> +       };
>>>> +
>>>> +       mmc1_pins_uhs: mmc1-uhs-pins {
>>>> +               pins-cmd-dat {
>>>> +                       pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
>>>> +                                <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
>>>> +                                <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
>>>> +                                <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
>>>> +                                <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
>>>> +                       input-enable;
>>>> +                       drive-strength = <8>;
>>>> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
>>>> +               };
>>>> +
>>>> +               pins-clk {
>>>> +                       pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
>>>> +                       drive-strength = <8>;
>>>> +                       bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
>>>> +               };
>>>
>>> I wonder if pins-insert should be duplicated here. And there's no
>>> difference between the standard and UHS pinconfigs. One would expect
>>> higher drive strength on the UHS set, if two sets were required.
>>> So maybe we should just have one set, and use that one for both
>>> the default and uhs states.
>>>
>>
>> I don't think that it would really make a lot of sense to duplicate the
>> insertion pin setup in the UHS-specific pinctrl set...
>>
>> Whenever you remove the uSD card, the controller goes back to default,
>> as the first steps in card initialization are always happening at low
>> speed and only after that we can switch to UHS speeds... so we do expect
>> that the first-ever state is always `default` (by spec!), which means
>> that we are also ensuring that the insertion pin setup is always done.
> 
> Right. What I wanted to say was that, besides the insertion pin, there's
> no difference between the default and uhs states here. So why have two
> copies instead of one that is referenced twice? (the uhs state is required
> by the binding).
> 

OH!!!! Right. Yes I definitely agree with you on that one.

Let's split the pins-insert in `mmc1_pins_det: mmc1-detect-pins` and add
a reference to it in the default pinctrl, that's a sensible option.

I'll do that for v3!

> ChenYu
> 
>> Cheers,
>> Angelo
>>
>>> Otherwise,
>>>
>>> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
>>> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
>>>
>>>> +       };
>>>> +
>>>>           nor_pins_default: nor-default-pins {
>>>>                   pins-ck-io {
>>>>                           pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
>>>> --
>>>> 2.35.1
>>>>
>>>>
>>


-- 
AngeloGioacchino Del Regno
Software Engineer

Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718

[PATCH v2 5/8] arm64: dts: mediatek: cherry: Enable Elantech eKTH3000 i2c trackpad

[AngeloGioacchino Del Regno]

The Cherry platform uses an Elantech touchpad/trackpad: enable
probing it at address 0x15 on I2C1.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 8859957c7b27..58349d4c3c8b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -134,6 +134,16 @@ &i2c1 {
 	i2c-scl-internal-delay-ns = <12500>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
+
+	trackpad@15 {
+		compatible = "elan,ekth3000";
+		reg = <0x15>;
+		interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&trackpad_pins>;
+		vcc-supply = <&pp3300_s3>;
+		wakeup-source;
+	};
 };
 
 &i2c2 {
@@ -727,6 +737,14 @@ subpmic_pin_irq: pins-subpmic-int-n {
 		};
 	};
 
+	trackpad_pins: trackpad-default-pins {
+		pins-int-n {
+			pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
 	touchscreen_pins: touchscreen-default-pins {
 		pins-int-n {
 			pinmux = <PINMUX_GPIO92__FUNC_GPIO92>;
-- 
2.35.1

Re: [PATCH v2 5/8] arm64: dts: mediatek: cherry: Enable Elantech eKTH3000 i2c trackpad

[Chen-Yu Tsai]

On Thu, Jul 21, 2022 at 10:52 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> The Cherry platform uses an Elantech touchpad/trackpad: enable
> probing it at address 0x15 on I2C1.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>

[PATCH v2 6/8] arm64: dts: mediatek: cherry: Enable DSP, audio codec and sound card

[AngeloGioacchino Del Regno]

All machines of the Cherry platform have a working DSP (integrated
into the MT8195 SoC), and audio support, some with a different audio
codec: specifically, some using Realtek's RT5682I and some RT5682S.

Write a configuration for all the audio bits to enable functionality.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../dts/mediatek/mt8195-cherry-tomato-r1.dts  |  10 ++
 .../dts/mediatek/mt8195-cherry-tomato-r2.dts  |  10 ++
 .../dts/mediatek/mt8195-cherry-tomato-r3.dts  |  10 ++
 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 117 ++++++++++++++++++
 4 files changed, 147 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts
index 3348ba69ff6c..2d5e8f371b6d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts
@@ -10,6 +10,16 @@ / {
 	compatible = "google,tomato-rev1", "google,tomato", "mediatek,mt8195";
 };
 
+&audio_codec {
+	compatible = "realtek,rt5682i";
+	realtek,btndet-delay = <16>;
+};
+
+&sound {
+	compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
+	model = "mt8195_r1019_5682";
+};
+
 &ts_10 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts
index 4669e9d917f8..2586c32ce6e6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts
@@ -10,6 +10,11 @@ / {
 	compatible = "google,tomato-rev2", "google,tomato", "mediatek,mt8195";
 };
 
+&audio_codec {
+	compatible = "realtek,rt5682i";
+	realtek,btndet-delay = <16>;
+};
+
 &pio_default {
 	pins-low-power-hdmi-disable {
 		pinmux = <PINMUX_GPIO31__FUNC_GPIO31>,
@@ -30,6 +35,11 @@ pins-low-power-pcie0-disable {
 	};
 };
 
+&sound {
+	compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
+	model = "mt8195_r1019_5682";
+};
+
 &ts_10 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts
index 5021edd02f7c..f54f9477b99d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts
@@ -11,6 +11,11 @@ / {
 		     "google,tomato", "mediatek,mt8195";
 };
 
+&audio_codec {
+	compatible = "realtek,rt5682s";
+	realtek,amic-delay-ms = <250>;
+};
+
 &pio_default {
 	pins-low-power-hdmi-disable {
 		pinmux = <PINMUX_GPIO31__FUNC_GPIO31>,
@@ -31,6 +36,11 @@ pins-low-power-pcie0-disable {
 	};
 };
 
+&sound {
+	compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
+	model = "m8195_r1019_5682s";
+};
+
 &ts_10 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 58349d4c3c8b..ca9955a97f8f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -25,6 +25,12 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
+	dmic_codec: dmic-codec {
+		compatible = "dmic-codec";
+		num-channels = <2>;
+		wakeup-delay-ms = <50>;
+	};
+
 	memory@40000000 {
 		device_type = "memory";
 		reg = <0 0x40000000 0 0x80000000>;
@@ -116,9 +122,49 @@ scp_mem: memory@50000000 {
 			reg = <0 0x50000000 0 0x2900000>;
 			no-map;
 		};
+
+		adsp_mem: memory@60000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60000000 0 0xd80000>;
+			no-map;
+		};
+
+		afe_mem: memory@60d80000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60d80000 0 0x100000>;
+			no-map;
+		};
+
+		adsp_device_mem: memory@60e80000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0x60e80000 0 0x280000>;
+			no-map;
+		};
+	};
+
+	spk_amplifier: rt1019p {
+		compatible = "realtek,rt1019p";
+		label = "rt1019p";
+		pinctrl-names = "default";
+		pinctrl-0 = <&rt1019p_pins_default>;
+		sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>;
 	};
 };
 
+&adsp {
+	status = "okay";
+
+	memory-region = <&adsp_device_mem>, <&adsp_mem>;
+};
+
+&afe {
+	status = "okay";
+
+	mediatek,etdm-in2-cowork-source = <2>;
+	mediatek,etdm-out2-cowork-source = <0>;
+	memory-region = <&afe_mem>;
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -152,6 +198,17 @@ &i2c2 {
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_pins>;
+
+	audio_codec: codec@1a {
+		/* Realtek RT5682i or RT5682s, sharing the same configuration */
+		reg = <0x1a>;
+		interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>;
+		realtek,jd-src = <1>;
+
+		AVDD-supply = <&mt6359_vio18_ldo_reg>;
+		MICVDD-supply = <&pp3300_z2>;
+		VBAT-supply = <&pp3300_z5>;
+	};
 };
 
 &i2c3 {
@@ -256,6 +313,11 @@ &mmc1 {
 	vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
 };
 
+&mt6359codec {
+	mediatek,dmic-mode = <1>;  /* one-wire */
+	mediatek,mic-type-0 = <2>; /* DMIC */
+};
+
 /* for CPU-L */
 &mt6359_vcore_buck_reg {
 	regulator-always-on;
@@ -463,6 +525,34 @@ &pio {
 		"AP_SPI_FLASH_MOSI",
 		"AP_SPI_FLASH_MISO";
 
+	aud_pins_default: audio-default-pins {
+		pins-cmd-dat {
+		    pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>,
+			     <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>,
+			     <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>,
+			     <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>,
+			     <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>,
+			     <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>,
+			     <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>,
+			     <PINMUX_GPIO0__FUNC_TDMIN_MCK>,
+			     <PINMUX_GPIO1__FUNC_TDMIN_DI>,
+			     <PINMUX_GPIO2__FUNC_TDMIN_LRCK>,
+			     <PINMUX_GPIO3__FUNC_TDMIN_BCK>,
+			     <PINMUX_GPIO60__FUNC_I2SO2_D0>,
+			     <PINMUX_GPIO49__FUNC_I2SIN_D0>,
+			     <PINMUX_GPIO50__FUNC_I2SO1_MCK>,
+			     <PINMUX_GPIO51__FUNC_I2SO1_BCK>,
+			     <PINMUX_GPIO52__FUNC_I2SO1_WS>,
+			     <PINMUX_GPIO53__FUNC_I2SO1_D0>;
+		};
+
+		pins-hp-jack-int-odl {
+			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>;
+			input-enable;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+		};
+	};
+
 	cr50_int: cr50-irq-default-pins {
 		pins-gsc-ap-int-odl {
 			pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
@@ -707,6 +797,21 @@ pins-low-power-pupd {
 		};
 	};
 
+	rt1011_pins_default: rt1011-default-pins {
+		pins-spk {
+			pinmux = <PINMUX_GPIO94__FUNC_GPIO94>,
+				 <PINMUX_GPIO100__FUNC_GPIO100>;
+			output-high;
+		};
+	};
+
+	rt1019p_pins_default: rt1019p-default-pins {
+		pins-amp-sdb {
+			pinmux = <PINMUX_GPIO100__FUNC_GPIO100>;
+			output-low;
+		};
+	};
+
 	scp_pins: scp-default-pins {
 		pins-vreq {
 			pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
@@ -779,6 +884,18 @@ cros-ec-rpmsg {
 	};
 };
 
+&sound {
+	status = "okay";
+
+	mediatek,adsp = <&adsp>;
+	mediatek,dai-link =
+		"DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE",
+		"ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE",
+		"AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5";
+	pinctrl-names = "default";
+	pinctrl-0 = <&aud_pins_default>;
+};
+
 &spi0 {
 	status = "okay";
 
-- 
2.35.1

Re: [PATCH v2 6/8] arm64: dts: mediatek: cherry: Enable DSP, audio codec and sound card

[Chen-Yu Tsai]

On Thu, Jul 21, 2022 at 10:53 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> All machines of the Cherry platform have a working DSP (integrated
> into the MT8195 SoC), and audio support, some with a different audio
> codec: specifically, some using Realtek's RT5682I and some RT5682S.
>
> Write a configuration for all the audio bits to enable functionality.

I think we're still missing some code for SOF that implements the
machine_select() callback, plus the firmware has to be fetched from
the ChromeOS rootfs.

It might make sense to have SOF disabled for now. Removing the adsp
reference and the overriding dai-link entry from the sound node
should do the trick.


ChenYu

> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../dts/mediatek/mt8195-cherry-tomato-r1.dts  |  10 ++
>  .../dts/mediatek/mt8195-cherry-tomato-r2.dts  |  10 ++
>  .../dts/mediatek/mt8195-cherry-tomato-r3.dts  |  10 ++
>  .../boot/dts/mediatek/mt8195-cherry.dtsi      | 117 ++++++++++++++++++
>  4 files changed, 147 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts
> index 3348ba69ff6c..2d5e8f371b6d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts
> @@ -10,6 +10,16 @@ / {
>         compatible = "google,tomato-rev1", "google,tomato", "mediatek,mt8195";
>  };
>
> +&audio_codec {
> +       compatible = "realtek,rt5682i";
> +       realtek,btndet-delay = <16>;
> +};
> +
> +&sound {
> +       compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
> +       model = "mt8195_r1019_5682";
> +};
> +
>  &ts_10 {
>         status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts
> index 4669e9d917f8..2586c32ce6e6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts
> @@ -10,6 +10,11 @@ / {
>         compatible = "google,tomato-rev2", "google,tomato", "mediatek,mt8195";
>  };
>
> +&audio_codec {
> +       compatible = "realtek,rt5682i";
> +       realtek,btndet-delay = <16>;
> +};
> +
>  &pio_default {
>         pins-low-power-hdmi-disable {
>                 pinmux = <PINMUX_GPIO31__FUNC_GPIO31>,
> @@ -30,6 +35,11 @@ pins-low-power-pcie0-disable {
>         };
>  };
>
> +&sound {
> +       compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
> +       model = "mt8195_r1019_5682";
> +};
> +
>  &ts_10 {
>         status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts
> index 5021edd02f7c..f54f9477b99d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts
> @@ -11,6 +11,11 @@ / {
>                      "google,tomato", "mediatek,mt8195";
>  };
>
> +&audio_codec {
> +       compatible = "realtek,rt5682s";
> +       realtek,amic-delay-ms = <250>;
> +};
> +
>  &pio_default {
>         pins-low-power-hdmi-disable {
>                 pinmux = <PINMUX_GPIO31__FUNC_GPIO31>,
> @@ -31,6 +36,11 @@ pins-low-power-pcie0-disable {
>         };
>  };
>
> +&sound {
> +       compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
> +       model = "m8195_r1019_5682s";
> +};
> +
>  &ts_10 {
>         status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index 58349d4c3c8b..ca9955a97f8f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -25,6 +25,12 @@ chosen {
>                 stdout-path = "serial0:115200n8";
>         };
>
> +       dmic_codec: dmic-codec {
> +               compatible = "dmic-codec";
> +               num-channels = <2>;
> +               wakeup-delay-ms = <50>;
> +       };
> +
>         memory@40000000 {
>                 device_type = "memory";
>                 reg = <0 0x40000000 0 0x80000000>;
> @@ -116,9 +122,49 @@ scp_mem: memory@50000000 {
>                         reg = <0 0x50000000 0 0x2900000>;
>                         no-map;
>                 };
> +
> +               adsp_mem: memory@60000000 {
> +                       compatible = "shared-dma-pool";
> +                       reg = <0 0x60000000 0 0xd80000>;
> +                       no-map;
> +               };
> +
> +               afe_mem: memory@60d80000 {
> +                       compatible = "shared-dma-pool";
> +                       reg = <0 0x60d80000 0 0x100000>;
> +                       no-map;
> +               };
> +
> +               adsp_device_mem: memory@60e80000 {
> +                       compatible = "shared-dma-pool";
> +                       reg = <0 0x60e80000 0 0x280000>;
> +                       no-map;
> +               };
> +       };
> +
> +       spk_amplifier: rt1019p {
> +               compatible = "realtek,rt1019p";
> +               label = "rt1019p";
> +               pinctrl-names = "default";
> +               pinctrl-0 = <&rt1019p_pins_default>;
> +               sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>;
>         };
>  };
>
> +&adsp {
> +       status = "okay";
> +
> +       memory-region = <&adsp_device_mem>, <&adsp_mem>;
> +};
> +
> +&afe {
> +       status = "okay";
> +
> +       mediatek,etdm-in2-cowork-source = <2>;
> +       mediatek,etdm-out2-cowork-source = <0>;
> +       memory-region = <&afe_mem>;
> +};
> +
>  &i2c0 {
>         status = "okay";
>
> @@ -152,6 +198,17 @@ &i2c2 {
>         clock-frequency = <400000>;
>         pinctrl-names = "default";
>         pinctrl-0 = <&i2c2_pins>;
> +
> +       audio_codec: codec@1a {
> +               /* Realtek RT5682i or RT5682s, sharing the same configuration */
> +               reg = <0x1a>;
> +               interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>;
> +               realtek,jd-src = <1>;
> +
> +               AVDD-supply = <&mt6359_vio18_ldo_reg>;
> +               MICVDD-supply = <&pp3300_z2>;
> +               VBAT-supply = <&pp3300_z5>;
> +       };
>  };
>
>  &i2c3 {
> @@ -256,6 +313,11 @@ &mmc1 {
>         vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
>  };
>
> +&mt6359codec {
> +       mediatek,dmic-mode = <1>;  /* one-wire */
> +       mediatek,mic-type-0 = <2>; /* DMIC */
> +};
> +
>  /* for CPU-L */
>  &mt6359_vcore_buck_reg {
>         regulator-always-on;
> @@ -463,6 +525,34 @@ &pio {
>                 "AP_SPI_FLASH_MOSI",
>                 "AP_SPI_FLASH_MISO";
>
> +       aud_pins_default: audio-default-pins {
> +               pins-cmd-dat {
> +                   pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>,
> +                            <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>,
> +                            <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>,
> +                            <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>,
> +                            <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>,
> +                            <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>,
> +                            <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>,
> +                            <PINMUX_GPIO0__FUNC_TDMIN_MCK>,
> +                            <PINMUX_GPIO1__FUNC_TDMIN_DI>,
> +                            <PINMUX_GPIO2__FUNC_TDMIN_LRCK>,
> +                            <PINMUX_GPIO3__FUNC_TDMIN_BCK>,
> +                            <PINMUX_GPIO60__FUNC_I2SO2_D0>,
> +                            <PINMUX_GPIO49__FUNC_I2SIN_D0>,
> +                            <PINMUX_GPIO50__FUNC_I2SO1_MCK>,
> +                            <PINMUX_GPIO51__FUNC_I2SO1_BCK>,
> +                            <PINMUX_GPIO52__FUNC_I2SO1_WS>,
> +                            <PINMUX_GPIO53__FUNC_I2SO1_D0>;
> +               };
> +
> +               pins-hp-jack-int-odl {
> +                       pinmux = <PINMUX_GPIO89__FUNC_GPIO89>;
> +                       input-enable;
> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> +               };
> +       };
> +
>         cr50_int: cr50-irq-default-pins {
>                 pins-gsc-ap-int-odl {
>                         pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
> @@ -707,6 +797,21 @@ pins-low-power-pupd {
>                 };
>         };
>
> +       rt1011_pins_default: rt1011-default-pins {
> +               pins-spk {
> +                       pinmux = <PINMUX_GPIO94__FUNC_GPIO94>,
> +                                <PINMUX_GPIO100__FUNC_GPIO100>;
> +                       output-high;
> +               };
> +       };
> +
> +       rt1019p_pins_default: rt1019p-default-pins {
> +               pins-amp-sdb {
> +                       pinmux = <PINMUX_GPIO100__FUNC_GPIO100>;
> +                       output-low;
> +               };
> +       };
> +
>         scp_pins: scp-default-pins {
>                 pins-vreq {
>                         pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
> @@ -779,6 +884,18 @@ cros-ec-rpmsg {
>         };
>  };
>
> +&sound {
> +       status = "okay";
> +
> +       mediatek,adsp = <&adsp>;
> +       mediatek,dai-link =
> +               "DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE",
> +               "ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE",
> +               "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5";
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&aud_pins_default>;
> +};
> +
>  &spi0 {
>         status = "okay";
>
> --
> 2.35.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2 6/8] arm64: dts: mediatek: cherry: Enable DSP, audio codec and sound card

[AngeloGioacchino Del Regno]

Il 25/07/22 12:44, Chen-Yu Tsai ha scritto:
> On Thu, Jul 21, 2022 at 10:53 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> All machines of the Cherry platform have a working DSP (integrated
>> into the MT8195 SoC), and audio support, some with a different audio
>> codec: specifically, some using Realtek's RT5682I and some RT5682S.
>>
>> Write a configuration for all the audio bits to enable functionality.
> 
> I think we're still missing some code for SOF that implements the
> machine_select() callback, plus the firmware has to be fetched from
> the ChromeOS rootfs.
> 
> It might make sense to have SOF disabled for now. Removing the adsp
> reference and the overriding dai-link entry from the sound node
> should do the trick.
> 

Uhm... I think that we should either have audio, with DSP, or not have it
at all... the userspace configurations will differ, so we'd end up with
two different confs of which one will get unused and cluttering the ucm2
conf git.

At this point, I think that the most sensible option is to either omit
this commit, or keep audio disabled until the machine_select() callback
gets in...

> 
> ChenYu
> 
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   .../dts/mediatek/mt8195-cherry-tomato-r1.dts  |  10 ++
>>   .../dts/mediatek/mt8195-cherry-tomato-r2.dts  |  10 ++
>>   .../dts/mediatek/mt8195-cherry-tomato-r3.dts  |  10 ++
>>   .../boot/dts/mediatek/mt8195-cherry.dtsi      | 117 ++++++++++++++++++
>>   4 files changed, 147 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts
>> index 3348ba69ff6c..2d5e8f371b6d 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts
>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts
>> @@ -10,6 +10,16 @@ / {
>>          compatible = "google,tomato-rev1", "google,tomato", "mediatek,mt8195";
>>   };
>>
>> +&audio_codec {
>> +       compatible = "realtek,rt5682i";
>> +       realtek,btndet-delay = <16>;
>> +};
>> +
>> +&sound {
>> +       compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
>> +       model = "mt8195_r1019_5682";
>> +};
>> +
>>   &ts_10 {
>>          status = "okay";
>>   };
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts
>> index 4669e9d917f8..2586c32ce6e6 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts
>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts
>> @@ -10,6 +10,11 @@ / {
>>          compatible = "google,tomato-rev2", "google,tomato", "mediatek,mt8195";
>>   };
>>
>> +&audio_codec {
>> +       compatible = "realtek,rt5682i";
>> +       realtek,btndet-delay = <16>;
>> +};
>> +
>>   &pio_default {
>>          pins-low-power-hdmi-disable {
>>                  pinmux = <PINMUX_GPIO31__FUNC_GPIO31>,
>> @@ -30,6 +35,11 @@ pins-low-power-pcie0-disable {
>>          };
>>   };
>>
>> +&sound {
>> +       compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
>> +       model = "mt8195_r1019_5682";
>> +};
>> +
>>   &ts_10 {
>>          status = "okay";
>>   };
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts
>> index 5021edd02f7c..f54f9477b99d 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts
>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r3.dts
>> @@ -11,6 +11,11 @@ / {
>>                       "google,tomato", "mediatek,mt8195";
>>   };
>>
>> +&audio_codec {
>> +       compatible = "realtek,rt5682s";
>> +       realtek,amic-delay-ms = <250>;
>> +};
>> +
>>   &pio_default {
>>          pins-low-power-hdmi-disable {
>>                  pinmux = <PINMUX_GPIO31__FUNC_GPIO31>,
>> @@ -31,6 +36,11 @@ pins-low-power-pcie0-disable {
>>          };
>>   };
>>
>> +&sound {
>> +       compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
>> +       model = "m8195_r1019_5682s";
>> +};
>> +
>>   &ts_10 {
>>          status = "okay";
>>   };
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> index 58349d4c3c8b..ca9955a97f8f 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> @@ -25,6 +25,12 @@ chosen {
>>                  stdout-path = "serial0:115200n8";
>>          };
>>
>> +       dmic_codec: dmic-codec {
>> +               compatible = "dmic-codec";
>> +               num-channels = <2>;
>> +               wakeup-delay-ms = <50>;
>> +       };
>> +
>>          memory@40000000 {
>>                  device_type = "memory";
>>                  reg = <0 0x40000000 0 0x80000000>;
>> @@ -116,9 +122,49 @@ scp_mem: memory@50000000 {
>>                          reg = <0 0x50000000 0 0x2900000>;
>>                          no-map;
>>                  };
>> +
>> +               adsp_mem: memory@60000000 {
>> +                       compatible = "shared-dma-pool";
>> +                       reg = <0 0x60000000 0 0xd80000>;
>> +                       no-map;
>> +               };
>> +
>> +               afe_mem: memory@60d80000 {
>> +                       compatible = "shared-dma-pool";
>> +                       reg = <0 0x60d80000 0 0x100000>;
>> +                       no-map;
>> +               };
>> +
>> +               adsp_device_mem: memory@60e80000 {
>> +                       compatible = "shared-dma-pool";
>> +                       reg = <0 0x60e80000 0 0x280000>;
>> +                       no-map;
>> +               };
>> +       };
>> +
>> +       spk_amplifier: rt1019p {
>> +               compatible = "realtek,rt1019p";
>> +               label = "rt1019p";
>> +               pinctrl-names = "default";
>> +               pinctrl-0 = <&rt1019p_pins_default>;
>> +               sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>;
>>          };
>>   };
>>
>> +&adsp {
>> +       status = "okay";
>> +
>> +       memory-region = <&adsp_device_mem>, <&adsp_mem>;
>> +};
>> +
>> +&afe {
>> +       status = "okay";
>> +
>> +       mediatek,etdm-in2-cowork-source = <2>;
>> +       mediatek,etdm-out2-cowork-source = <0>;
>> +       memory-region = <&afe_mem>;
>> +};
>> +
>>   &i2c0 {
>>          status = "okay";
>>
>> @@ -152,6 +198,17 @@ &i2c2 {
>>          clock-frequency = <400000>;
>>          pinctrl-names = "default";
>>          pinctrl-0 = <&i2c2_pins>;
>> +
>> +       audio_codec: codec@1a {
>> +               /* Realtek RT5682i or RT5682s, sharing the same configuration */
>> +               reg = <0x1a>;
>> +               interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>;
>> +               realtek,jd-src = <1>;
>> +
>> +               AVDD-supply = <&mt6359_vio18_ldo_reg>;
>> +               MICVDD-supply = <&pp3300_z2>;
>> +               VBAT-supply = <&pp3300_z5>;
>> +       };
>>   };
>>
>>   &i2c3 {
>> @@ -256,6 +313,11 @@ &mmc1 {
>>          vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
>>   };
>>
>> +&mt6359codec {
>> +       mediatek,dmic-mode = <1>;  /* one-wire */
>> +       mediatek,mic-type-0 = <2>; /* DMIC */
>> +};
>> +
>>   /* for CPU-L */
>>   &mt6359_vcore_buck_reg {
>>          regulator-always-on;
>> @@ -463,6 +525,34 @@ &pio {
>>                  "AP_SPI_FLASH_MOSI",
>>                  "AP_SPI_FLASH_MISO";
>>
>> +       aud_pins_default: audio-default-pins {
>> +               pins-cmd-dat {
>> +                   pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>,
>> +                            <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>,
>> +                            <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>,
>> +                            <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>,
>> +                            <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>,
>> +                            <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>,
>> +                            <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>,
>> +                            <PINMUX_GPIO0__FUNC_TDMIN_MCK>,
>> +                            <PINMUX_GPIO1__FUNC_TDMIN_DI>,
>> +                            <PINMUX_GPIO2__FUNC_TDMIN_LRCK>,
>> +                            <PINMUX_GPIO3__FUNC_TDMIN_BCK>,
>> +                            <PINMUX_GPIO60__FUNC_I2SO2_D0>,
>> +                            <PINMUX_GPIO49__FUNC_I2SIN_D0>,
>> +                            <PINMUX_GPIO50__FUNC_I2SO1_MCK>,
>> +                            <PINMUX_GPIO51__FUNC_I2SO1_BCK>,
>> +                            <PINMUX_GPIO52__FUNC_I2SO1_WS>,
>> +                            <PINMUX_GPIO53__FUNC_I2SO1_D0>;
>> +               };
>> +
>> +               pins-hp-jack-int-odl {
>> +                       pinmux = <PINMUX_GPIO89__FUNC_GPIO89>;
>> +                       input-enable;
>> +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
>> +               };
>> +       };
>> +
>>          cr50_int: cr50-irq-default-pins {
>>                  pins-gsc-ap-int-odl {
>>                          pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
>> @@ -707,6 +797,21 @@ pins-low-power-pupd {
>>                  };
>>          };
>>
>> +       rt1011_pins_default: rt1011-default-pins {
>> +               pins-spk {
>> +                       pinmux = <PINMUX_GPIO94__FUNC_GPIO94>,
>> +                                <PINMUX_GPIO100__FUNC_GPIO100>;
>> +                       output-high;
>> +               };
>> +       };
>> +
>> +       rt1019p_pins_default: rt1019p-default-pins {
>> +               pins-amp-sdb {
>> +                       pinmux = <PINMUX_GPIO100__FUNC_GPIO100>;
>> +                       output-low;
>> +               };
>> +       };
>> +
>>          scp_pins: scp-default-pins {
>>                  pins-vreq {
>>                          pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
>> @@ -779,6 +884,18 @@ cros-ec-rpmsg {
>>          };
>>   };
>>
>> +&sound {
>> +       status = "okay";
>> +
>> +       mediatek,adsp = <&adsp>;
>> +       mediatek,dai-link =
>> +               "DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE",
>> +               "ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE",
>> +               "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5";
>> +       pinctrl-names = "default";
>> +       pinctrl-0 = <&aud_pins_default>;
>> +};
>> +
>>   &spi0 {
>>          status = "okay";
>>
>> --
>> 2.35.1
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
AngeloGioacchino Del Regno
Software Engineer

Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718

Re: [PATCH v2 6/8] arm64: dts: mediatek: cherry: Enable DSP, audio codec and sound card

[Chen-Yu Tsai]

On Mon, Jul 25, 2022 at 6:49 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 25/07/22 12:44, Chen-Yu Tsai ha scritto:
> > On Thu, Jul 21, 2022 at 10:53 PM AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@collabora.com> wrote:
> >>
> >> All machines of the Cherry platform have a working DSP (integrated
> >> into the MT8195 SoC), and audio support, some with a different audio
> >> codec: specifically, some using Realtek's RT5682I and some RT5682S.
> >>
> >> Write a configuration for all the audio bits to enable functionality.
> >
> > I think we're still missing some code for SOF that implements the
> > machine_select() callback, plus the firmware has to be fetched from
> > the ChromeOS rootfs.
> >
> > It might make sense to have SOF disabled for now. Removing the adsp
> > reference and the overriding dai-link entry from the sound node
> > should do the trick.
> >
>
> Uhm... I think that we should either have audio, with DSP, or not have it
> at all... the userspace configurations will differ, so we'd end up with
> two different confs of which one will get unused and cluttering the ucm2
> conf git.

You're right. I haven't even figured out which ones to pull in.

> At this point, I think that the most sensible option is to either omit
> this commit, or keep audio disabled until the machine_select() callback
> gets in...

Agreed.

ChenYu

[PATCH v2 7/8] arm64: dts: mediatek: cherry: Enable keyboard PWM backlight

[AngeloGioacchino Del Regno]

Add a pwm-leds node to enable the PWM controlled keyboard backlight.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index ca9955a97f8f..9086a440a995 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
 #include "mt8195.dtsi"
 #include "mt6359.dtsi"
 
@@ -31,6 +32,18 @@ dmic_codec: dmic-codec {
 		wakeup-delay-ms = <50>;
 	};
 
+	led-controller {
+		compatible = "pwm-leds";
+
+		keyboard_backlight: keyboard-backlight {
+			default-state = "off";
+			function = LED_FUNCTION_KBD_BACKLIGHT;
+			label = "cros_ec::kbd_backlight";
+			max-brightness = <1023>;
+			pwms = <&cros_ec_pwm 3>;
+		};
+	};
+
 	memory@40000000 {
 		device_type = "memory";
 		reg = <0 0x40000000 0 0x80000000>;
-- 
2.35.1

Re: [PATCH v2 7/8] arm64: dts: mediatek: cherry: Enable keyboard PWM backlight

[Chen-Yu Tsai]

n Thu, Jul 21, 2022 at 10:53 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Add a pwm-leds node to enable the PWM controlled keyboard backlight.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index ca9955a97f8f..9086a440a995 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -4,6 +4,7 @@
>   */
>
>  #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
>  #include "mt8195.dtsi"
>  #include "mt6359.dtsi"
>
> @@ -31,6 +32,18 @@ dmic_codec: dmic-codec {
>                 wakeup-delay-ms = <50>;
>         };
>
> +       led-controller {
> +               compatible = "pwm-leds";
> +
> +               keyboard_backlight: keyboard-backlight {
> +                       default-state = "off";
> +                       function = LED_FUNCTION_KBD_BACKLIGHT;
> +                       label = "cros_ec::kbd_backlight";
> +                       max-brightness = <1023>;
> +                       pwms = <&cros_ec_pwm 3>;
> +               };
> +       };
> +

This didn't work for me. However using "google,cros-kbd-led-backlight"
under the EC did. That might be a better option.

ChenYu

>         memory@40000000 {
>                 device_type = "memory";
>                 reg = <0 0x40000000 0 0x80000000>;
> --
> 2.35.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2 7/8] arm64: dts: mediatek: cherry: Enable keyboard PWM backlight

[AngeloGioacchino Del Regno]

Il 25/07/22 11:57, Chen-Yu Tsai ha scritto:
> n Thu, Jul 21, 2022 at 10:53 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Add a pwm-leds node to enable the PWM controlled keyboard backlight.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 13 +++++++++++++
>>   1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> index ca9955a97f8f..9086a440a995 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>> @@ -4,6 +4,7 @@
>>    */
>>
>>   #include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/leds/common.h>
>>   #include "mt8195.dtsi"
>>   #include "mt6359.dtsi"
>>
>> @@ -31,6 +32,18 @@ dmic_codec: dmic-codec {
>>                  wakeup-delay-ms = <50>;
>>          };
>>
>> +       led-controller {
>> +               compatible = "pwm-leds";
>> +
>> +               keyboard_backlight: keyboard-backlight {
>> +                       default-state = "off";
>> +                       function = LED_FUNCTION_KBD_BACKLIGHT;
>> +                       label = "cros_ec::kbd_backlight";
>> +                       max-brightness = <1023>;
>> +                       pwms = <&cros_ec_pwm 3>;
>> +               };
>> +       };
>> +
> 
> This didn't work for me. However using "google,cros-kbd-led-backlight"
> under the EC did. That might be a better option.

Strange. But okay if there's a better option I'll check that out for v3.

Cheers!
Angelo

> 
> ChenYu
> 
>>          memory@40000000 {
>>                  device_type = "memory";
>>                  reg = <0 0x40000000 0 0x80000000>;
>> --
>> 2.35.1
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2 7/8] arm64: dts: mediatek: cherry: Enable keyboard PWM backlight

[Chen-Yu Tsai]

On Mon, Jul 25, 2022 at 6:04 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 25/07/22 11:57, Chen-Yu Tsai ha scritto:
> > n Thu, Jul 21, 2022 at 10:53 PM AngeloGioacchino Del Regno
> > <angelogioacchino.delregno@collabora.com> wrote:
> >>
> >> Add a pwm-leds node to enable the PWM controlled keyboard backlight.
> >>
> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >> ---
> >>   arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 13 +++++++++++++
> >>   1 file changed, 13 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> >> index ca9955a97f8f..9086a440a995 100644
> >> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> >> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> >> @@ -4,6 +4,7 @@
> >>    */
> >>
> >>   #include <dt-bindings/gpio/gpio.h>
> >> +#include <dt-bindings/leds/common.h>
> >>   #include "mt8195.dtsi"
> >>   #include "mt6359.dtsi"
> >>
> >> @@ -31,6 +32,18 @@ dmic_codec: dmic-codec {
> >>                  wakeup-delay-ms = <50>;
> >>          };
> >>
> >> +       led-controller {
> >> +               compatible = "pwm-leds";
> >> +
> >> +               keyboard_backlight: keyboard-backlight {
> >> +                       default-state = "off";
> >> +                       function = LED_FUNCTION_KBD_BACKLIGHT;
> >> +                       label = "cros_ec::kbd_backlight";
> >> +                       max-brightness = <1023>;
> >> +                       pwms = <&cros_ec_pwm 3>;
> >> +               };
> >> +       };
> >> +
> >
> > This didn't work for me. However using "google,cros-kbd-led-backlight"
> > under the EC did. That might be a better option.
>
> Strange. But okay if there's a better option I'll check that out for v3.

It might be an EC firmware version issue. My devices are all running
test images, and don't automatically update the EC firmware.

For reference, mine is at:

RO:    tomato_v2.0.10686-234e646fd8
        tomato_14268.0.0
RW:    tomato_v2.0.10686-234e646fd8
        tomato_14268.0.0
Build:    tomato_v2.0.10686-234e646fd8 tomato_14268.0.0
        2021-10-07 09:00:32
        @chromeos-ci-legacy-us-central2-d-x32-34-us9d

ChenYu

> Cheers!
> Angelo
>
> >
> > ChenYu
> >
> >>          memory@40000000 {
> >>                  device_type = "memory";
> >>                  reg = <0 0x40000000 0 0x80000000>;
> >> --
> >> 2.35.1
> >>
> >>
> >> _______________________________________________
> >> linux-arm-kernel mailing list
> >> linux-arm-kernel@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

Re: [PATCH v2 7/8] arm64: dts: mediatek: cherry: Enable keyboard PWM backlight

[AngeloGioacchino Del Regno]

Il 25/07/22 12:06, Chen-Yu Tsai ha scritto:
> On Mon, Jul 25, 2022 at 6:04 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Il 25/07/22 11:57, Chen-Yu Tsai ha scritto:
>>> n Thu, Jul 21, 2022 at 10:53 PM AngeloGioacchino Del Regno
>>> <angelogioacchino.delregno@collabora.com> wrote:
>>>>
>>>> Add a pwm-leds node to enable the PWM controlled keyboard backlight.
>>>>
>>>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>>> ---
>>>>    arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 13 +++++++++++++
>>>>    1 file changed, 13 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>>>> index ca9955a97f8f..9086a440a995 100644
>>>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>>>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
>>>> @@ -4,6 +4,7 @@
>>>>     */
>>>>
>>>>    #include <dt-bindings/gpio/gpio.h>
>>>> +#include <dt-bindings/leds/common.h>
>>>>    #include "mt8195.dtsi"
>>>>    #include "mt6359.dtsi"
>>>>
>>>> @@ -31,6 +32,18 @@ dmic_codec: dmic-codec {
>>>>                   wakeup-delay-ms = <50>;
>>>>           };
>>>>
>>>> +       led-controller {
>>>> +               compatible = "pwm-leds";
>>>> +
>>>> +               keyboard_backlight: keyboard-backlight {
>>>> +                       default-state = "off";
>>>> +                       function = LED_FUNCTION_KBD_BACKLIGHT;
>>>> +                       label = "cros_ec::kbd_backlight";
>>>> +                       max-brightness = <1023>;
>>>> +                       pwms = <&cros_ec_pwm 3>;
>>>> +               };
>>>> +       };
>>>> +
>>>
>>> This didn't work for me. However using "google,cros-kbd-led-backlight"
>>> under the EC did. That might be a better option.
>>
>> Strange. But okay if there's a better option I'll check that out for v3.
> 
> It might be an EC firmware version issue. My devices are all running
> test images, and don't automatically update the EC firmware.
> 
> For reference, mine is at:
> 
> RO:    tomato_v2.0.10686-234e646fd8
>          tomato_14268.0.0
> RW:    tomato_v2.0.10686-234e646fd8
>          tomato_14268.0.0
> Build:    tomato_v2.0.10686-234e646fd8 tomato_14268.0.0
>          2021-10-07 09:00:32
>          @chromeos-ci-legacy-us-central2-d-x32-34-us9d
> 

It's surely about the firmware, because I can confirm that I didn't
have a working KB kacklight before upgrading... I remember debugging
that and I couldn't figure out why it wasn't working...

After an upgrade, it magically worked, so that's it.

RO version:    tomato_v2.0.11883-9f0d374060

RO cros fwid:  tomato_14454.14.0

RW version:    tomato_v2.0.11893-d27ab0e96d

RW cros fwid:  tomato_14454.23.0



That's the FW that I have here on my machine... :-)

I'll anyway check out the binding that you suggested, as if that works
in any condition that's simply better!


> ChenYu
> 
>> Cheers!
>> Angelo
>>
>>>
>>> ChenYu
>>>
>>>>           memory@40000000 {
>>>>                   device_type = "memory";
>>>>                   reg = <0 0x40000000 0 0x80000000>;
>>>> --
>>>> 2.35.1
>>>>
>>>>
>>>> _______________________________________________
>>>> linux-arm-kernel mailing list
>>>> linux-arm-kernel@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>

[PATCH v2 8/8] arm64: dts: mediatek: cherry: Enable MT6315 regulators on SPMI bus

[AngeloGioacchino Del Regno]

All machines in the Cherry platform use MT6315 over SPMI: add the
two instances, providing Vbcpu and Vgpu regulators.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../boot/dts/mediatek/mt8195-cherry.dtsi      | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index 9086a440a995..6219544e9912 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/leds/common.h>
+#include <dt-bindings/spmi/spmi.h>
 #include "mt8195.dtsi"
 #include "mt6359.dtsi"
 
@@ -979,6 +980,47 @@ usb_c1: connector@1 {
 	};
 };
 
+&spmi {
+	#address-cells = <2>;
+	#size-cells = <0>;
+
+	mt6315@6 {
+		compatible = "mediatek,mt6315-regulator";
+		reg = <0x6 SPMI_USID>;
+
+		regulators {
+			mt6315_6_vbuck1: vbuck1 {
+				regulator-compatible = "vbuck1";
+				regulator-name = "Vbcpu";
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1193750>;
+				regulator-enable-ramp-delay = <256>;
+				regulator-ramp-delay = <6250>;
+				regulator-allowed-modes = <0 1 2>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	mt6315@7 {
+		compatible = "mediatek,mt6315-regulator";
+		reg = <0x7 SPMI_USID>;
+
+		regulators {
+			mt6315_7_vbuck1: vbuck1 {
+				regulator-compatible = "vbuck1";
+				regulator-name = "Vgpu";
+				regulator-min-microvolt = <625000>;
+				regulator-max-microvolt = <1193750>;
+				regulator-enable-ramp-delay = <256>;
+				regulator-ramp-delay = <6250>;
+				regulator-allowed-modes = <0 1 2>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
 &u3phy0 {
 	status = "okay";
 };
-- 
2.35.1

Re: [PATCH v2 8/8] arm64: dts: mediatek: cherry: Enable MT6315 regulators on SPMI bus

[Chen-Yu Tsai]

On Thu, Jul 21, 2022 at 10:54 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> All machines in the Cherry platform use MT6315 over SPMI: add the
> two instances, providing Vbcpu and Vgpu regulators.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Tested-by: Chen-Yu Tsai <wenst@chromium.org>

> ---
>  .../boot/dts/mediatek/mt8195-cherry.dtsi      | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index 9086a440a995..6219544e9912 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -5,6 +5,7 @@
>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/leds/common.h>
> +#include <dt-bindings/spmi/spmi.h>
>  #include "mt8195.dtsi"
>  #include "mt6359.dtsi"
>
> @@ -979,6 +980,47 @@ usb_c1: connector@1 {
>         };
>  };
>
> +&spmi {
> +       #address-cells = <2>;
> +       #size-cells = <0>;
> +
> +       mt6315@6 {
> +               compatible = "mediatek,mt6315-regulator";
> +               reg = <0x6 SPMI_USID>;
> +
> +               regulators {
> +                       mt6315_6_vbuck1: vbuck1 {
> +                               regulator-compatible = "vbuck1";
> +                               regulator-name = "Vbcpu";
> +                               regulator-min-microvolt = <300000>;
> +                               regulator-max-microvolt = <1193750>;

Tinghan,

Could you help confirm these numbers? They must be valid for the
big cluster supply, not the PMIC.

> +                               regulator-enable-ramp-delay = <256>;
> +                               regulator-ramp-delay = <6250>;
> +                               regulator-allowed-modes = <0 1 2>;
> +                               regulator-always-on;
> +                       };
> +               };
> +       };
> +
> +       mt6315@7 {
> +               compatible = "mediatek,mt6315-regulator";
> +               reg = <0x7 SPMI_USID>;
> +
> +               regulators {
> +                       mt6315_7_vbuck1: vbuck1 {
> +                               regulator-compatible = "vbuck1";
> +                               regulator-name = "Vgpu";
> +                               regulator-min-microvolt = <625000>;
> +                               regulator-max-microvolt = <1193750>;

Same here for the GPU.


Thanks
ChenYu


> +                               regulator-enable-ramp-delay = <256>;
> +                               regulator-ramp-delay = <6250>;
> +                               regulator-allowed-modes = <0 1 2>;
> +                               regulator-always-on;
> +                       };
> +               };
> +       };
> +};
> +
>  &u3phy0 {
>         status = "okay";
>  };
> --
> 2.35.1
>
>