From: <Tudor.Ambarus@microchip.com>
To: <Kavyasree.Kotagiri@microchip.com>, <arnd@arndb.de>,
<robh+dt@kernel.org>, <krzk+dt@kernel.org>,
<alexandre.belloni@bootlin.com>, <olof@lixom.net>,
<soc@kernel.org>, <Nicolas.Ferre@microchip.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<UNGLinuxDriver@microchip.com>, <Manohar.Puri@microchip.com>
Subject: Re: [PATCH 1/2] ARM: dts: lan966x: Add QSPI nodes
Date: Thu, 7 Apr 2022 12:16:41 +0000 [thread overview]
Message-ID: <fa197d6a-878c-ea49-c40d-1268eb1587a4@microchip.com> (raw)
In-Reply-To: <20220407105835.10962-2-kavyasree.kotagiri@microchip.com>
On 4/7/22 13:58, Kavyasree Kotagiri wrote:
> LAN966x SoC supports 3 instances of QSPI.
> Data and clock of qspi0, qspi1, qspi2 works upto 100Mhz.
>
> Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 48 ++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index 7d2869648050..b3c687db0aea 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -196,6 +196,54 @@
> status = "disabled";
> };
>
> + qspi0: spi@e0804000 {
> + compatible = "microchip,lan966x-qspi";
Why do you introduce a new compatible? Is this IP different than
the one on sama7g5? What are the differences? You need to add the
new compatible in the bindings file before using it in dt.
I see you use "-qspi" for all the 3 instances of the IP. Does this
IP support octal mode?
Cheers,
ta
next prev parent reply other threads:[~2022-04-07 12:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-07 10:58 [PATCH 0/2] ARM: dts: Add LAN966x QSPI nodes Kavyasree Kotagiri
2022-04-07 10:58 ` [PATCH 1/2] ARM: dts: lan966x: Add " Kavyasree Kotagiri
2022-04-07 12:07 ` Krzysztof Kozlowski
2022-04-07 12:16 ` Tudor.Ambarus [this message]
2022-04-07 10:58 ` [PATCH 2/2] ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR memory nodes Kavyasree Kotagiri
2022-04-07 12:13 ` Krzysztof Kozlowski
2022-04-07 12:26 ` Tudor.Ambarus
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