* [PATCH 0/2] ARM: dts: Add LAN966x QSPI nodes @ 2022-04-07 10:58 Kavyasree Kotagiri 2022-04-07 10:58 ` [PATCH 1/2] ARM: dts: lan966x: Add " Kavyasree Kotagiri 2022-04-07 10:58 ` [PATCH 2/2] ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR memory nodes Kavyasree Kotagiri 0 siblings, 2 replies; 7+ messages in thread From: Kavyasree Kotagiri @ 2022-04-07 10:58 UTC (permalink / raw) To: arnd, robh+dt, krzk+dt, alexandre.belloni, olof, soc, nicolas.ferre Cc: linux-arm-kernel, devicetree, linux-kernel, UNGLinuxDriver, tudor.ambarus, Kavyasree.Kotagiri, Manohar.Puri This patch series adds QSPI nodes of LAN966x Soc. Also enables qspi0 controller and SST SPI-NOR flash for pcb8291 board. Kavyasree Kotagiri (2): ARM: dts: lan966x: Add QSPI nodes ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR memory nodes arch/arm/boot/dts/lan966x-pcb8291.dts | 15 +++++++++ arch/arm/boot/dts/lan966x.dtsi | 48 +++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] ARM: dts: lan966x: Add QSPI nodes 2022-04-07 10:58 [PATCH 0/2] ARM: dts: Add LAN966x QSPI nodes Kavyasree Kotagiri @ 2022-04-07 10:58 ` Kavyasree Kotagiri 2022-04-07 12:07 ` Krzysztof Kozlowski 2022-04-07 12:16 ` Tudor.Ambarus 2022-04-07 10:58 ` [PATCH 2/2] ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR memory nodes Kavyasree Kotagiri 1 sibling, 2 replies; 7+ messages in thread From: Kavyasree Kotagiri @ 2022-04-07 10:58 UTC (permalink / raw) To: arnd, robh+dt, krzk+dt, alexandre.belloni, olof, soc, nicolas.ferre Cc: linux-arm-kernel, devicetree, linux-kernel, UNGLinuxDriver, tudor.ambarus, Kavyasree.Kotagiri, Manohar.Puri LAN966x SoC supports 3 instances of QSPI. Data and clock of qspi0, qspi1, qspi2 works upto 100Mhz. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> --- arch/arm/boot/dts/lan966x.dtsi | 48 ++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 7d2869648050..b3c687db0aea 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -196,6 +196,54 @@ status = "disabled"; }; + qspi0: spi@e0804000 { + compatible = "microchip,lan966x-qspi"; + reg = <0xe0804000 0x100>, + <0x20000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks GCK_ID_QSPI0>; + clock-names = "gclk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>, + <&dma0 AT91_XDMAC_DT_PERID(1)>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi1: spi@e0054000 { + compatible = "microchip,lan966x-qspi"; + reg = <0xe0054000 0x100>, + <0x40000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks GCK_ID_QSPI1>; + clock-names = "gclk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(15)>, + <&dma0 AT91_XDMAC_DT_PERID(16)>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi2: spi@e0834000 { + compatible = "microchip,lan966x-qspi"; + reg = <0xe0834000 0x100>, + <0x30000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks GCK_ID_QSPI2>; + clock-names = "gclk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(17)>, + <&dma0 AT91_XDMAC_DT_PERID(18)>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + can0: can@e081c000 { compatible = "bosch,m_can"; reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; -- 2.17.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] ARM: dts: lan966x: Add QSPI nodes 2022-04-07 10:58 ` [PATCH 1/2] ARM: dts: lan966x: Add " Kavyasree Kotagiri @ 2022-04-07 12:07 ` Krzysztof Kozlowski 2022-04-07 12:16 ` Tudor.Ambarus 1 sibling, 0 replies; 7+ messages in thread From: Krzysztof Kozlowski @ 2022-04-07 12:07 UTC (permalink / raw) To: Kavyasree Kotagiri, arnd, robh+dt, krzk+dt, alexandre.belloni, olof, soc, nicolas.ferre Cc: linux-arm-kernel, devicetree, linux-kernel, UNGLinuxDriver, tudor.ambarus, Manohar.Puri Thank you for your patch. There is something to discuss/improve. This should be sent with your DT bindings patch in one patchset. On 07/04/2022 12:58, Kavyasree Kotagiri wrote: > LAN966x SoC supports 3 instances of QSPI. > Data and clock of qspi0, qspi1, qspi2 works upto 100Mhz. s/upto/up to/ > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > arch/arm/boot/dts/lan966x.dtsi | 48 ++++++++++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi > index 7d2869648050..b3c687db0aea 100644 > --- a/arch/arm/boot/dts/lan966x.dtsi > +++ b/arch/arm/boot/dts/lan966x.dtsi > @@ -196,6 +196,54 @@ > status = "disabled"; > }; > > + qspi0: spi@e0804000 { > + compatible = "microchip,lan966x-qspi"; > + reg = <0xe0804000 0x100>, > + <0x20000000 0x08000000>; > + reg-names = "qspi_base", "qspi_mmap"; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks GCK_ID_QSPI0>; > + clock-names = "gclk"; This is not correct with the DT schema. > + dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>, > + <&dma0 AT91_XDMAC_DT_PERID(1)>; > + dma-names = "rx", "tx"; This as well. You can test schema with 'make dtbs_check DT_SCHEMA_FILES=...." (check the docs for help what is needed to do it). Best regards, Krzysztof ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] ARM: dts: lan966x: Add QSPI nodes 2022-04-07 10:58 ` [PATCH 1/2] ARM: dts: lan966x: Add " Kavyasree Kotagiri 2022-04-07 12:07 ` Krzysztof Kozlowski @ 2022-04-07 12:16 ` Tudor.Ambarus 1 sibling, 0 replies; 7+ messages in thread From: Tudor.Ambarus @ 2022-04-07 12:16 UTC (permalink / raw) To: Kavyasree.Kotagiri, arnd, robh+dt, krzk+dt, alexandre.belloni, olof, soc, Nicolas.Ferre Cc: linux-arm-kernel, devicetree, linux-kernel, UNGLinuxDriver, Manohar.Puri On 4/7/22 13:58, Kavyasree Kotagiri wrote: > LAN966x SoC supports 3 instances of QSPI. > Data and clock of qspi0, qspi1, qspi2 works upto 100Mhz. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > arch/arm/boot/dts/lan966x.dtsi | 48 ++++++++++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi > index 7d2869648050..b3c687db0aea 100644 > --- a/arch/arm/boot/dts/lan966x.dtsi > +++ b/arch/arm/boot/dts/lan966x.dtsi > @@ -196,6 +196,54 @@ > status = "disabled"; > }; > > + qspi0: spi@e0804000 { > + compatible = "microchip,lan966x-qspi"; Why do you introduce a new compatible? Is this IP different than the one on sama7g5? What are the differences? You need to add the new compatible in the bindings file before using it in dt. I see you use "-qspi" for all the 3 instances of the IP. Does this IP support octal mode? Cheers, ta ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR memory nodes 2022-04-07 10:58 [PATCH 0/2] ARM: dts: Add LAN966x QSPI nodes Kavyasree Kotagiri 2022-04-07 10:58 ` [PATCH 1/2] ARM: dts: lan966x: Add " Kavyasree Kotagiri @ 2022-04-07 10:58 ` Kavyasree Kotagiri 2022-04-07 12:13 ` Krzysztof Kozlowski 2022-04-07 12:26 ` Tudor.Ambarus 1 sibling, 2 replies; 7+ messages in thread From: Kavyasree Kotagiri @ 2022-04-07 10:58 UTC (permalink / raw) To: arnd, robh+dt, krzk+dt, alexandre.belloni, olof, soc, nicolas.ferre Cc: linux-arm-kernel, devicetree, linux-kernel, UNGLinuxDriver, tudor.ambarus, Kavyasree.Kotagiri, Manohar.Puri Enable QSPI0 controller and sst26vf016b SPI-NOR flash present on it. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> --- arch/arm/boot/dts/lan966x-pcb8291.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts index 3281af90ac6d..99d96d46661d 100644 --- a/arch/arm/boot/dts/lan966x-pcb8291.dts +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts @@ -62,3 +62,18 @@ &watchdog { status = "okay"; }; + +&qspi0 { + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <1>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +}; -- 2.17.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR memory nodes 2022-04-07 10:58 ` [PATCH 2/2] ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR memory nodes Kavyasree Kotagiri @ 2022-04-07 12:13 ` Krzysztof Kozlowski 2022-04-07 12:26 ` Tudor.Ambarus 1 sibling, 0 replies; 7+ messages in thread From: Krzysztof Kozlowski @ 2022-04-07 12:13 UTC (permalink / raw) To: Kavyasree Kotagiri, arnd, robh+dt, krzk+dt, alexandre.belloni, olof, soc, nicolas.ferre Cc: linux-arm-kernel, devicetree, linux-kernel, UNGLinuxDriver, tudor.ambarus, Manohar.Puri On 07/04/2022 12:58, Kavyasree Kotagiri wrote: > Enable QSPI0 controller and sst26vf016b SPI-NOR flash present on it. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > arch/arm/boot/dts/lan966x-pcb8291.dts | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts > index 3281af90ac6d..99d96d46661d 100644 > --- a/arch/arm/boot/dts/lan966x-pcb8291.dts > +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts > @@ -62,3 +62,18 @@ > &watchdog { > status = "okay"; > }; > + > +&qspi0 { > + status = "okay"; > + > + spi-flash@0 { Just "flash" please (to be generic). > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <20000000>; > + #address-cells = <1>; > + #size-cells = <1>; Why do you need address/size cells here? You don't have any children. > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + m25p,fast-read; > + }; > +}; Best regards, Krzysztof ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR memory nodes 2022-04-07 10:58 ` [PATCH 2/2] ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR memory nodes Kavyasree Kotagiri 2022-04-07 12:13 ` Krzysztof Kozlowski @ 2022-04-07 12:26 ` Tudor.Ambarus 1 sibling, 0 replies; 7+ messages in thread From: Tudor.Ambarus @ 2022-04-07 12:26 UTC (permalink / raw) To: Kavyasree.Kotagiri, arnd, robh+dt, krzk+dt, alexandre.belloni, olof, soc, Nicolas.Ferre Cc: linux-arm-kernel, devicetree, linux-kernel, UNGLinuxDriver, Manohar.Puri On 4/7/22 13:58, Kavyasree Kotagiri wrote: > Enable QSPI0 controller and sst26vf016b SPI-NOR flash present on it. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > arch/arm/boot/dts/lan966x-pcb8291.dts | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts > index 3281af90ac6d..99d96d46661d 100644 > --- a/arch/arm/boot/dts/lan966x-pcb8291.dts > +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts > @@ -62,3 +62,18 @@ > &watchdog { > status = "okay"; > }; > + > +&qspi0 { > + status = "okay"; > + > + spi-flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <20000000>; You should describe the flash's maximum frequency: • High-Speed Clock Frequency: - 2.7V-3.6V: 104 MHz maximum - 2.3V-3.6V: 80 MHz maximum https://ww1.microchip.com/downloads/aemDocuments/documents/MPD/ProductDocuments/DataSheets/SST26VF016B-2.5V-3.0V-16-Mbit-Serial-Quad-IO-%28SQI%29-Flash-Memory-20005262G.pdf > + #address-cells = <1>; > + #size-cells = <1>; > + spi-tx-bus-width = <4>; > + spi-rx-bus-width = <4>; > + m25p,fast-read; > + }; > +}; ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-04-07 12:26 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-07 10:58 [PATCH 0/2] ARM: dts: Add LAN966x QSPI nodes Kavyasree Kotagiri 2022-04-07 10:58 ` [PATCH 1/2] ARM: dts: lan966x: Add " Kavyasree Kotagiri 2022-04-07 12:07 ` Krzysztof Kozlowski 2022-04-07 12:16 ` Tudor.Ambarus 2022-04-07 10:58 ` [PATCH 2/2] ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR memory nodes Kavyasree Kotagiri 2022-04-07 12:13 ` Krzysztof Kozlowski 2022-04-07 12:26 ` Tudor.Ambarus
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