linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: David Laight <David.Laight@ACULAB.COM>
To: 'Fenghua Yu' <fenghua.yu@intel.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	H Peter Anvin <hpa@zytor.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	Dave Hansen <dave.hansen@intel.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	Radim Krcmar <rkrcmar@redhat.com>,
	Christopherson Sean J <sean.j.christopherson@intel.com>,
	Ashok Raj <ashok.raj@intel.com>, Tony Luck <tony.luck@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	"Xiaoyao Li " <xiaoyao.li@intel.com>,
	"Sai Praneeth Prakhya" <sai.praneeth.prakhya@intel.com>,
	Ravi V Shankar <ravi.v.shankar@intel.com>
Cc: linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Subject: RE: [PATCH v9 02/17] drivers/net/b44: Align pwol_mask to unsigned long for better performance
Date: Mon, 24 Jun 2019 15:12:05 +0000	[thread overview]
Message-ID: <fce80c42ba1949fd8d7924786bbf0ec8@AcuMS.aculab.com> (raw)
In-Reply-To: <1560897679-228028-3-git-send-email-fenghua.yu@intel.com>

From: Fenghua Yu
> Sent: 18 June 2019 23:41
> From: Peter Zijlstra <peterz@infradead.org>
> 
> A bit in pwol_mask is set in b44_magic_pattern() by atomic set_bit().
> But since pwol_mask is local and never exposed to concurrency, there is
> no need to set bit in pwol_mask atomically.
> 
> set_bit() sets the bit in a single unsigned long location. Because
> pwol_mask may not be aligned to unsigned long, the location may cross two
> cache lines. On x86, accessing two cache lines in locked instruction in
> set_bit() is called split locked access and can cause overall performance
> degradation.
> 
> So use non atomic __set_bit() to set pwol_mask bits. __set_bit() won't hit
> split lock issue on x86.
> 
> Signed-off-by: Peter Zijlstra <peterz@infradead.org>
> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
> ---
>  drivers/net/ethernet/broadcom/b44.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/ethernet/broadcom/b44.c b/drivers/net/ethernet/broadcom/b44.c
> index 97ab0dd25552..5738ab963dfb 100644
> --- a/drivers/net/ethernet/broadcom/b44.c
> +++ b/drivers/net/ethernet/broadcom/b44.c
> @@ -1520,7 +1520,7 @@ static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
> 
>  	memset(ppattern + offset, 0xff, magicsync);
>  	for (j = 0; j < magicsync; j++)
> -		set_bit(len++, (unsigned long *) pmask);
> +		__set_bit(len++, (unsigned long *)pmask);
> 
>  	for (j = 0; j < B44_MAX_PATTERNS; j++) {
>  		if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
> @@ -1532,7 +1532,7 @@ static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
>  		for (k = 0; k< ethaddr_bytes; k++) {
>  			ppattern[offset + magicsync +
>  				(j * ETH_ALEN) + k] = macaddr[k];
> -			set_bit(len++, (unsigned long *) pmask);
> +			__set_bit(len++, (unsigned long *)pmask);

Is this code expected to do anything sensible on BE systems?
Casting the bitmask[] argument to any of the set_bit() functions is dubious at best.

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)


  reply	other threads:[~2019-06-24 15:12 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-18 22:41 [PATCH v9 00/17] x86/split_lock: Enable split lock detection Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 01/17] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 02/17] drivers/net/b44: Align pwol_mask to unsigned long for better performance Fenghua Yu
2019-06-24 15:12   ` David Laight [this message]
2019-06-24 18:43     ` Paolo Bonzini
2019-06-18 22:41 ` [PATCH v9 03/17] x86/split_lock: Align x86_capability to unsigned long to avoid split locked access Fenghua Yu
2019-06-24 15:12   ` David Laight
2019-06-25 23:54     ` Fenghua Yu
2019-06-26 19:15       ` Thomas Gleixner
2019-06-18 22:41 ` [PATCH v9 04/17] x86/msr-index: Define MSR_IA32_CORE_CAP and split lock detection bit Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 05/17] x86/cpufeatures: Enumerate MSR_IA32_CORE_CAP Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 06/17] x86/split_lock: Enumerate split lock detection by MSR_IA32_CORE_CAP Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 07/17] x86/split_lock: Enumerate split lock detection on Icelake mobile processor Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 08/17] x86/split_lock: Define MSR TEST_CTL register Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 09/17] x86/split_lock: Handle #AC exception for split lock Fenghua Yu
2019-06-26 20:20   ` Thomas Gleixner
2019-06-26 20:36     ` Fenghua Yu
2019-06-26 21:47       ` Thomas Gleixner
2019-09-25 18:09         ` Sean Christopherson
2019-10-16  6:58           ` Xiaoyao Li
2019-10-16  9:29           ` Thomas Gleixner
2019-10-16 15:59             ` Sean Christopherson
2019-10-16  9:40           ` Paolo Bonzini
2019-10-16  9:47             ` Thomas Gleixner
2019-10-16 10:16               ` Paolo Bonzini
2019-10-16 11:23                 ` Xiaoyao Li
2019-10-16 11:26                   ` Paolo Bonzini
2019-10-16 13:13                     ` Xiaoyao Li
2019-10-16 14:43                       ` Thomas Gleixner
2019-10-16 15:37                         ` Paolo Bonzini
2019-10-16 16:25                           ` Xiaoyao Li
2019-10-16 16:38                             ` Paolo Bonzini
2019-10-17 12:29                           ` [RFD] x86/split_lock: Request to Intel Thomas Gleixner
2019-10-17 17:23                             ` Sean Christopherson
2019-10-17 21:31                               ` Thomas Gleixner
2019-10-17 23:38                                 ` Sean Christopherson
2019-10-17 23:28                             ` Luck, Tony
2019-10-18 10:45                               ` David Laight
2019-10-18 21:03                                 ` hpa
2019-10-18  2:36                             ` Xiaoyao Li
2019-10-18  9:02                               ` Thomas Gleixner
2019-10-18 10:20                                 ` Xiaoyao Li
2019-10-18 10:43                                   ` Peter Zijlstra
2019-10-16 11:49                 ` [PATCH v9 09/17] x86/split_lock: Handle #AC exception for split lock Thomas Gleixner
2019-10-16 11:58                   ` Paolo Bonzini
2019-10-16 13:51                     ` Xiaoyao Li
2019-10-16 14:08                       ` Paolo Bonzini
2019-10-16 14:14                         ` David Laight
2019-10-16 15:03                           ` Thomas Gleixner
2019-10-16 15:41                         ` Sean Christopherson
2019-10-16 15:43                           ` Paolo Bonzini
2019-10-16 16:23                             ` Sean Christopherson
2019-10-16 17:42                               ` Sean Christopherson
2019-10-17  1:23                                 ` Xiaoyao Li
2019-10-21 13:06                                   ` Paolo Bonzini
2019-10-21 13:03                                 ` Paolo Bonzini
2019-10-21 13:02                               ` Paolo Bonzini
2019-10-16 14:50                       ` Thomas Gleixner
2019-06-18 22:41 ` [PATCH v9 10/17] kvm/x86: Emulate MSR IA32_CORE_CAPABILITY Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 11/17] kvm/vmx: Emulate MSR TEST_CTL Fenghua Yu
2019-06-27  2:24   ` Xiaoyao Li
2019-06-27  7:12     ` Thomas Gleixner
2019-06-27  7:58       ` Xiaoyao Li
2019-06-27 12:11         ` Thomas Gleixner
2019-06-27 12:22           ` Xiaoyao Li
2019-06-18 22:41 ` [PATCH v9 12/17] x86/split_lock: Enable split lock detection by default Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 13/17] x86/split_lock: Disable split lock detection by kernel parameter "nosplit_lock_detect" Fenghua Yu
2019-06-26 20:34   ` Thomas Gleixner
2019-06-26 20:37     ` Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 14/17] x86/split_lock: Add a debugfs interface to enable/disable split lock detection during run time Fenghua Yu
2019-06-26 21:37   ` Thomas Gleixner
2019-06-18 22:41 ` [PATCH v9 15/17] x86/split_lock: Add documentation for split lock detection interface Fenghua Yu
2019-06-26 21:51   ` Thomas Gleixner
2019-06-18 22:41 ` [PATCH v9 16/17] x86/split_lock: Reorganize few header files in order to call WARN_ON_ONCE() in atomic bit ops Fenghua Yu
2019-06-18 22:41 ` [PATCH v9 17/17] x86/split_lock: Warn on unaligned address in atomic bit operations Fenghua Yu
2019-06-26 22:00   ` Thomas Gleixner
2019-09-16 22:39 ` [PATCH 0/3] Fix some 4-byte vs. 8-byte alignment issues Tony Luck
2019-09-16 22:39   ` [PATCH 1/3] x86/common: Align cpu_caps_cleared and cpu_caps_set to unsigned long Tony Luck
2019-11-15 19:26     ` [tip: x86/cpu] x86/cpu: " tip-bot2 for Fenghua Yu
2019-09-16 22:39   ` [PATCH 2/3] drivers/net/b44: Align pwol_mask to unsigned long for better performance Tony Luck
2019-09-16 22:39   ` [PATCH 3/3] x86/split_lock: Align the x86_capability array to size of unsigned long Tony Luck
2019-09-17  8:29     ` David Laight
2019-09-17 19:14       ` Luck, Tony
2019-09-18  8:54         ` David Laight
2019-11-15 19:26     ` [tip: x86/cpu] x86/cpu: " tip-bot2 for Fenghua Yu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=fce80c42ba1949fd8d7924786bbf0ec8@AcuMS.aculab.com \
    --to=david.laight@aculab.com \
    --cc=akpm@linux-foundation.org \
    --cc=ashok.raj@intel.com \
    --cc=bp@alien8.de \
    --cc=dan.j.williams@intel.com \
    --cc=dave.hansen@intel.com \
    --cc=fenghua.yu@intel.com \
    --cc=hpa@zytor.com \
    --cc=kvm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=peterz@infradead.org \
    --cc=ravi.v.shankar@intel.com \
    --cc=rkrcmar@redhat.com \
    --cc=sai.praneeth.prakhya@intel.com \
    --cc=sean.j.christopherson@intel.com \
    --cc=tglx@linutronix.de \
    --cc=tony.luck@intel.com \
    --cc=x86@kernel.org \
    --cc=xiaoyao.li@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).