* [PATCH v2 0/4] Add LLCC support for SM8250 SoC
@ 2020-11-30 9:39 Manivannan Sadhasivam
2020-11-30 9:39 ` [PATCH v2 1/4] dt-bindings: msm: Add LLCC for SM8250 Manivannan Sadhasivam
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Manivannan Sadhasivam @ 2020-11-30 9:39 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt
Cc: linux-arm-msm, linux-kernel, dmitry.baryshkov, saiprakash.ranjan,
Manivannan Sadhasivam
Hello,
This series adds Last Level Cache Controller (LLCC) support for SM8250
SoC from Qualcomm.
All 4 patches in this series are expected to go through arm-soc tree.
Thanks,
Mani
Changes in v2:
* Used patch from Sai for using the major version extracted from the IP
instead of a dedicated llcc_v2 flag.
Manivannan Sadhasivam (3):
dt-bindings: msm: Add LLCC for SM8250
arm64: dts: qcom: sm8250: Add support for LLCC block
soc: qcom: llcc-qcom: Add support for SM8250 SoC
Sai Prakash Ranjan (1):
soc: qcom: llcc-qcom: Extract major hardware version
.../bindings/arm/msm/qcom,llcc.yaml | 1 +
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++
drivers/soc/qcom/llcc-qcom.c | 50 +++++++++++++++++++
include/linux/soc/qcom/llcc-qcom.h | 3 ++
4 files changed, 60 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 1/4] dt-bindings: msm: Add LLCC for SM8250 2020-11-30 9:39 [PATCH v2 0/4] Add LLCC support for SM8250 SoC Manivannan Sadhasivam @ 2020-11-30 9:39 ` Manivannan Sadhasivam 2020-11-30 9:39 ` [PATCH v2 2/4] arm64: dts: qcom: sm8250: Add support for LLCC block Manivannan Sadhasivam ` (2 subsequent siblings) 3 siblings, 0 replies; 7+ messages in thread From: Manivannan Sadhasivam @ 2020-11-30 9:39 UTC (permalink / raw) To: agross, bjorn.andersson, robh+dt Cc: linux-arm-msm, linux-kernel, dmitry.baryshkov, saiprakash.ranjan, Manivannan Sadhasivam Add LLCC compatible for SM8250 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 0a9889debc7c..c299dc907f6c 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -24,6 +24,7 @@ properties: - qcom,sc7180-llcc - qcom,sdm845-llcc - qcom,sm8150-llcc + - qcom,sm8250-llcc reg: items: -- 2.25.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/4] arm64: dts: qcom: sm8250: Add support for LLCC block 2020-11-30 9:39 [PATCH v2 0/4] Add LLCC support for SM8250 SoC Manivannan Sadhasivam 2020-11-30 9:39 ` [PATCH v2 1/4] dt-bindings: msm: Add LLCC for SM8250 Manivannan Sadhasivam @ 2020-11-30 9:39 ` Manivannan Sadhasivam 2020-12-01 4:38 ` Sai Prakash Ranjan 2020-11-30 9:39 ` [PATCH v2 3/4] soc: qcom: llcc-qcom: Extract major hardware version Manivannan Sadhasivam 2020-11-30 9:39 ` [PATCH v2 4/4] soc: qcom: llcc-qcom: Add support for SM8250 SoC Manivannan Sadhasivam 3 siblings, 1 reply; 7+ messages in thread From: Manivannan Sadhasivam @ 2020-11-30 9:39 UTC (permalink / raw) To: agross, bjorn.andersson, robh+dt Cc: linux-arm-msm, linux-kernel, dmitry.baryshkov, saiprakash.ranjan, Manivannan Sadhasivam Add support for Last Level Cache Controller (LLCC) in SM8250 SoC. This LLCC is used to provide common cache memory pool for the cores in the SM8250 SoC thereby minimizing the percore caches. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 65acd1f381eb..118b6bb29ebc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1758,6 +1758,12 @@ usb_1_dwc3: dwc3@a600000 { }; }; + system-cache-controller@9200000 { + compatible = "qcom,sm8250-llcc"; + reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + }; + usb_2: usb@a8f8800 { compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; reg = <0 0x0a8f8800 0 0x400>; -- 2.25.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/4] arm64: dts: qcom: sm8250: Add support for LLCC block 2020-11-30 9:39 ` [PATCH v2 2/4] arm64: dts: qcom: sm8250: Add support for LLCC block Manivannan Sadhasivam @ 2020-12-01 4:38 ` Sai Prakash Ranjan 0 siblings, 0 replies; 7+ messages in thread From: Sai Prakash Ranjan @ 2020-12-01 4:38 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: agross, bjorn.andersson, robh+dt, linux-arm-msm, linux-kernel, dmitry.baryshkov On 2020-11-30 15:09, Manivannan Sadhasivam wrote: > Add support for Last Level Cache Controller (LLCC) in SM8250 SoC. > This LLCC is used to provide common cache memory pool for the cores in > the SM8250 SoC thereby minimizing the percore caches. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi > b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index 65acd1f381eb..118b6bb29ebc 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -1758,6 +1758,12 @@ usb_1_dwc3: dwc3@a600000 { > }; > }; > > + system-cache-controller@9200000 { > + compatible = "qcom,sm8250-llcc"; > + reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; > + reg-names = "llcc_base", "llcc_broadcast_base"; > + }; > + > usb_2: usb@a8f8800 { > compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; > reg = <0 0x0a8f8800 0 0x400>; Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/4] soc: qcom: llcc-qcom: Extract major hardware version 2020-11-30 9:39 [PATCH v2 0/4] Add LLCC support for SM8250 SoC Manivannan Sadhasivam 2020-11-30 9:39 ` [PATCH v2 1/4] dt-bindings: msm: Add LLCC for SM8250 Manivannan Sadhasivam 2020-11-30 9:39 ` [PATCH v2 2/4] arm64: dts: qcom: sm8250: Add support for LLCC block Manivannan Sadhasivam @ 2020-11-30 9:39 ` Manivannan Sadhasivam 2020-11-30 9:39 ` [PATCH v2 4/4] soc: qcom: llcc-qcom: Add support for SM8250 SoC Manivannan Sadhasivam 3 siblings, 0 replies; 7+ messages in thread From: Manivannan Sadhasivam @ 2020-11-30 9:39 UTC (permalink / raw) To: agross, bjorn.andersson, robh+dt Cc: linux-arm-msm, linux-kernel, dmitry.baryshkov, saiprakash.ranjan, Manivannan Sadhasivam From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> The major hardware version of the LLCC IP is encoded in its LLCC_COMMON_HW_INFO register. Extract the version and cache it in the driver data so that it can be used to implement version specific functionality like enabling Write sub cache for given SCID. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> [mani: splitted the version extract as a single patch and few cleanups] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/soc/qcom/llcc-qcom.c | 12 ++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 16b421608e9c..a559617ea7c0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -4,6 +4,7 @@ * */ +#include <linux/bitfield.h> #include <linux/bitmap.h> #include <linux/bitops.h> #include <linux/device.h> @@ -35,6 +36,9 @@ #define CACHE_LINE_SIZE_SHIFT 6 +#define LLCC_COMMON_HW_INFO 0x00030000 +#define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24) + #define LLCC_COMMON_STATUS0 0x0003000c #define LLCC_LB_CNT_MASK GENMASK(31, 28) #define LLCC_LB_CNT_SHIFT 28 @@ -476,6 +480,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct qcom_llcc_config *cfg; const struct llcc_slice_config *llcc_cfg; u32 sz; + u32 version; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -496,6 +501,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } + /* Extract major version of the IP */ + ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version); + if (ret) + goto err; + + drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version); + ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0, &num_banks); if (ret) diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 3db6797ba6ff..d17a3de80510 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -79,6 +79,7 @@ struct llcc_edac_reg_data { * @bitmap: Bit map to track the active slice ids * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting + * @major_version: Indicates the LLCC major version */ struct llcc_drv_data { struct regmap *regmap; @@ -91,6 +92,7 @@ struct llcc_drv_data { unsigned long *bitmap; u32 *offsets; int ecc_irq; + u32 major_version; }; #if IS_ENABLED(CONFIG_QCOM_LLCC) -- 2.25.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 4/4] soc: qcom: llcc-qcom: Add support for SM8250 SoC 2020-11-30 9:39 [PATCH v2 0/4] Add LLCC support for SM8250 SoC Manivannan Sadhasivam ` (2 preceding siblings ...) 2020-11-30 9:39 ` [PATCH v2 3/4] soc: qcom: llcc-qcom: Extract major hardware version Manivannan Sadhasivam @ 2020-11-30 9:39 ` Manivannan Sadhasivam 2020-12-01 6:24 ` Sai Prakash Ranjan 3 siblings, 1 reply; 7+ messages in thread From: Manivannan Sadhasivam @ 2020-11-30 9:39 UTC (permalink / raw) To: agross, bjorn.andersson, robh+dt Cc: linux-arm-msm, linux-kernel, dmitry.baryshkov, saiprakash.ranjan, Manivannan Sadhasivam SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN register needs to be written to enable the Write Sub Cache for each SCID. Hence, use a dedicated "write_scid_en" member with predefined values and write them for LLCC IP version 2. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/soc/qcom/llcc-qcom.c | 38 ++++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 1 + 2 files changed, 39 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index a559617ea7c0..8403a77b59fe 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -51,6 +51,7 @@ #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 #define LLCC_TRP_PCB_ACT 0x21f04 +#define LLCC_TRP_WRSC_EN 0x21f20 #define BANK_OFFSET_STRIDE 0x80000 @@ -77,6 +78,7 @@ * then the ways assigned to this client are not flushed on power * collapse. * @activate_on_init: Activate the slice immediately after it is programmed + * @write_scid_en: Bit enables write cache support for a given scid. */ struct llcc_slice_config { u32 usecase_id; @@ -91,6 +93,7 @@ struct llcc_slice_config { bool dis_cap_alloc; bool retain_on_pc; bool activate_on_init; + bool write_scid_en; }; struct qcom_llcc_config { @@ -151,6 +154,25 @@ static const struct llcc_slice_config sm8150_data[] = { { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, }; +static const struct llcc_slice_config sm8250_data[] = { + { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, + { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, + { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, + { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, + { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, + { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, +}; + static const struct qcom_llcc_config sc7180_cfg = { .sct_data = sc7180_data, .size = ARRAY_SIZE(sc7180_data), @@ -168,6 +190,11 @@ static const struct qcom_llcc_config sm8150_cfg = { .size = ARRAY_SIZE(sm8150_data), }; +static const struct qcom_llcc_config sm8250_cfg = { + .sct_data = sm8250_data, + .size = ARRAY_SIZE(sm8250_data), +}; + static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; /** @@ -417,6 +444,16 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, return ret; } + if (drv_data->major_version == 2) { + u32 wren; + + wren = config->write_scid_en << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, + BIT(config->slice_id), wren); + if (ret) + return ret; + } + if (config->activate_on_init) { desc.slice_id = config->slice_id; ret = llcc_slice_activate(&desc); @@ -571,6 +608,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, + { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, { } }; diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index d17a3de80510..64fc582ae415 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -29,6 +29,7 @@ #define LLCC_AUDHW 22 #define LLCC_NPU 23 #define LLCC_WLHW 24 +#define LLCC_CVP 28 #define LLCC_MODPE 29 #define LLCC_APTCM 30 #define LLCC_WRCACHE 31 -- 2.25.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 4/4] soc: qcom: llcc-qcom: Add support for SM8250 SoC 2020-11-30 9:39 ` [PATCH v2 4/4] soc: qcom: llcc-qcom: Add support for SM8250 SoC Manivannan Sadhasivam @ 2020-12-01 6:24 ` Sai Prakash Ranjan 0 siblings, 0 replies; 7+ messages in thread From: Sai Prakash Ranjan @ 2020-12-01 6:24 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: agross, bjorn.andersson, robh+dt, linux-arm-msm, linux-kernel, dmitry.baryshkov On 2020-11-30 15:09, Manivannan Sadhasivam wrote: > SM8250 SoC uses LLCC IP version 2. In this version, the WRSC_EN > register > needs to be written to enable the Write Sub Cache for each SCID. Hence, > use a dedicated "write_scid_en" member with predefined values and write > them for LLCC IP version 2. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > drivers/soc/qcom/llcc-qcom.c | 38 ++++++++++++++++++++++++++++++ > include/linux/soc/qcom/llcc-qcom.h | 1 + > 2 files changed, 39 insertions(+) > > diff --git a/drivers/soc/qcom/llcc-qcom.c > b/drivers/soc/qcom/llcc-qcom.c > index a559617ea7c0..8403a77b59fe 100644 > --- a/drivers/soc/qcom/llcc-qcom.c > +++ b/drivers/soc/qcom/llcc-qcom.c > @@ -51,6 +51,7 @@ > > #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 > #define LLCC_TRP_PCB_ACT 0x21f04 > +#define LLCC_TRP_WRSC_EN 0x21f20 > > #define BANK_OFFSET_STRIDE 0x80000 > > @@ -77,6 +78,7 @@ > * then the ways assigned to this client are not flushed > on power > * collapse. > * @activate_on_init: Activate the slice immediately after it is > programmed > + * @write_scid_en: Bit enables write cache support for a given scid. > */ > struct llcc_slice_config { > u32 usecase_id; > @@ -91,6 +93,7 @@ struct llcc_slice_config { > bool dis_cap_alloc; > bool retain_on_pc; > bool activate_on_init; > + bool write_scid_en; > }; > > struct qcom_llcc_config { > @@ -151,6 +154,25 @@ static const struct llcc_slice_config > sm8150_data[] = { > { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, > }; > > +static const struct llcc_slice_config sm8250_data[] = { > + { LLCC_CPUSS, 1, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, > + { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_AUDIO, 6, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, > + { LLCC_CMPT, 10, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, > + { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_GPU, 12, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, > + { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, > + { LLCC_CMPTDMA, 15, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_DISP, 16, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_VIDFW, 17, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_NPU, 23, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_WLHW, 24, 1024, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_CVP, 28, 256, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, > + { LLCC_APTCM, 30, 128, 3, 0, 0x0, 0x3, 1, 0, 0, 1, 0, 0 }, > + { LLCC_WRCACHE, 31, 256, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, > +}; > + > static const struct qcom_llcc_config sc7180_cfg = { > .sct_data = sc7180_data, > .size = ARRAY_SIZE(sc7180_data), > @@ -168,6 +190,11 @@ static const struct qcom_llcc_config sm8150_cfg = > { > .size = ARRAY_SIZE(sm8150_data), > }; > > +static const struct qcom_llcc_config sm8250_cfg = { > + .sct_data = sm8250_data, > + .size = ARRAY_SIZE(sm8250_data), > +}; > + > static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; > > /** > @@ -417,6 +444,16 @@ static int _qcom_llcc_cfg_program(const struct > llcc_slice_config *config, > return ret; > } > > + if (drv_data->major_version == 2) { > + u32 wren; > + > + wren = config->write_scid_en << config->slice_id; > + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_EN, > + BIT(config->slice_id), wren); > + if (ret) > + return ret; > + } > + > if (config->activate_on_init) { > desc.slice_id = config->slice_id; > ret = llcc_slice_activate(&desc); > @@ -571,6 +608,7 @@ static const struct of_device_id > qcom_llcc_of_match[] = { > { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, > { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, > { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, > + { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, > { } > }; > > diff --git a/include/linux/soc/qcom/llcc-qcom.h > b/include/linux/soc/qcom/llcc-qcom.h > index d17a3de80510..64fc582ae415 100644 > --- a/include/linux/soc/qcom/llcc-qcom.h > +++ b/include/linux/soc/qcom/llcc-qcom.h > @@ -29,6 +29,7 @@ > #define LLCC_AUDHW 22 > #define LLCC_NPU 23 > #define LLCC_WLHW 24 > +#define LLCC_CVP 28 > #define LLCC_MODPE 29 > #define LLCC_APTCM 30 > #define LLCC_WRCACHE 31 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-12-01 6:25 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-11-30 9:39 [PATCH v2 0/4] Add LLCC support for SM8250 SoC Manivannan Sadhasivam 2020-11-30 9:39 ` [PATCH v2 1/4] dt-bindings: msm: Add LLCC for SM8250 Manivannan Sadhasivam 2020-11-30 9:39 ` [PATCH v2 2/4] arm64: dts: qcom: sm8250: Add support for LLCC block Manivannan Sadhasivam 2020-12-01 4:38 ` Sai Prakash Ranjan 2020-11-30 9:39 ` [PATCH v2 3/4] soc: qcom: llcc-qcom: Extract major hardware version Manivannan Sadhasivam 2020-11-30 9:39 ` [PATCH v2 4/4] soc: qcom: llcc-qcom: Add support for SM8250 SoC Manivannan Sadhasivam 2020-12-01 6:24 ` Sai Prakash Ranjan
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