From: Marijn Suijten <marijn.suijten@somainline.org>
To: Jessica Zhang <quic_jesszhan@quicinc.com>
Cc: Rob Clark <robdclark@gmail.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
quic_abhinavk@quicinc.com, linux-arm-msm@vger.kernel.org,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] drm/msm/dsi: Enable DATABUS_WIDEN for DSI command mode
Date: Wed, 14 Jun 2023 11:56:35 +0200 [thread overview]
Message-ID: <ky7sgsaohak2pcdf6pbhedfyrwk4ea7y3ekfqlw7rn6cpk4rhe@rjuhb23n37oz> (raw)
In-Reply-To: <20230525-add-widebus-support-v1-3-c7069f2efca1@quicinc.com>
On 2023-06-13 18:57:13, Jessica Zhang wrote:
> DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
> 48 bits of compressed data per pclk instead of 24.
>
> For all chipsets that support this mode, enable it whenever DSC is
> enabled as recommend by the hardware programming guide.
>
> Only enable this for command mode as we are currently unable to validate
> it for video mode.
>
> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
> ---
>
> Note: The dsi.xml.h changes were generated using the headergen2 script in
> envytools [1], but the changes to the copyright and rules-ng-ng source file
> paths were dropped.
>
> [1] https://github.com/freedreno/envytools/
More interesting would be a link to the Mesa MR upstreaming this
bitfield to dsi.xml [2] (which I have not found on my own yet).
[2]: https://gitlab.freedesktop.org/mesa/mesa/-/blame/main/src/freedreno/registers/dsi/dsi.xml
> drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 +
> drivers/gpu/drm/msm/dsi/dsi_host.c | 19 ++++++++++++++++++-
> 2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> index a4a154601114..2a7d980e12c3 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> @@ -664,6 +664,7 @@ static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap v
> return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
> }
> #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
> +#define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x00100000
>
> #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
> #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 5d7b4409e4e9..1da5238e7105 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -927,6 +927,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> u32 hdisplay = mode->hdisplay;
> u32 wc;
> int ret;
> + bool widebus_supported = msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&
> + msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0;
> +
>
> DBG("");
>
> @@ -973,8 +976,15 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> *
> * hdisplay will be divided by 3 here to account for the fact
> * that DPU sends 3 bytes per pclk cycle to DSI.
> + *
> + * If widebus is supported, set DATABUS_WIDEN register and divide hdisplay by 6
> + * instead of 3
So this should allow us to divide pclk by 2, or have much lower latency?
Otherwise it'll tick enough times to transmit the data twice.
Note that I brought up the exact same concerns when you used the 3:1
ratio from dsi_bpp / dsc_bpp in your pclk reduction patch (instad of the
number of bits/bytes that DPU sends to DSI per pclk), but no-one has
replied to my inquiry yet.
> */
> - hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
> + if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && widebus_supported)
> + hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 6);
> + else
> + hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
Nit: I wonder if this is more concise when written as:
u32 bytes_per_pclk;
...
if (!video && widebus)
bytes_per_pclk = 6;
else
bytes_per_pclk = 3;
hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc),
bytes_per_pclk);
That is less duplication, **and** the value becomes self-documenting!
> +
> h_total += hdisplay;
> ha_end = ha_start + hdisplay;
> }
> @@ -1027,6 +1037,13 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
> DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
> DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
> +
> + if (msm_host->dsc && widebus_supported) {
Can we also support widebus for uncompressed streams (sending 2 pixels
of bpp=24 per pclk), and if so, is that something you want to add in the
future (a comment would be nice)?
> + u32 mdp_ctrl2 = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2);
> +
> + mdp_ctrl2 |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN;
> + dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, mdp_ctrl2);
> + }
Same comment as on your BURST_MODE patch (which this'll conflict with):
does this belong to the timing setup or is it better moved to
dsi_ctrl_config?
- Marijn
> }
> }
>
>
> --
> 2.40.1
>
next prev parent reply other threads:[~2023-06-14 9:56 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 1:57 [PATCH 0/3] Add support for databus widen mode Jessica Zhang
2023-06-14 1:57 ` [PATCH 1/3] drm/msm/dpu: Add DPU_INTF_DATABUS_WIDEN feature flag for DPU >= 5.0 Jessica Zhang
2023-06-14 7:50 ` Dmitry Baryshkov
2023-06-14 11:42 ` Marijn Suijten
2023-06-14 12:01 ` Dmitry Baryshkov
2023-06-14 12:23 ` Marijn Suijten
2023-06-14 19:35 ` Abhinav Kumar
2023-06-14 19:54 ` Abhinav Kumar
2023-06-14 20:39 ` [Freedreno] " Abhinav Kumar
2023-06-14 20:43 ` Dmitry Baryshkov
2023-06-16 21:10 ` Abhinav Kumar
2023-06-17 0:37 ` Dmitry Baryshkov
2023-06-20 21:37 ` Jessica Zhang
2023-06-20 22:11 ` Dmitry Baryshkov
2023-06-20 23:37 ` Jessica Zhang
2023-06-14 21:41 ` Marijn Suijten
2023-06-16 21:13 ` Abhinav Kumar
2023-06-16 21:58 ` Marijn Suijten
2023-06-14 22:49 ` Marijn Suijten
2023-06-16 21:06 ` Abhinav Kumar
2023-06-16 22:00 ` Marijn Suijten
2023-06-14 1:57 ` [PATCH 2/3] drm/msm/dpu: Set DATABUS_WIDEN on command mode encoders Jessica Zhang
2023-06-14 7:56 ` Dmitry Baryshkov
2023-06-16 21:18 ` Abhinav Kumar
2023-06-16 21:54 ` Marijn Suijten
2023-06-17 0:35 ` Dmitry Baryshkov
2023-06-20 21:38 ` Jessica Zhang
2023-06-20 22:10 ` Dmitry Baryshkov
2023-06-21 15:17 ` Marijn Suijten
2023-06-21 16:36 ` Dmitry Baryshkov
2023-06-21 19:00 ` Marijn Suijten
2023-06-21 23:01 ` Abhinav Kumar
2023-06-21 23:46 ` Dmitry Baryshkov
2023-06-22 22:37 ` Abhinav Kumar
2023-06-22 23:14 ` Dmitry Baryshkov
2023-06-22 23:37 ` [Freedreno] " Abhinav Kumar
2023-06-29 17:26 ` Abhinav Kumar
2023-06-29 17:37 ` Jessica Zhang
2023-06-14 1:57 ` [PATCH 3/3] drm/msm/dsi: Enable DATABUS_WIDEN for DSI command mode Jessica Zhang
2023-06-14 7:49 ` Dmitry Baryshkov
2023-06-14 10:03 ` Marijn Suijten
2023-06-22 23:04 ` Abhinav Kumar
2023-06-23 7:02 ` Marijn Suijten
2023-06-16 21:23 ` Abhinav Kumar
2023-06-14 9:56 ` Marijn Suijten [this message]
2023-06-23 0:01 ` [Freedreno] " Abhinav Kumar
2023-06-23 0:41 ` Dmitry Baryshkov
2023-06-23 7:19 ` Marijn Suijten
2023-06-23 17:29 ` Abhinav Kumar
2023-06-23 20:14 ` Marijn Suijten
2023-06-23 20:34 ` Abhinav Kumar
2023-06-23 21:33 ` Marijn Suijten
2023-06-23 21:47 ` Abhinav Kumar
2023-06-14 10:09 ` [PATCH 0/3] Add support for databus widen mode Marijn Suijten
2023-06-16 11:30 ` Dmitry Baryshkov
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