* [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC
@ 2020-12-10 10:28 Yash Shah
2020-12-10 10:28 ` [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740 Yash Shah
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Yash Shah @ 2020-12-10 10:28 UTC (permalink / raw)
To: linux-kernel, linux-riscv, devicetree
Cc: bp, anup, Jonathan.Cameron, wsa, sam, aou, palmer, paul.walmsley,
robh+dt, sagar.kadam, sachin.ghadi, Yash Shah
Add support for additional interrupt present in SiFive FU740 chip.
Changes:
v3:
- Rename the subject line of dt-binding patch
- Add the additional interrupt "DirFail" as the last entry so as to keep
the order of all previous index same.
v2:
- Changes as per Rob Herring's request on v1
Yash Shah (2):
dt-bindings: riscv: Update l2 cache DT documentation to add support
for SiFive FU740
RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive
FU740
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
drivers/soc/sifive/sifive_l2_cache.c | 27 +++++++++++++++--
2 files changed, 54 insertions(+), 7 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740
2020-12-10 10:28 [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC Yash Shah
@ 2020-12-10 10:28 ` Yash Shah
2020-12-11 1:55 ` Palmer Dabbelt
2020-12-11 3:46 ` Rob Herring
2020-12-10 10:28 ` [PATCH v3 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support " Yash Shah
2021-01-08 1:36 ` [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC Palmer Dabbelt
2 siblings, 2 replies; 6+ messages in thread
From: Yash Shah @ 2020-12-10 10:28 UTC (permalink / raw)
To: linux-kernel, linux-riscv, devicetree
Cc: bp, anup, Jonathan.Cameron, wsa, sam, aou, palmer, paul.walmsley,
robh+dt, sagar.kadam, sachin.ghadi, Yash Shah
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
compared to 3 in FU540. Update the DT documentation accordingly with
"compatible" and "interrupt" property changes.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
.../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
1 file changed, 30 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index efc0198..6a576dc 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -27,6 +27,7 @@ select:
items:
- enum:
- sifive,fu540-c000-ccache
+ - sifive,fu740-c000-ccache
required:
- compatible
@@ -34,7 +35,9 @@ select:
properties:
compatible:
items:
- - const: sifive,fu540-c000-ccache
+ - enum:
+ - sifive,fu540-c000-ccache
+ - sifive,fu740-c000-ccache
- const: cache
cache-block-size:
@@ -52,10 +55,13 @@ properties:
cache-unified: true
interrupts:
- description: |
- Must contain entries for DirError, DataError and DataFail signals.
minItems: 3
- maxItems: 3
+ maxItems: 4
+ items:
+ - description: DirError interrupt
+ - description: DataError interrupt
+ - description: DataFail interrupt
+ - description: DirFail interrupt
reg:
maxItems: 1
@@ -67,6 +73,26 @@ properties:
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
+if:
+ properties:
+ compatible:
+ contains:
+ const: sifive,fu540-c000-ccache
+
+then:
+ properties:
+ interrupts:
+ description: |
+ Must contain entries for DirError, DataError and DataFail signals.
+ maxItems: 3
+
+else:
+ properties:
+ interrupts:
+ description: |
+ Must contain entries for DirError, DataError, DataFail, DirFail signals.
+ minItems: 4
+
additionalProperties: false
required:
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740
2020-12-10 10:28 [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC Yash Shah
2020-12-10 10:28 ` [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740 Yash Shah
@ 2020-12-10 10:28 ` Yash Shah
2021-01-08 1:36 ` [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC Palmer Dabbelt
2 siblings, 0 replies; 6+ messages in thread
From: Yash Shah @ 2020-12-10 10:28 UTC (permalink / raw)
To: linux-kernel, linux-riscv, devicetree
Cc: bp, anup, Jonathan.Cameron, wsa, sam, aou, palmer, paul.walmsley,
robh+dt, sagar.kadam, sachin.ghadi, Yash Shah
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
drivers/soc/sifive/sifive_l2_cache.c | 27 ++++++++++++++++++++++++---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 44d7e19..59640a1 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -17,6 +17,10 @@
#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
+#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
+#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
+#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
+
#define SIFIVE_L2_DATECCFIX_LOW 0x140
#define SIFIVE_L2_DATECCFIX_HIGH 0x144
#define SIFIVE_L2_DATECCFIX_COUNT 0x148
@@ -29,7 +33,7 @@
#define SIFIVE_L2_WAYENABLE 0x08
#define SIFIVE_L2_ECCINJECTERR 0x40
-#define SIFIVE_L2_MAX_ECCINTR 3
+#define SIFIVE_L2_MAX_ECCINTR 4
static void __iomem *l2_base;
static int g_irq[SIFIVE_L2_MAX_ECCINTR];
@@ -39,6 +43,7 @@ enum {
DIR_CORR = 0,
DATA_CORR,
DATA_UNCORR,
+ DIR_UNCORR,
};
#ifdef CONFIG_DEBUG_FS
@@ -93,6 +98,7 @@ static void l2_config_read(void)
static const struct of_device_id sifive_l2_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
+ { .compatible = "sifive,fu740-c000-ccache" },
{ /* end of table */ },
};
@@ -155,6 +161,15 @@ static irqreturn_t l2_int_handler(int irq, void *device)
atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
"DirECCFix");
}
+ if (irq == g_irq[DIR_UNCORR]) {
+ add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
+ add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
+ /* Reading this register clears the DirFail interrupt sig */
+ readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
+ atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
+ "DirECCFail");
+ panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
+ }
if (irq == g_irq[DATA_CORR]) {
add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
@@ -181,7 +196,7 @@ static int __init sifive_l2_init(void)
{
struct device_node *np;
struct resource res;
- int i, rc;
+ int i, rc, intr_num;
np = of_find_matching_node(NULL, sifive_l2_ids);
if (!np)
@@ -194,7 +209,13 @@ static int __init sifive_l2_init(void)
if (!l2_base)
return -ENOMEM;
- for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
+ intr_num = of_property_count_u32_elems(np, "interrupts");
+ if (!intr_num) {
+ pr_err("L2CACHE: no interrupts property\n");
+ return -ENODEV;
+ }
+
+ for (i = 0; i < intr_num; i++) {
g_irq[i] = irq_of_parse_and_map(np, i);
rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
if (rc) {
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740
2020-12-10 10:28 ` [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740 Yash Shah
@ 2020-12-11 1:55 ` Palmer Dabbelt
2020-12-11 3:46 ` Rob Herring
1 sibling, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2020-12-11 1:55 UTC (permalink / raw)
To: yash.shah
Cc: linux-kernel, linux-riscv, devicetree, bp, anup,
Jonathan.Cameron, wsa, sam, aou, Paul Walmsley, robh+dt,
sagar.kadam, sachin.ghadi, yash.shah
On Thu, 10 Dec 2020 02:28:02 PST (-0800), yash.shah@sifive.com wrote:
> The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> compared to 3 in FU540. Update the DT documentation accordingly with
> "compatible" and "interrupt" property changes.
This generally looks good to me, but I'd prefer to get an ack from the DT folks
as I do frequently miss stuff in the bindings.
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
> 1 file changed, 30 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> index efc0198..6a576dc 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> @@ -27,6 +27,7 @@ select:
> items:
> - enum:
> - sifive,fu540-c000-ccache
> + - sifive,fu740-c000-ccache
>
> required:
> - compatible
> @@ -34,7 +35,9 @@ select:
> properties:
> compatible:
> items:
> - - const: sifive,fu540-c000-ccache
> + - enum:
> + - sifive,fu540-c000-ccache
> + - sifive,fu740-c000-ccache
> - const: cache
>
> cache-block-size:
> @@ -52,10 +55,13 @@ properties:
> cache-unified: true
>
> interrupts:
> - description: |
> - Must contain entries for DirError, DataError and DataFail signals.
> minItems: 3
> - maxItems: 3
> + maxItems: 4
> + items:
> + - description: DirError interrupt
> + - description: DataError interrupt
> + - description: DataFail interrupt
> + - description: DirFail interrupt
>
> reg:
> maxItems: 1
> @@ -67,6 +73,26 @@ properties:
> The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
> The reserved memory node should be defined as per the bindings in reserved-memory.txt.
>
> +if:
> + properties:
> + compatible:
> + contains:
> + const: sifive,fu540-c000-ccache
> +
> +then:
> + properties:
> + interrupts:
> + description: |
> + Must contain entries for DirError, DataError and DataFail signals.
> + maxItems: 3
> +
> +else:
> + properties:
> + interrupts:
> + description: |
> + Must contain entries for DirError, DataError, DataFail, DirFail signals.
> + minItems: 4
> +
> additionalProperties: false
>
> required:
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740
2020-12-10 10:28 ` [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740 Yash Shah
2020-12-11 1:55 ` Palmer Dabbelt
@ 2020-12-11 3:46 ` Rob Herring
1 sibling, 0 replies; 6+ messages in thread
From: Rob Herring @ 2020-12-11 3:46 UTC (permalink / raw)
To: Yash Shah
Cc: anup, bp, paul.walmsley, sagar.kadam, sachin.ghadi, devicetree,
palmer, linux-kernel, linux-riscv, robh+dt, aou,
Jonathan.Cameron, sam, wsa
On Thu, 10 Dec 2020 15:58:02 +0530, Yash Shah wrote:
> The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> compared to 3 in FU540. Update the DT documentation accordingly with
> "compatible" and "interrupt" property changes.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
> 1 file changed, 30 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC
2020-12-10 10:28 [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC Yash Shah
2020-12-10 10:28 ` [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740 Yash Shah
2020-12-10 10:28 ` [PATCH v3 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support " Yash Shah
@ 2021-01-08 1:36 ` Palmer Dabbelt
2 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2021-01-08 1:36 UTC (permalink / raw)
To: yash.shah
Cc: linux-kernel, linux-riscv, devicetree, bp, anup,
Jonathan.Cameron, wsa, sam, aou, Paul Walmsley, robh+dt,
sagar.kadam, sachin.ghadi, yash.shah
On Thu, 10 Dec 2020 02:28:01 PST (-0800), yash.shah@sifive.com wrote:
> Add support for additional interrupt present in SiFive FU740 chip.
>
> Changes:
> v3:
> - Rename the subject line of dt-binding patch
> - Add the additional interrupt "DirFail" as the last entry so as to keep
> the order of all previous index same.
>
> v2:
> - Changes as per Rob Herring's request on v1
>
> Yash Shah (2):
> dt-bindings: riscv: Update l2 cache DT documentation to add support
> for SiFive FU740
> RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive
> FU740
>
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
> drivers/soc/sifive/sifive_l2_cache.c | 27 +++++++++++++++--
> 2 files changed, 54 insertions(+), 7 deletions(-)
Thanks, these are on for-next.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-01-08 1:37 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-10 10:28 [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC Yash Shah
2020-12-10 10:28 ` [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740 Yash Shah
2020-12-11 1:55 ` Palmer Dabbelt
2020-12-11 3:46 ` Rob Herring
2020-12-10 10:28 ` [PATCH v3 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support " Yash Shah
2021-01-08 1:36 ` [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC Palmer Dabbelt
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).