From: Maxime Ripard <maxime@cerno.tech>
To: Roman Beranek <romanberanek@icloud.com>
Cc: Frank Oltmanns <frank@oltmanns.dev>, Chen-Yu Tsai <wens@csie.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] drm/sun4i: uncouple DSI dotclock divider from TCON0_DCLK_REG
Date: Wed, 5 Apr 2023 17:03:26 +0200 [thread overview]
Message-ID: <pu3vdz4gnkwgn4thg6tndbnvfroevpnq75bqbfv7yyrh4gkv63@xxl3dsjf2ih3> (raw)
In-Reply-To: <CROTQHUM88W0.2URPO95U5ZMS5@void.crly.cz>
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On Wed, Apr 05, 2023 at 02:34:11PM +0200, Roman Beranek wrote:
> Hello Maxime,
>
> On Wed Mar 29, 2023 at 9:58 PM CEST, Maxime Ripard wrote:
> > > In order to preserve semantic correctness however, I propose to preface
> > > the change with a patch that renames sun4i_dotclock and tcon-pixel-clock
> > > such that dot/pixel is replaced with d/data. What do you think?
> >
> > I don't think it's exposed to the userspace in any way so it makes sense to me
> >
>
> Here's a new series that includes those renames:
> <https://lore.kernel.org/all/20230331110245.43527-1-me@crly.cz/>
>
> It turns out however that the new dclk rates can't be set exactly as
> requested without touching pll-video0*, tcon0 now therefore gets
> reparented from pll-mipi to pll-video0-2x which, as it further turns
> out, breaks DSI. While simply forbidding the video0-2x mux option seems
> to me as the right way to go because there's not much use for it with
> non-DSI interfaces either besides the opportunity to power pll-mipi
> down, I'd like to run by you first.
Sounds reasonable
> * As pll-mipi doesn't have CLK_SET_RATE_PARENT flag set, pll-video0
> retains its boot-time rate of 294 MHz set by sunxi-dw-hdmi driver
> in u-boot. Why 294 MHz (as opposed to the default rate of 297 MHz)?
> The driver actually asks for 297 MHz, clock_set_pll3 rounds it to
> 294 MHz though because it limits itself to 6 MHz steps.
We could also address that though
Maxime
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next prev parent reply other threads:[~2023-04-05 15:03 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 16:16 [PATCH] drm/sun4i: uncouple DSI dotclock divider from TCON0_DCLK_REG Roman Beranek
2023-03-21 14:56 ` Maxime Ripard
2023-03-21 16:50 ` Roman Beranek
2023-03-21 20:53 ` Roman Beranek
2023-03-27 20:21 ` Maxime Ripard
2023-03-25 11:40 ` Frank Oltmanns
2023-03-27 20:20 ` Maxime Ripard
2023-03-27 23:48 ` Roman Beranek
2023-03-29 19:58 ` Maxime Ripard
2023-03-30 4:45 ` Frank Oltmanns
2023-03-31 5:36 ` Roman Beranek
2023-04-05 12:34 ` Roman Beranek
2023-04-05 15:03 ` Maxime Ripard [this message]
2023-04-12 7:14 ` Roman Beranek
2023-04-12 14:09 ` Maxime Ripard
2023-04-08 7:07 ` Jernej Škrabec
2023-04-12 1:22 ` Roman Beranek
2023-03-28 19:28 ` Frank Oltmanns
2023-03-29 19:56 ` Maxime Ripard
2023-03-30 4:41 ` Frank Oltmanns
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