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From: tip-bot for Yazen Ghannam <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: tglx@linutronix.de, tony.luck@intel.com, bp@alien8.de,
	torvalds@linux-foundation.org, bp@suse.de,
	aravindksg.lkml@gmail.com, peterz@infradead.org, hpa@zytor.com,
	luto@amacapital.net, brgerst@gmail.com,
	linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
	dvlasenk@redhat.com, Yazen.Ghannam@amd.com, mingo@kernel.org
Subject: [tip:ras/core] x86/RAS: Add SMCA support to AMD Error Injector
Date: Thu, 12 May 2016 03:29:06 -0700
Message-ID: <tip-754a92305980b1fecffe033dd3fdc49c37f8e4b0@git.kernel.org> (raw)
In-Reply-To: <1462971509-3856-8-git-send-email-bp@alien8.de>

Commit-ID:  754a92305980b1fecffe033dd3fdc49c37f8e4b0
Gitweb:     http://git.kernel.org/tip/754a92305980b1fecffe033dd3fdc49c37f8e4b0
Author:     Yazen Ghannam <Yazen.Ghannam@amd.com>
AuthorDate: Wed, 11 May 2016 14:58:29 +0200
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 12 May 2016 09:08:23 +0200

x86/RAS: Add SMCA support to AMD Error Injector

Use SMCA MSRs when writing to MCA_{STATUS,ADDR,MISC} and
MCA_DE{STAT,ADDR} when injecting Deferred Errors on SMCA platforms.

Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1462971509-3856-8-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/ras/mce_amd_inj.c | 31 +++++++++++++++++++++++++------
 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/arch/x86/ras/mce_amd_inj.c b/arch/x86/ras/mce_amd_inj.c
index 9e02dca..e69f470 100644
--- a/arch/x86/ras/mce_amd_inj.c
+++ b/arch/x86/ras/mce_amd_inj.c
@@ -290,14 +290,33 @@ static void do_inject(void)
 	wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
 		     (u32)mcg_status, (u32)(mcg_status >> 32));
 
-	wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
-		     (u32)i_mce.status, (u32)(i_mce.status >> 32));
+	if (boot_cpu_has(X86_FEATURE_SMCA)) {
+		if (inj_type == DFR_INT_INJ) {
+			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DESTAT(b),
+				     (u32)i_mce.status, (u32)(i_mce.status >> 32));
+
+			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_DEADDR(b),
+				     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
+		} else {
+			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_STATUS(b),
+				     (u32)i_mce.status, (u32)(i_mce.status >> 32));
+
+			wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_ADDR(b),
+				     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
+		}
+
+		wrmsr_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(b),
+			     (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
+	} else {
+		wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
+			     (u32)i_mce.status, (u32)(i_mce.status >> 32));
 
-	wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
-		     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
+		wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
+			     (u32)i_mce.addr, (u32)(i_mce.addr >> 32));
 
-	wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
-		     (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
+		wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
+			     (u32)i_mce.misc, (u32)(i_mce.misc >> 32));
+	}
 
 	toggle_hw_mce_inject(cpu, false);
 

      reply index

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-11 12:58 [PATCH 0/7] x86/ras: RAS queue Borislav Petkov
2016-05-11 12:58 ` [PATCH 1/7] x86/mce/AMD: Log Deferred Errors using SMCA MCA_DE{STAT,ADDR} registers Borislav Petkov
2016-05-12 10:26   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2016-05-11 12:58 ` [PATCH 2/7] x86/mce/AMD: Disable LogDeferredInMcaStat for SMCA systems Borislav Petkov
2016-05-12 10:27   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2016-05-11 12:58 ` [PATCH 3/7] x86/mce/AMD: Save an indentation level in prepare_threshold_block() Borislav Petkov
2016-05-12 10:27   ` [tip:ras/core] " tip-bot for Borislav Petkov
2016-05-11 12:58 ` [PATCH 4/7] x86/cpu: Add detection of AMD RAS Capabilities Borislav Petkov
2016-05-12 10:27   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2016-05-11 12:58 ` [PATCH 5/7] x86/mce: Update AMD mcheck init to use cpu_has() facilities Borislav Petkov
2016-05-12 10:28   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2016-05-11 12:58 ` [PATCH 6/7] EDAC, mce_amd: Detect SMCA using X86_FEATURE_SMCA Borislav Petkov
2016-05-12 10:28   ` [tip:ras/core] " tip-bot for Yazen Ghannam
2016-05-11 12:58 ` [PATCH 7/7] x86/RAS: Add SMCA support to AMD Error Injector Borislav Petkov
2016-05-12 10:29   ` tip-bot for Yazen Ghannam [this message]

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