* [PATCH v1 1/2] x86/platform/intel-mid: Add Intel Penwell to ID table
@ 2016-09-08 10:32 Andy Shevchenko
2016-09-08 10:32 ` [PATCH v1 2/2] x86/platform/intel-mid: Keep SRAM powered on at boot Andy Shevchenko
2016-09-08 13:19 ` [tip:x86/platform] x86/platform/intel-mid: Add Intel Penwell to ID table tip-bot for Andy Shevchenko
0 siblings, 2 replies; 4+ messages in thread
From: Andy Shevchenko @ 2016-09-08 10:32 UTC (permalink / raw)
To: ngo Molnar, linux-kernel, Thomas Gleixner, H. Peter Anvin, x86
Cc: Andy Shevchenko
The commit ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support
Penwell") enables the PWRMU driver on platforms based on Intel Penwell,
unfortunately this is not enough.
Add Intel Penwell ID to pci-mid.c driver as well. To avoid confusion in the
future add a comment to both drivers.
Fixes: ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/platform/intel-mid/pwr.c | 1 +
drivers/pci/pci-mid.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 2dfe998..146ed54 100644
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -427,6 +427,7 @@ static const struct mid_pwr_device_info mid_info = {
.set_initial_state = mid_set_initial_state,
};
+/* This table should be in sync with the one in drivers/pci/pci-mid.c */
static const struct pci_device_id mid_pwr_pci_ids[] = {
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
diff --git a/drivers/pci/pci-mid.c b/drivers/pci/pci-mid.c
index b7ea64f..55f453d 100644
--- a/drivers/pci/pci-mid.c
+++ b/drivers/pci/pci-mid.c
@@ -60,7 +60,12 @@ static struct pci_platform_pm_ops mid_pci_platform_pm = {
#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
+/*
+ * This table should be in sync with the one in
+ * arch/x86/platform/intel-mid/pwr.c.
+ */
static const struct x86_cpu_id lpss_cpu_ids[] = {
+ ICPU(INTEL_FAM6_ATOM_PENWELL),
ICPU(INTEL_FAM6_ATOM_MERRIFIELD),
{}
};
--
2.9.3
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v1 2/2] x86/platform/intel-mid: Keep SRAM powered on at boot 2016-09-08 10:32 [PATCH v1 1/2] x86/platform/intel-mid: Add Intel Penwell to ID table Andy Shevchenko @ 2016-09-08 10:32 ` Andy Shevchenko 2016-09-08 13:19 ` [tip:x86/platform] " tip-bot for Andy Shevchenko 2016-09-08 13:19 ` [tip:x86/platform] x86/platform/intel-mid: Add Intel Penwell to ID table tip-bot for Andy Shevchenko 1 sibling, 1 reply; 4+ messages in thread From: Andy Shevchenko @ 2016-09-08 10:32 UTC (permalink / raw) To: ngo Molnar, linux-kernel, Thomas Gleixner, H. Peter Anvin, x86 Cc: Andy Shevchenko On Penwell SRAM has to be powered on, otherwise it prevents booting. Fixes: ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- arch/x86/platform/intel-mid/pwr.c | 45 +++++++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c index 146ed54..5d3b45a 100644 --- a/arch/x86/platform/intel-mid/pwr.c +++ b/arch/x86/platform/intel-mid/pwr.c @@ -380,7 +380,7 @@ static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id) return 0; } -static int mid_set_initial_state(struct mid_pwr *pwr) +static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states) { unsigned int i, j; int ret; @@ -405,10 +405,10 @@ static int mid_set_initial_state(struct mid_pwr *pwr) * NOTE: The actual device mapping is provided by a platform at run * time using vendor capability of PCI configuration space. */ - mid_pwr_set_state(pwr, 0, 0xffffffff); - mid_pwr_set_state(pwr, 1, 0xffffffff); - mid_pwr_set_state(pwr, 2, 0xffffffff); - mid_pwr_set_state(pwr, 3, 0xffffffff); + mid_pwr_set_state(pwr, 0, states[0]); + mid_pwr_set_state(pwr, 1, states[1]); + mid_pwr_set_state(pwr, 2, states[2]); + mid_pwr_set_state(pwr, 3, states[3]); /* Send command to SCU */ ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG); @@ -423,14 +423,41 @@ static int mid_set_initial_state(struct mid_pwr *pwr) return 0; } -static const struct mid_pwr_device_info mid_info = { - .set_initial_state = mid_set_initial_state, +static int pnw_set_initial_state(struct mid_pwr *pwr) +{ + /* On Penwell SRAM must stay powered on */ + const u32 states[] = { + 0xf00fffff, /* PM_SSC(0) */ + 0xffffffff, /* PM_SSC(1) */ + 0xffffffff, /* PM_SSC(2) */ + 0xffffffff, /* PM_SSC(3) */ + }; + return mid_set_initial_state(pwr, states); +} + +static int tng_set_initial_state(struct mid_pwr *pwr) +{ + const u32 states[] = { + 0xffffffff, /* PM_SSC(0) */ + 0xffffffff, /* PM_SSC(1) */ + 0xffffffff, /* PM_SSC(2) */ + 0xffffffff, /* PM_SSC(3) */ + }; + return mid_set_initial_state(pwr, states); +} + +static const struct mid_pwr_device_info pnw_info = { + .set_initial_state = pnw_set_initial_state, +}; + +static const struct mid_pwr_device_info tng_info = { + .set_initial_state = tng_set_initial_state, }; /* This table should be in sync with the one in drivers/pci/pci-mid.c */ static const struct pci_device_id mid_pwr_pci_ids[] = { - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info }, - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&pnw_info }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info }, {} }; -- 2.9.3 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [tip:x86/platform] x86/platform/intel-mid: Keep SRAM powered on at boot 2016-09-08 10:32 ` [PATCH v1 2/2] x86/platform/intel-mid: Keep SRAM powered on at boot Andy Shevchenko @ 2016-09-08 13:19 ` tip-bot for Andy Shevchenko 0 siblings, 0 replies; 4+ messages in thread From: tip-bot for Andy Shevchenko @ 2016-09-08 13:19 UTC (permalink / raw) To: linux-tip-commits Cc: peterz, hpa, andriy.shevchenko, mingo, torvalds, tglx, linux-kernel Commit-ID: f43ea76cf310c3be95cb75ae1350cbe76a8f2380 Gitweb: http://git.kernel.org/tip/f43ea76cf310c3be95cb75ae1350cbe76a8f2380 Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> AuthorDate: Thu, 8 Sep 2016 13:32:32 +0300 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Thu, 8 Sep 2016 14:07:54 +0200 x86/platform/intel-mid: Keep SRAM powered on at boot On Penwell SRAM has to be powered on, otherwise it prevents booting. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Fixes: ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell") Link: http://lkml.kernel.org/r/20160908103232.137587-2-andriy.shevchenko@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/platform/intel-mid/pwr.c | 45 +++++++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c index 146ed54..5d3b45a 100644 --- a/arch/x86/platform/intel-mid/pwr.c +++ b/arch/x86/platform/intel-mid/pwr.c @@ -380,7 +380,7 @@ static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id) return 0; } -static int mid_set_initial_state(struct mid_pwr *pwr) +static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states) { unsigned int i, j; int ret; @@ -405,10 +405,10 @@ static int mid_set_initial_state(struct mid_pwr *pwr) * NOTE: The actual device mapping is provided by a platform at run * time using vendor capability of PCI configuration space. */ - mid_pwr_set_state(pwr, 0, 0xffffffff); - mid_pwr_set_state(pwr, 1, 0xffffffff); - mid_pwr_set_state(pwr, 2, 0xffffffff); - mid_pwr_set_state(pwr, 3, 0xffffffff); + mid_pwr_set_state(pwr, 0, states[0]); + mid_pwr_set_state(pwr, 1, states[1]); + mid_pwr_set_state(pwr, 2, states[2]); + mid_pwr_set_state(pwr, 3, states[3]); /* Send command to SCU */ ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG); @@ -423,14 +423,41 @@ static int mid_set_initial_state(struct mid_pwr *pwr) return 0; } -static const struct mid_pwr_device_info mid_info = { - .set_initial_state = mid_set_initial_state, +static int pnw_set_initial_state(struct mid_pwr *pwr) +{ + /* On Penwell SRAM must stay powered on */ + const u32 states[] = { + 0xf00fffff, /* PM_SSC(0) */ + 0xffffffff, /* PM_SSC(1) */ + 0xffffffff, /* PM_SSC(2) */ + 0xffffffff, /* PM_SSC(3) */ + }; + return mid_set_initial_state(pwr, states); +} + +static int tng_set_initial_state(struct mid_pwr *pwr) +{ + const u32 states[] = { + 0xffffffff, /* PM_SSC(0) */ + 0xffffffff, /* PM_SSC(1) */ + 0xffffffff, /* PM_SSC(2) */ + 0xffffffff, /* PM_SSC(3) */ + }; + return mid_set_initial_state(pwr, states); +} + +static const struct mid_pwr_device_info pnw_info = { + .set_initial_state = pnw_set_initial_state, +}; + +static const struct mid_pwr_device_info tng_info = { + .set_initial_state = tng_set_initial_state, }; /* This table should be in sync with the one in drivers/pci/pci-mid.c */ static const struct pci_device_id mid_pwr_pci_ids[] = { - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info }, - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&pnw_info }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info }, {} }; ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [tip:x86/platform] x86/platform/intel-mid: Add Intel Penwell to ID table 2016-09-08 10:32 [PATCH v1 1/2] x86/platform/intel-mid: Add Intel Penwell to ID table Andy Shevchenko 2016-09-08 10:32 ` [PATCH v1 2/2] x86/platform/intel-mid: Keep SRAM powered on at boot Andy Shevchenko @ 2016-09-08 13:19 ` tip-bot for Andy Shevchenko 1 sibling, 0 replies; 4+ messages in thread From: tip-bot for Andy Shevchenko @ 2016-09-08 13:19 UTC (permalink / raw) To: linux-tip-commits Cc: torvalds, linux-kernel, mingo, hpa, andriy.shevchenko, tglx, peterz Commit-ID: 8e522e1d321b12829960c9b26668c92f14c68d7f Gitweb: http://git.kernel.org/tip/8e522e1d321b12829960c9b26668c92f14c68d7f Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> AuthorDate: Thu, 8 Sep 2016 13:32:31 +0300 Committer: Ingo Molnar <mingo@kernel.org> CommitDate: Thu, 8 Sep 2016 14:07:53 +0200 x86/platform/intel-mid: Add Intel Penwell to ID table Commit: ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell") ... enabled the PWRMU driver on platforms based on Intel Penwell, but unfortunately this is not enough. Add Intel Penwell ID to pci-mid.c driver as well. To avoid confusion in the future add a comment to both drivers. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Fixes: ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell") Link: http://lkml.kernel.org/r/20160908103232.137587-1-andriy.shevchenko@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org> --- arch/x86/platform/intel-mid/pwr.c | 1 + drivers/pci/pci-mid.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c index 2dfe998..146ed54 100644 --- a/arch/x86/platform/intel-mid/pwr.c +++ b/arch/x86/platform/intel-mid/pwr.c @@ -427,6 +427,7 @@ static const struct mid_pwr_device_info mid_info = { .set_initial_state = mid_set_initial_state, }; +/* This table should be in sync with the one in drivers/pci/pci-mid.c */ static const struct pci_device_id mid_pwr_pci_ids[] = { { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info }, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info }, diff --git a/drivers/pci/pci-mid.c b/drivers/pci/pci-mid.c index b7ea64f..55f453d 100644 --- a/drivers/pci/pci-mid.c +++ b/drivers/pci/pci-mid.c @@ -60,7 +60,12 @@ static struct pci_platform_pm_ops mid_pci_platform_pm = { #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } +/* + * This table should be in sync with the one in + * arch/x86/platform/intel-mid/pwr.c. + */ static const struct x86_cpu_id lpss_cpu_ids[] = { + ICPU(INTEL_FAM6_ATOM_PENWELL), ICPU(INTEL_FAM6_ATOM_MERRIFIELD), {} }; ^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-09-08 13:20 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-09-08 10:32 [PATCH v1 1/2] x86/platform/intel-mid: Add Intel Penwell to ID table Andy Shevchenko 2016-09-08 10:32 ` [PATCH v1 2/2] x86/platform/intel-mid: Keep SRAM powered on at boot Andy Shevchenko 2016-09-08 13:19 ` [tip:x86/platform] " tip-bot for Andy Shevchenko 2016-09-08 13:19 ` [tip:x86/platform] x86/platform/intel-mid: Add Intel Penwell to ID table tip-bot for Andy Shevchenko
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