From: Ido Schimmel <idosch@idosch.org>
To: netdev@vger.kernel.org
Cc: davem@davemloft.net, richardcochran@gmail.com, jiri@mellanox.com,
shalomt@mellanox.com, petrm@mellanox.com, mlxsw@mellanox.com,
Ido Schimmel <idosch@mellanox.com>
Subject: [PATCH net-next 5/9] mlxsw: reg: Add Management Pulse Per Second Register
Date: Mon, 3 Jun 2019 15:12:40 +0300 [thread overview]
Message-ID: <20190603121244.3398-6-idosch@idosch.org> (raw)
In-Reply-To: <20190603121244.3398-1-idosch@idosch.org>
From: Shalom Toledo <shalomt@mellanox.com>
The MTPPS register provides the device PPS capabilities, configure the PPS
in and out modules and holds the PPS in time stamp.
Signed-off-by: Shalom Toledo <shalomt@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Reviewed-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
---
drivers/net/ethernet/mellanox/mlxsw/reg.h | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index 9ec154975cb2..d8eb9ef01646 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -8691,6 +8691,63 @@ static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
MLXSW_REG_MLCR_DURATION_MAX : 0);
}
+/* MTPPS - Management Pulse Per Second Register
+ * --------------------------------------------
+ * This register provides the device PPS capabilities, configure the PPS in and
+ * out modules and holds the PPS in time stamp.
+ */
+#define MLXSW_REG_MTPPS_ID 0x9053
+#define MLXSW_REG_MTPPS_LEN 0x3C
+
+MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
+
+/* reg_mtpps_enable
+ * Enables the PPS functionality the specific pin.
+ * A boolean variable.
+ * Access: RW
+ */
+MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
+
+enum mlxsw_reg_mtpps_pin_mode {
+ MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
+};
+
+/* reg_mtpps_pin_mode
+ * Pin mode to be used. The mode must comply with the supported modes of the
+ * requested pin.
+ * Access: RW
+ */
+MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
+
+#define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7
+
+/* reg_mtpps_pin
+ * Pin to be configured or queried out of the supported pins.
+ * Access: Index
+ */
+MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
+
+/* reg_mtpps_time_stamp
+ * When pin_mode = pps_in, the latched device time when it was triggered from
+ * the external GPIO pin.
+ * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
+ * time to generate next output signal.
+ * Time is in units of device clock.
+ * Access: RW
+ */
+MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
+
+static inline void
+mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
+{
+ MLXSW_REG_ZERO(mtpps, payload);
+ mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
+ mlxsw_reg_mtpps_pin_mode_set(payload,
+ MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
+ mlxsw_reg_mtpps_enable_set(payload, true);
+ mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
+}
+
/* MTUTC - Management UTC Register
* -------------------------------
* Configures the HW UTC counter.
@@ -10149,6 +10206,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
MLXSW_REG(mgir),
MLXSW_REG(mrsr),
MLXSW_REG(mlcr),
+ MLXSW_REG(mtpps),
MLXSW_REG(mtutc),
MLXSW_REG(mpsc),
MLXSW_REG(mcqi),
--
2.20.1
next prev parent reply other threads:[~2019-06-03 12:13 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-03 12:12 [PATCH net-next 0/9] mlxsw: Add support for physical hardware clock Ido Schimmel
2019-06-03 12:12 ` [PATCH net-next 1/9] mlxsw: cmd: Free running clock PCI BAR and offsets via query firmware Ido Schimmel
2019-06-03 12:12 ` [PATCH net-next 2/9] mlxsw: core: Add a new interface for reading the hardware free running clock Ido Schimmel
2019-06-03 12:12 ` [PATCH net-next 3/9] mlxsw: pci: Query free running clock PCI BAR and offsets Ido Schimmel
2019-06-03 12:12 ` [PATCH net-next 4/9] mlxsw: reg: Add Management UTC Register Ido Schimmel
2019-06-04 14:17 ` Richard Cochran
2019-06-05 11:30 ` Shalom Toledo
2019-06-05 17:23 ` Richard Cochran
2019-06-05 18:55 ` Shalom Toledo
2019-06-06 2:37 ` Richard Cochran
2019-06-06 9:11 ` Shalom Toledo
2019-06-06 10:12 ` Petr Machata
2019-06-03 12:12 ` Ido Schimmel [this message]
2019-06-03 12:12 ` [PATCH net-next 6/9] ptp: ptp_clock: Publish scaled_ppm_to_ppb Ido Schimmel
2019-06-04 14:21 ` Richard Cochran
2019-06-05 11:46 ` Shalom Toledo
2019-06-03 12:12 ` [PATCH net-next 7/9] mlxsw: spectrum_ptp: Add implementation for physical hardware clock operations Ido Schimmel
2019-06-04 14:28 ` Richard Cochran
2019-06-05 6:30 ` Jiri Pirko
2019-06-05 17:24 ` Richard Cochran
2019-06-05 11:44 ` Shalom Toledo
2019-06-05 17:40 ` Richard Cochran
2019-06-05 19:28 ` Shalom Toledo
2019-06-06 2:43 ` Richard Cochran
2019-06-06 8:50 ` Shalom Toledo
2019-06-06 8:57 ` Shalom Toledo
2019-06-04 17:03 ` Richard Cochran
2019-06-05 9:00 ` Petr Machata
2019-06-05 17:31 ` Richard Cochran
2019-06-06 10:21 ` Petr Machata
2019-06-03 12:12 ` [PATCH net-next 8/9] mlxsw: spectrum: PTP physical hardware clock initialization Ido Schimmel
2019-06-03 12:12 ` [PATCH net-next 9/9] selftests: ptp: Add Physical Hardware Clock test Ido Schimmel
2019-06-04 17:05 ` Richard Cochran
2019-06-07 11:15 ` Vladimir Oltean
2019-06-08 10:44 ` Vladimir Oltean
2019-06-11 13:54 ` Shalom Toledo
2019-06-03 17:35 ` [PATCH net-next 0/9] mlxsw: Add support for physical hardware clock David Miller
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