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From: Hau <hau@realtek.com>
To: Heiner Kallweit <hkallweit1@gmail.com>
Cc: "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	nic_swsd <nic_swsd@realtek.com>,
	"kuba@kernel.org" <kuba@kernel.org>,
	"grundler@chromium.org" <grundler@chromium.org>
Subject: RE: [PATCH net] r8169: fix rtl8125b dmar pte write access not set error
Date: Wed, 5 Oct 2022 05:44:22 +0000	[thread overview]
Message-ID: <25c7b354dff14ed381f91963f134a87c@realtek.com> (raw)
In-Reply-To: <840eab89-375a-bb28-9937-aeaa17922048@gmail.com>

> On 04.10.2022 10:10, Chunhao Lin wrote:
> > When close device, rx will be enabled if wol is enabeld. When open
> > device it will cause rx to dma to wrong address after pci_set_master().
> >
> Hi Hau,
> 
> I never experienced this problem. Is it an edge case that can occur under
> specific circumstances?
> 

This issue is happen on google chromebook with IOMMU enabled. Because rx is enabled when wol is enabled, 
so I think there is a chance that the packet receive in device close will be dma to invalid memory address when
device is open.

 ------Please consider the environment before printing this e-mail.

  reply	other threads:[~2022-10-05  5:44 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-04  8:10 [PATCH net] r8169: fix rtl8125b dmar pte write access not set error Chunhao Lin
2022-10-04 20:14 ` Heiner Kallweit
2022-10-05  5:44   ` Hau [this message]
2022-10-05 16:29 ` Heiner Kallweit
2022-10-06 14:23   ` Hau
2022-10-08 21:53 ` Heiner Kallweit
2022-10-09  7:45 ` Heiner Kallweit
2022-10-12  7:59   ` Hau
2022-10-12 19:33     ` Heiner Kallweit
2022-10-13  6:04       ` Hau
2022-10-15  8:18         ` Heiner Kallweit
2022-10-17 17:23           ` Hau
2022-10-17 19:38             ` Heiner Kallweit
2022-10-20 18:01               ` Hau
2022-10-24 18:02               ` Hau

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