* [PATCH v4 net-next 01/19] ionic: Add basic framework for IONIC Network device driver
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-22 21:40 ` [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands Shannon Nelson
` (17 subsequent siblings)
18 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
This patch adds a basic driver framework for the Pensando IONIC
network device. There is no functionality right now other than
the ability to load and unload.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
.../networking/device_drivers/index.rst | 1 +
.../device_drivers/pensando/ionic.rst | 64 +++++++++++++++++++
MAINTAINERS | 8 +++
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/pensando/Kconfig | 32 ++++++++++
drivers/net/ethernet/pensando/Makefile | 6 ++
drivers/net/ethernet/pensando/ionic/Makefile | 6 ++
drivers/net/ethernet/pensando/ionic/ionic.h | 25 ++++++++
.../net/ethernet/pensando/ionic/ionic_bus.h | 10 +++
.../ethernet/pensando/ionic/ionic_bus_pci.c | 58 +++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_main.c | 29 +++++++++
12 files changed, 241 insertions(+)
create mode 100644 Documentation/networking/device_drivers/pensando/ionic.rst
create mode 100644 drivers/net/ethernet/pensando/Kconfig
create mode 100644 drivers/net/ethernet/pensando/Makefile
create mode 100644 drivers/net/ethernet/pensando/ionic/Makefile
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic.h
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_bus.h
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_main.c
diff --git a/Documentation/networking/device_drivers/index.rst b/Documentation/networking/device_drivers/index.rst
index 2b7fefe72351..57fec66c5419 100644
--- a/Documentation/networking/device_drivers/index.rst
+++ b/Documentation/networking/device_drivers/index.rst
@@ -23,6 +23,7 @@ Contents:
intel/ice
google/gve
mellanox/mlx5
+ pensando/ionic
.. only:: subproject
diff --git a/Documentation/networking/device_drivers/pensando/ionic.rst b/Documentation/networking/device_drivers/pensando/ionic.rst
new file mode 100644
index 000000000000..6b05d1dad533
--- /dev/null
+++ b/Documentation/networking/device_drivers/pensando/ionic.rst
@@ -0,0 +1,64 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+==========================================================
+Linux* Driver for the Pensando(R) Ethernet adapter family
+==========================================================
+
+Pensando Linux Ethernet driver.
+Copyright(c) 2019 Pensando Systems, Inc
+
+Contents
+========
+
+- Identifying the Adapter
+- Special Features
+- Support
+
+Identifying the Adapter
+=======================
+
+To find if one or more Pensando PCI Ethernet devices are installed on the
+host, check for the PCI devices::
+
+ $ lspci -d 1dd8:
+ b5:00.0 Ethernet controller: Device 1dd8:1002
+ b6:00.0 Ethernet controller: Device 1dd8:1002
+
+If such devices are listed as above, then the ionic.ko driver should find
+and configure them for use. There should be log entries in the kernel
+messages such as these::
+
+ $ dmesg | grep ionic
+ ionic Pensando Ethernet NIC Driver, ver 0.11.0-k
+ ionic 0000:b5:00.0 enp181s0: renamed from eth0
+ ionic 0000:b5:00.0: NETDEV_CHANGENAME lif0 enp181s0
+ ionic 0000:b6:00.0 enp182s0: renamed from eth0
+ ionic 0000:b6:00.0: NETDEV_CHANGENAME lif0 enp182s0
+
+Special Features
+================
+
+Extended Debug Statistics
+-------------------------
+Basic network driver statistics are available through ethtool's
+statistics request::
+
+ $ ethtool -S enp181s0
+
+Extended debugging statistics can be enabled with the driver private
+flag "sw-dbg-stats"::
+
+ $ ethtool --show-priv-flags enp181s0
+ Private flags for enp181s0:
+ sw-dbg-stats: off
+ $ ethtool --set-priv-flags enp181s0 sw-dbg-stats on
+
+Support
+=======
+For general Linux networking support, please use the netdev mailing
+list, which is monitored by Pensando personnel::
+ netdev@vger.kernel.org
+
+For more specific support needs, please use the Pensando driver support
+email::
+ drivers@pensando.io
diff --git a/MAINTAINERS b/MAINTAINERS
index 211ea3a199bd..17634eb4ce72 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12502,6 +12502,14 @@ L: platform-driver-x86@vger.kernel.org
S: Maintained
F: drivers/platform/x86/peaq-wmi.c
+PENSANDO ETHERNET DRIVERS
+M: Shannon Nelson <snelson@pensando.io>
+M: Pensando Drivers <drivers@pensando.io>
+L: netdev@vger.kernel.org
+S: Supported
+F: Documentation/networking/device_drivers/pensando/ionic.rst
+F: drivers/net/ethernet/pensando/
+
PER-CPU MEMORY ALLOCATOR
M: Dennis Zhou <dennis@kernel.org>
M: Tejun Heo <tj@kernel.org>
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index 93a2d4deb27c..2830dc283ce6 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -168,6 +168,7 @@ config ETHOC
source "drivers/net/ethernet/packetengines/Kconfig"
source "drivers/net/ethernet/pasemi/Kconfig"
+source "drivers/net/ethernet/pensando/Kconfig"
source "drivers/net/ethernet/qlogic/Kconfig"
source "drivers/net/ethernet/qualcomm/Kconfig"
source "drivers/net/ethernet/rdc/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index fb9155cffcff..061edd22f507 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -97,3 +97,4 @@ obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/
obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/
obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/
obj-$(CONFIG_NET_VENDOR_SYNOPSYS) += synopsys/
+obj-$(CONFIG_NET_VENDOR_PENSANDO) += pensando/
diff --git a/drivers/net/ethernet/pensando/Kconfig b/drivers/net/ethernet/pensando/Kconfig
new file mode 100644
index 000000000000..5ea570be8379
--- /dev/null
+++ b/drivers/net/ethernet/pensando/Kconfig
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2019 Pensando Systems, Inc
+#
+# Pensando device configuration
+#
+
+config NET_VENDOR_PENSANDO
+ bool "Pensando devices"
+ default y
+ help
+ If you have a network (Ethernet) card belonging to this class, say Y.
+
+ Note that the answer to this question doesn't directly affect the
+ kernel: saying N will just cause the configurator to skip all
+ the questions about Pensando cards. If you say Y, you will be asked
+ for your specific card in the following questions.
+
+if NET_VENDOR_PENSANDO
+
+config IONIC
+ tristate "Pensando Ethernet IONIC Support"
+ depends on 64BIT && PCI
+ help
+ This enables the support for the Pensando family of Ethernet
+ adapters. More specific information on this driver can be
+ found in
+ <file:Documentation/networking/device_drivers/pensando/ionic.rst>.
+
+ To compile this driver as a module, choose M here. The module
+ will be called ionic.
+
+endif # NET_VENDOR_PENSANDO
diff --git a/drivers/net/ethernet/pensando/Makefile b/drivers/net/ethernet/pensando/Makefile
new file mode 100644
index 000000000000..21ce7499c122
--- /dev/null
+++ b/drivers/net/ethernet/pensando/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the Pensando network device drivers.
+#
+
+obj-$(CONFIG_IONIC) += ionic/
diff --git a/drivers/net/ethernet/pensando/ionic/Makefile b/drivers/net/ethernet/pensando/ionic/Makefile
new file mode 100644
index 000000000000..beb3faeccac1
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright(c) 2017 - 2019 Pensando Systems, Inc
+
+obj-$(CONFIG_IONIC) := ionic.o
+
+ionic-y := ionic_main.o ionic_bus_pci.o
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
new file mode 100644
index 000000000000..18c79adef06c
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#ifndef _IONIC_H_
+#define _IONIC_H_
+
+#define DRV_NAME "ionic"
+#define DRV_DESCRIPTION "Pensando Ethernet NIC Driver"
+#define DRV_VERSION "0.11.0-k"
+
+#define PCI_VENDOR_ID_PENSANDO 0x1dd8
+
+#define PCI_DEVICE_ID_PENSANDO_IONIC_ETH_PF 0x1002
+#define PCI_DEVICE_ID_PENSANDO_IONIC_ETH_VF 0x1003
+
+#define IONIC_SUBDEV_ID_NAPLES_25 0x4000
+#define IONIC_SUBDEV_ID_NAPLES_100_4 0x4001
+#define IONIC_SUBDEV_ID_NAPLES_100_8 0x4002
+
+struct ionic {
+ struct pci_dev *pdev;
+ struct device *dev;
+};
+
+#endif /* _IONIC_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus.h b/drivers/net/ethernet/pensando/ionic/ionic_bus.h
new file mode 100644
index 000000000000..94ba0afc6f38
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#ifndef _IONIC_BUS_H_
+#define _IONIC_BUS_H_
+
+int ionic_bus_register_driver(void);
+void ionic_bus_unregister_driver(void);
+
+#endif /* _IONIC_BUS_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
new file mode 100644
index 000000000000..3fc3479c85f1
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/pci.h>
+
+#include "ionic.h"
+#include "ionic_bus.h"
+
+/* Supported devices */
+static const struct pci_device_id ionic_id_table[] = {
+ { PCI_VDEVICE(PENSANDO, PCI_DEVICE_ID_PENSANDO_IONIC_ETH_PF) },
+ { PCI_VDEVICE(PENSANDO, PCI_DEVICE_ID_PENSANDO_IONIC_ETH_VF) },
+ { 0, } /* end of table */
+};
+MODULE_DEVICE_TABLE(pci, ionic_id_table);
+
+static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ struct device *dev = &pdev->dev;
+ struct ionic *ionic;
+
+ ionic = devm_kzalloc(dev, sizeof(*ionic), GFP_KERNEL);
+ if (!ionic)
+ return -ENOMEM;
+
+ ionic->pdev = pdev;
+ pci_set_drvdata(pdev, ionic);
+ ionic->dev = dev;
+
+ return 0;
+}
+
+static void ionic_remove(struct pci_dev *pdev)
+{
+ struct ionic *ionic = pci_get_drvdata(pdev);
+
+ devm_kfree(&pdev->dev, ionic);
+}
+
+static struct pci_driver ionic_driver = {
+ .name = DRV_NAME,
+ .id_table = ionic_id_table,
+ .probe = ionic_probe,
+ .remove = ionic_remove,
+};
+
+int ionic_bus_register_driver(void)
+{
+ return pci_register_driver(&ionic_driver);
+}
+
+void ionic_bus_unregister_driver(void)
+{
+ pci_unregister_driver(&ionic_driver);
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_main.c b/drivers/net/ethernet/pensando/ionic/ionic_main.c
new file mode 100644
index 000000000000..fb49c0ca5095
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_main.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/netdevice.h>
+#include <linux/utsname.h>
+
+#include "ionic.h"
+#include "ionic_bus.h"
+
+MODULE_DESCRIPTION(DRV_DESCRIPTION);
+MODULE_AUTHOR("Pensando Systems, Inc");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
+
+static int __init ionic_init_module(void)
+{
+ pr_info("%s %s, ver %s\n", DRV_NAME, DRV_DESCRIPTION, DRV_VERSION);
+ return ionic_bus_register_driver();
+}
+
+static void __exit ionic_cleanup_module(void)
+{
+ ionic_bus_unregister_driver();
+}
+
+module_init(ionic_init_module);
+module_exit(ionic_cleanup_module);
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
2019-07-22 21:40 ` [PATCH v4 net-next 01/19] ionic: Add basic framework for IONIC Network device driver Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-23 21:18 ` David Miller
2019-07-23 23:47 ` Saeed Mahameed
2019-07-22 21:40 ` [PATCH v4 net-next 03/19] ionic: Add port management commands Shannon Nelson
` (16 subsequent siblings)
18 siblings, 2 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
The ionic device has a small set of PCI registers, including a
device control and data space, and a large set of message
commands.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/Makefile | 2 +-
drivers/net/ethernet/pensando/ionic/ionic.h | 20 +
.../net/ethernet/pensando/ionic/ionic_bus.h | 1 +
.../ethernet/pensando/ionic/ionic_bus_pci.c | 140 +-
.../ethernet/pensando/ionic/ionic_debugfs.c | 67 +
.../ethernet/pensando/ionic/ionic_debugfs.h | 28 +
.../net/ethernet/pensando/ionic/ionic_dev.c | 132 +
.../net/ethernet/pensando/ionic/ionic_dev.h | 144 +
.../net/ethernet/pensando/ionic/ionic_if.h | 2552 +++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_main.c | 296 ++
.../net/ethernet/pensando/ionic/ionic_regs.h | 133 +
11 files changed, 3512 insertions(+), 3 deletions(-)
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_dev.c
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_dev.h
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_if.h
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_regs.h
diff --git a/drivers/net/ethernet/pensando/ionic/Makefile b/drivers/net/ethernet/pensando/ionic/Makefile
index beb3faeccac1..49a8e28a5c84 100644
--- a/drivers/net/ethernet/pensando/ionic/Makefile
+++ b/drivers/net/ethernet/pensando/ionic/Makefile
@@ -3,4 +3,4 @@
obj-$(CONFIG_IONIC) := ionic.o
-ionic-y := ionic_main.o ionic_bus_pci.o
+ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_debugfs.o
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
index 18c79adef06c..4fd0ae86556a 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -4,6 +4,10 @@
#ifndef _IONIC_H_
#define _IONIC_H_
+#include "ionic_if.h"
+#include "ionic_dev.h"
+#include "ionic_debugfs.h"
+
#define DRV_NAME "ionic"
#define DRV_DESCRIPTION "Pensando Ethernet NIC Driver"
#define DRV_VERSION "0.11.0-k"
@@ -17,9 +21,25 @@
#define IONIC_SUBDEV_ID_NAPLES_100_4 0x4001
#define IONIC_SUBDEV_ID_NAPLES_100_8 0x4002
+#define devcmd_timeout 10
+
struct ionic {
struct pci_dev *pdev;
struct device *dev;
+ struct ionic_dev idev;
+ struct mutex dev_cmd_lock; /* lock for dev_cmd operations */
+ struct dentry *dentry;
+ struct ionic_dev_bar bars[IONIC_BARS_MAX];
+ unsigned int num_bars;
+ struct identity ident;
};
+int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_wait);
+int ionic_set_dma_mask(struct ionic *ionic);
+int ionic_setup(struct ionic *ionic);
+
+int ionic_identify(struct ionic *ionic);
+int ionic_init(struct ionic *ionic);
+int ionic_reset(struct ionic *ionic);
+
#endif /* _IONIC_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus.h b/drivers/net/ethernet/pensando/ionic/ionic_bus.h
index 94ba0afc6f38..24b4c01ec03f 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus.h
@@ -4,6 +4,7 @@
#ifndef _IONIC_BUS_H_
#define _IONIC_BUS_H_
+const char *ionic_bus_info(struct ionic *ionic);
int ionic_bus_register_driver(void);
void ionic_bus_unregister_driver(void);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
index 3fc3479c85f1..7eb23f0e87ac 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -17,27 +17,163 @@ static const struct pci_device_id ionic_id_table[] = {
};
MODULE_DEVICE_TABLE(pci, ionic_id_table);
+const char *ionic_bus_info(struct ionic *ionic)
+{
+ return pci_name(ionic->pdev);
+}
+
+static int ionic_map_bars(struct ionic *ionic)
+{
+ struct pci_dev *pdev = ionic->pdev;
+ struct device *dev = ionic->dev;
+ struct ionic_dev_bar *bars;
+ unsigned int i, j;
+
+ bars = ionic->bars;
+ ionic->num_bars = 0;
+
+ for (i = 0, j = 0; i < IONIC_BARS_MAX; i++) {
+ if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
+ continue;
+ bars[j].len = pci_resource_len(pdev, i);
+
+ /* only map the whole bar 0 */
+ if (j > 0) {
+ bars[j].vaddr = NULL;
+ } else {
+ bars[j].vaddr = pci_iomap(pdev, i, bars[j].len);
+ if (!bars[j].vaddr) {
+ dev_err(dev,
+ "Cannot memory-map BAR %d, aborting\n",
+ i);
+ return -ENODEV;
+ }
+ }
+
+ bars[j].bus_addr = pci_resource_start(pdev, i);
+ bars[j].res_index = i;
+ ionic->num_bars++;
+ j++;
+ }
+
+ return 0;
+}
+
+static void ionic_unmap_bars(struct ionic *ionic)
+{
+ struct ionic_dev_bar *bars = ionic->bars;
+ unsigned int i;
+
+ for (i = 0; i < IONIC_BARS_MAX; i++) {
+ if (bars[i].vaddr) {
+ iounmap(bars[i].vaddr);
+ bars[i].bus_addr = 0;
+ bars[i].vaddr = NULL;
+ bars[i].len = 0;
+ }
+ }
+}
+
static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct device *dev = &pdev->dev;
struct ionic *ionic;
+ int err;
ionic = devm_kzalloc(dev, sizeof(*ionic), GFP_KERNEL);
if (!ionic)
return -ENOMEM;
ionic->pdev = pdev;
- pci_set_drvdata(pdev, ionic);
ionic->dev = dev;
+ pci_set_drvdata(pdev, ionic);
+ mutex_init(&ionic->dev_cmd_lock);
+
+ /* Query system for DMA addressing limitation for the device. */
+ err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(IONIC_ADDR_LEN));
+ if (err) {
+ dev_err(dev, "Unable to obtain 64-bit DMA for consistent allocations, aborting. err=%d\n",
+ err);
+ goto err_out_clear_drvdata;
+ }
+
+ ionic_debugfs_add_dev(ionic);
+
+ /* Setup PCI device */
+ err = pci_enable_device_mem(pdev);
+ if (err) {
+ dev_err(dev, "Cannot enable PCI device: %d, aborting\n", err);
+ goto err_out_debugfs_del_dev;
+ }
+
+ err = pci_request_regions(pdev, DRV_NAME);
+ if (err) {
+ dev_err(dev, "Cannot request PCI regions: %d, aborting\n", err);
+ goto err_out_pci_disable_device;
+ }
+
+ pci_set_master(pdev);
+
+ err = ionic_map_bars(ionic);
+ if (err)
+ goto err_out_pci_clear_master;
+
+ /* Configure the device */
+ err = ionic_setup(ionic);
+ if (err) {
+ dev_err(dev, "Cannot setup device: %d, aborting\n", err);
+ goto err_out_unmap_bars;
+ }
+
+ err = ionic_identify(ionic);
+ if (err) {
+ dev_err(dev, "Cannot identify device: %d, aborting\n", err);
+ goto err_out_teardown;
+ }
+
+ err = ionic_init(ionic);
+ if (err) {
+ dev_err(dev, "Cannot init device: %d, aborting\n", err);
+ goto err_out_teardown;
+ }
return 0;
+
+err_out_teardown:
+ ionic_dev_teardown(ionic);
+err_out_unmap_bars:
+ ionic_unmap_bars(ionic);
+ pci_release_regions(pdev);
+err_out_pci_clear_master:
+ pci_clear_master(pdev);
+err_out_pci_disable_device:
+ pci_disable_device(pdev);
+err_out_debugfs_del_dev:
+ ionic_debugfs_del_dev(ionic);
+err_out_clear_drvdata:
+ mutex_destroy(&ionic->dev_cmd_lock);
+ pci_set_drvdata(pdev, NULL);
+
+ return err;
}
static void ionic_remove(struct pci_dev *pdev)
{
struct ionic *ionic = pci_get_drvdata(pdev);
- devm_kfree(&pdev->dev, ionic);
+ if (ionic) {
+ ionic_reset(ionic);
+ ionic_dev_teardown(ionic);
+ ionic_unmap_bars(ionic);
+ pci_release_regions(pdev);
+ pci_clear_master(pdev);
+ pci_disable_sriov(pdev);
+ pci_disable_device(pdev);
+ ionic_debugfs_del_dev(ionic);
+ mutex_destroy(&ionic->dev_cmd_lock);
+
+ devm_kfree(&pdev->dev, ionic);
+ }
}
static struct pci_driver ionic_driver = {
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
new file mode 100644
index 000000000000..c33a8bfcbcd4
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#include <linux/netdevice.h>
+
+#include "ionic.h"
+#include "ionic_bus.h"
+#include "ionic_debugfs.h"
+
+#ifdef CONFIG_DEBUG_FS
+
+static struct dentry *ionic_dir;
+
+void ionic_debugfs_create(void)
+{
+ ionic_dir = debugfs_create_dir(DRV_NAME, NULL);
+}
+
+void ionic_debugfs_destroy(void)
+{
+ debugfs_remove_recursive(ionic_dir);
+}
+
+int ionic_debugfs_add_dev(struct ionic *ionic)
+{
+ struct dentry *dentry;
+
+ dentry = debugfs_create_dir(ionic_bus_info(ionic), ionic_dir);
+ if (IS_ERR_OR_NULL(dentry))
+ return PTR_ERR(dentry);
+
+ ionic->dentry = dentry;
+
+ return 0;
+}
+
+void ionic_debugfs_del_dev(struct ionic *ionic)
+{
+ debugfs_remove_recursive(ionic->dentry);
+ ionic->dentry = NULL;
+}
+
+static int identity_show(struct seq_file *seq, void *v)
+{
+ struct ionic *ionic = seq->private;
+ struct identity *ident = &ionic->ident;
+
+ seq_printf(seq, "nlifs: %d\n", ident->dev.nlifs);
+ seq_printf(seq, "nintrs: %d\n", ident->dev.nintrs);
+ seq_printf(seq, "ndbpgs_per_lif: %d\n", ident->dev.ndbpgs_per_lif);
+ seq_printf(seq, "intr_coal_mult: %d\n", ident->dev.intr_coal_mult);
+ seq_printf(seq, "intr_coal_div: %d\n", ident->dev.intr_coal_div);
+
+ seq_printf(seq, "max_ucast_filters: %d\n", ident->lif.eth.max_ucast_filters);
+ seq_printf(seq, "max_mcast_filters: %d\n", ident->lif.eth.max_mcast_filters);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(identity);
+
+int ionic_debugfs_add_ident(struct ionic *ionic)
+{
+ return debugfs_create_file("identity", 0400, ionic->dentry,
+ ionic, &identity_fops) ? 0 : -ENOTSUPP;
+}
+
+#endif
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
new file mode 100644
index 000000000000..c3958b0c15b1
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#ifndef _IONIC_DEBUGFS_H_
+#define _IONIC_DEBUGFS_H_
+
+#include <linux/debugfs.h>
+
+#ifdef CONFIG_DEBUG_FS
+
+void ionic_debugfs_create(void);
+void ionic_debugfs_destroy(void);
+int ionic_debugfs_add_dev(struct ionic *ionic);
+void ionic_debugfs_del_dev(struct ionic *ionic);
+int ionic_debugfs_add_bars(struct ionic *ionic);
+int ionic_debugfs_add_dev_cmd(struct ionic *ionic);
+int ionic_debugfs_add_ident(struct ionic *ionic);
+#else
+static inline void ionic_debugfs_create(void) { }
+static inline void ionic_debugfs_destroy(void) { }
+static inline int ionic_debugfs_add_dev(struct ionic *ionic) { return 0; }
+static inline void ionic_debugfs_del_dev(struct ionic *ionic) { }
+static inline int ionic_debugfs_add_bars(struct ionic *ionic) { return 0; }
+static inline int ionic_debugfs_add_dev_cmd(struct ionic *ionic) { return 0; }
+static inline int ionic_debugfs_add_ident(struct ionic *ionic) { return 0; }
+#endif
+
+#endif /* _IONIC_DEBUGFS_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.c b/drivers/net/ethernet/pensando/ionic/ionic_dev.c
new file mode 100644
index 000000000000..ca2ef0a1f620
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/etherdevice.h>
+#include "ionic.h"
+#include "ionic_dev.h"
+
+void ionic_init_devinfo(struct ionic_dev *idev)
+{
+ idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
+ idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
+
+ memcpy_fromio(idev->dev_info.fw_version,
+ idev->dev_info_regs->fw_version,
+ IONIC_DEVINFO_FWVERS_BUFLEN);
+
+ memcpy_fromio(idev->dev_info.serial_num,
+ idev->dev_info_regs->serial_num,
+ IONIC_DEVINFO_SERIAL_BUFLEN);
+
+ idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0;
+ idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0;
+}
+
+int ionic_dev_setup(struct ionic *ionic)
+{
+ struct ionic_dev_bar *bar = ionic->bars;
+ unsigned int num_bars = ionic->num_bars;
+ struct ionic_dev *idev = &ionic->idev;
+ struct device *dev = ionic->dev;
+ u32 sig;
+
+ /* BAR0: dev_cmd and interrupts */
+ if (num_bars < 1) {
+ dev_err(dev, "No bars found, aborting\n");
+ return -EFAULT;
+ }
+
+ if (bar->len < BAR0_SIZE) {
+ dev_err(dev, "Resource bar size %lu too small, aborting\n",
+ bar->len);
+ return -EFAULT;
+ }
+
+ idev->dev_info_regs = bar->vaddr + BAR0_DEV_INFO_REGS_OFFSET;
+ idev->dev_cmd_regs = bar->vaddr + BAR0_DEV_CMD_REGS_OFFSET;
+ idev->intr_status = bar->vaddr + BAR0_INTR_STATUS_OFFSET;
+ idev->intr_ctrl = bar->vaddr + BAR0_INTR_CTRL_OFFSET;
+
+ sig = ioread32(&idev->dev_info_regs->signature);
+ if (sig != IONIC_DEV_INFO_SIGNATURE) {
+ dev_err(dev, "Incompatible firmware signature %x", sig);
+ return -EFAULT;
+ }
+
+ ionic_init_devinfo(idev);
+
+ /* BAR1: doorbells */
+ bar++;
+ if (num_bars < 2) {
+ dev_err(dev, "Doorbell bar missing, aborting\n");
+ return -EFAULT;
+ }
+
+ idev->db_pages = bar->vaddr;
+ idev->phy_db_pages = bar->bus_addr;
+
+ return 0;
+}
+
+void ionic_dev_teardown(struct ionic *ionic)
+{
+ /* place holder */
+}
+
+/* Devcmd Interface */
+u8 ionic_dev_cmd_status(struct ionic_dev *idev)
+{
+ return ioread8(&idev->dev_cmd_regs->comp.comp.status);
+}
+
+bool ionic_dev_cmd_done(struct ionic_dev *idev)
+{
+ return ioread32(&idev->dev_cmd_regs->done) & DEV_CMD_DONE;
+}
+
+void ionic_dev_cmd_comp(struct ionic_dev *idev, union dev_cmd_comp *comp)
+{
+ memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp));
+}
+
+void ionic_dev_cmd_go(struct ionic_dev *idev, union dev_cmd *cmd)
+{
+ memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd));
+ iowrite32(0, &idev->dev_cmd_regs->done);
+ iowrite32(1, &idev->dev_cmd_regs->doorbell);
+}
+
+/* Device commands */
+void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver)
+{
+ union dev_cmd cmd = {
+ .identify.opcode = CMD_OPCODE_IDENTIFY,
+ .identify.ver = ver,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_init(struct ionic_dev *idev)
+{
+ union dev_cmd cmd = {
+ .init.opcode = CMD_OPCODE_INIT,
+ .init.type = 0,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_reset(struct ionic_dev *idev)
+{
+ union dev_cmd cmd = {
+ .reset.opcode = CMD_OPCODE_RESET,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
new file mode 100644
index 000000000000..66afab3ee396
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#ifndef _IONIC_DEV_H_
+#define _IONIC_DEV_H_
+
+#include <linux/mutex.h>
+#include <linux/workqueue.h>
+
+#include "ionic_if.h"
+#include "ionic_regs.h"
+
+struct ionic_dev_bar {
+ void __iomem *vaddr;
+ phys_addr_t bus_addr;
+ unsigned long len;
+ int res_index;
+};
+
+static inline void ionic_struct_size_checks(void)
+{
+ /* Registers */
+ BUILD_BUG_ON(sizeof(struct ionic_intr) != 32);
+
+ BUILD_BUG_ON(sizeof(struct doorbell) != 8);
+ BUILD_BUG_ON(sizeof(struct intr_ctrl) != 32);
+ BUILD_BUG_ON(sizeof(struct intr_status) != 8);
+
+ BUILD_BUG_ON(sizeof(union dev_regs) != 4096);
+ BUILD_BUG_ON(sizeof(union dev_info_regs) != 2048);
+ BUILD_BUG_ON(sizeof(union dev_cmd_regs) != 2048);
+
+ BUILD_BUG_ON(sizeof(struct lif_stats) != 1024);
+
+ BUILD_BUG_ON(sizeof(struct admin_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct admin_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct nop_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct nop_comp) != 16);
+
+ /* Device commands */
+ BUILD_BUG_ON(sizeof(struct dev_identify_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct dev_identify_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct dev_init_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct dev_init_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct dev_reset_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct dev_reset_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct dev_getattr_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct dev_getattr_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct dev_setattr_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct dev_setattr_comp) != 16);
+
+ /* Port commands */
+ BUILD_BUG_ON(sizeof(struct port_identify_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct port_identify_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct port_init_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct port_init_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct port_reset_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct port_reset_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct port_getattr_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct port_getattr_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct port_setattr_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct port_setattr_comp) != 16);
+
+ /* LIF commands */
+ BUILD_BUG_ON(sizeof(struct lif_init_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct lif_init_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct lif_reset_cmd) != 64);
+ BUILD_BUG_ON(sizeof(lif_reset_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct lif_getattr_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct lif_getattr_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct lif_setattr_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct lif_setattr_comp) != 16);
+
+ BUILD_BUG_ON(sizeof(struct q_init_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct q_init_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct q_control_cmd) != 64);
+ BUILD_BUG_ON(sizeof(q_control_comp) != 16);
+
+ BUILD_BUG_ON(sizeof(struct rx_mode_set_cmd) != 64);
+ BUILD_BUG_ON(sizeof(rx_mode_set_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct rx_filter_add_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct rx_filter_add_comp) != 16);
+ BUILD_BUG_ON(sizeof(struct rx_filter_del_cmd) != 64);
+ BUILD_BUG_ON(sizeof(rx_filter_del_comp) != 16);
+
+ /* RDMA commands */
+ BUILD_BUG_ON(sizeof(struct rdma_reset_cmd) != 64);
+ BUILD_BUG_ON(sizeof(struct rdma_queue_cmd) != 64);
+
+ /* Events */
+ BUILD_BUG_ON(sizeof(struct notifyq_cmd) != 4);
+ BUILD_BUG_ON(sizeof(union notifyq_comp) != 64);
+ BUILD_BUG_ON(sizeof(struct notifyq_event) != 64);
+ BUILD_BUG_ON(sizeof(struct link_change_event) != 64);
+ BUILD_BUG_ON(sizeof(struct reset_event) != 64);
+ BUILD_BUG_ON(sizeof(struct heartbeat_event) != 64);
+ BUILD_BUG_ON(sizeof(struct log_event) != 64);
+
+ /* I/O */
+ BUILD_BUG_ON(sizeof(struct txq_desc) != 16);
+ BUILD_BUG_ON(sizeof(struct txq_sg_desc) != 128);
+ BUILD_BUG_ON(sizeof(struct txq_comp) != 16);
+
+ BUILD_BUG_ON(sizeof(struct rxq_desc) != 16);
+ BUILD_BUG_ON(sizeof(struct rxq_sg_desc) != 128);
+ BUILD_BUG_ON(sizeof(struct rxq_comp) != 16);
+}
+
+struct ionic_devinfo {
+ u8 asic_type;
+ u8 asic_rev;
+ char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1];
+ char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1];
+};
+
+struct ionic_dev {
+ union dev_info_regs __iomem *dev_info_regs;
+ union dev_cmd_regs __iomem *dev_cmd_regs;
+
+ u64 __iomem *db_pages;
+ dma_addr_t phy_db_pages;
+
+ struct ionic_intr __iomem *intr_ctrl;
+ u64 __iomem *intr_status;
+
+ struct ionic_devinfo dev_info;
+};
+
+struct ionic;
+
+void ionic_init_devinfo(struct ionic_dev *idev);
+int ionic_dev_setup(struct ionic *ionic);
+void ionic_dev_teardown(struct ionic *ionic);
+
+void ionic_dev_cmd_go(struct ionic_dev *idev, union dev_cmd *cmd);
+u8 ionic_dev_cmd_status(struct ionic_dev *idev);
+bool ionic_dev_cmd_done(struct ionic_dev *idev);
+void ionic_dev_cmd_comp(struct ionic_dev *idev, union dev_cmd_comp *comp);
+
+void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver);
+void ionic_dev_cmd_init(struct ionic_dev *idev);
+void ionic_dev_cmd_reset(struct ionic_dev *idev);
+
+#endif /* _IONIC_DEV_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_if.h b/drivers/net/ethernet/pensando/ionic/ionic_if.h
new file mode 100644
index 000000000000..0afbe842c81e
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_if.h
@@ -0,0 +1,2552 @@
+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */
+/* Copyright (c) 2017-2019 Pensando Systems, Inc. All rights reserved. */
+
+#ifndef _IONIC_IF_H_
+#define _IONIC_IF_H_
+
+#pragma pack(push, 1)
+
+#define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */
+#define IONIC_DEV_INFO_VERSION 1
+#define IONIC_IFNAMSIZ 16
+
+/**
+ * Commands
+ */
+enum cmd_opcode {
+ CMD_OPCODE_NOP = 0,
+
+ /* Device commands */
+ CMD_OPCODE_IDENTIFY = 1,
+ CMD_OPCODE_INIT = 2,
+ CMD_OPCODE_RESET = 3,
+ CMD_OPCODE_GETATTR = 4,
+ CMD_OPCODE_SETATTR = 5,
+
+ /* Port commands */
+ CMD_OPCODE_PORT_IDENTIFY = 10,
+ CMD_OPCODE_PORT_INIT = 11,
+ CMD_OPCODE_PORT_RESET = 12,
+ CMD_OPCODE_PORT_GETATTR = 13,
+ CMD_OPCODE_PORT_SETATTR = 14,
+
+ /* LIF commands */
+ CMD_OPCODE_LIF_IDENTIFY = 20,
+ CMD_OPCODE_LIF_INIT = 21,
+ CMD_OPCODE_LIF_RESET = 22,
+ CMD_OPCODE_LIF_GETATTR = 23,
+ CMD_OPCODE_LIF_SETATTR = 24,
+
+ CMD_OPCODE_RX_MODE_SET = 30,
+ CMD_OPCODE_RX_FILTER_ADD = 31,
+ CMD_OPCODE_RX_FILTER_DEL = 32,
+
+ /* Queue commands */
+ CMD_OPCODE_Q_INIT = 40,
+ CMD_OPCODE_Q_CONTROL = 41,
+
+ /* RDMA commands */
+ CMD_OPCODE_RDMA_RESET_LIF = 50,
+ CMD_OPCODE_RDMA_CREATE_EQ = 51,
+ CMD_OPCODE_RDMA_CREATE_CQ = 52,
+ CMD_OPCODE_RDMA_CREATE_ADMINQ = 53,
+
+ /* QoS commands */
+ CMD_OPCODE_QOS_CLASS_IDENTIFY = 240,
+ CMD_OPCODE_QOS_CLASS_INIT = 241,
+ CMD_OPCODE_QOS_CLASS_RESET = 242,
+
+ /* Firmware commands */
+ CMD_OPCODE_FW_DOWNLOAD = 254,
+ CMD_OPCODE_FW_CONTROL = 255,
+};
+
+/**
+ * Command Return codes
+ */
+enum status_code {
+ IONIC_RC_SUCCESS = 0, /* Success */
+ IONIC_RC_EVERSION = 1, /* Incorrect version for request */
+ IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */
+ IONIC_RC_EIO = 3, /* I/O error */
+ IONIC_RC_EPERM = 4, /* Permission denied */
+ IONIC_RC_EQID = 5, /* Bad qid */
+ IONIC_RC_EQTYPE = 6, /* Bad qtype */
+ IONIC_RC_ENOENT = 7, /* No such element */
+ IONIC_RC_EINTR = 8, /* operation interrupted */
+ IONIC_RC_EAGAIN = 9, /* Try again */
+ IONIC_RC_ENOMEM = 10, /* Out of memory */
+ IONIC_RC_EFAULT = 11, /* Bad address */
+ IONIC_RC_EBUSY = 12, /* Device or resource busy */
+ IONIC_RC_EEXIST = 13, /* object already exists */
+ IONIC_RC_EINVAL = 14, /* Invalid argument */
+ IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */
+ IONIC_RC_ERANGE = 16, /* Parameter out of range */
+ IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */
+ IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */
+ IONIC_RC_ERROR = 29, /* Generic error */
+
+ IONIC_RC_ERDMA = 30, /* Generic RDMA error */
+};
+
+enum notifyq_opcode {
+ EVENT_OPCODE_LINK_CHANGE = 1,
+ EVENT_OPCODE_RESET = 2,
+ EVENT_OPCODE_HEARTBEAT = 3,
+ EVENT_OPCODE_LOG = 4,
+};
+
+/**
+ * struct cmd - General admin command format
+ * @opcode: Opcode for the command
+ * @lif_index: LIF index
+ * @cmd_data: Opcode-specific command bytes
+ */
+struct admin_cmd {
+ u8 opcode;
+ u8 rsvd;
+ __le16 lif_index;
+ u8 cmd_data[60];
+};
+
+/**
+ * struct admin_comp - General admin command completion format
+ * @status: The status of the command (enum status_code)
+ * @comp_index: The index in the descriptor ring for which this
+ * is the completion.
+ * @cmd_data: Command-specific bytes.
+ * @color: Color bit. (Always 0 for commands issued to the
+ * Device Cmd Registers.)
+ */
+struct admin_comp {
+ u8 status;
+ u8 rsvd;
+ __le16 comp_index;
+ u8 cmd_data[11];
+ u8 color;
+#define IONIC_COMP_COLOR_MASK 0x80
+};
+
+static inline u8 color_match(u8 color, u8 done_color)
+{
+ return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
+}
+
+/**
+ * struct nop_cmd - NOP command
+ * @opcode: opcode
+ */
+struct nop_cmd {
+ u8 opcode;
+ u8 rsvd[63];
+};
+
+/**
+ * struct nop_comp - NOP command completion
+ * @status: The status of the command (enum status_code)
+ */
+struct nop_comp {
+ u8 status;
+ u8 rsvd[15];
+};
+
+/**
+ * struct dev_init_cmd - Device init command
+ * @opcode: opcode
+ * @type: device type
+ */
+struct dev_init_cmd {
+ u8 opcode;
+ u8 type;
+ u8 rsvd[62];
+};
+
+/**
+ * struct init_comp - Device init command completion
+ * @status: The status of the command (enum status_code)
+ */
+struct dev_init_comp {
+ u8 status;
+ u8 rsvd[15];
+};
+
+/**
+ * struct dev_reset_cmd - Device reset command
+ * @opcode: opcode
+ */
+struct dev_reset_cmd {
+ u8 opcode;
+ u8 rsvd[63];
+};
+
+/**
+ * struct reset_comp - Reset command completion
+ * @status: The status of the command (enum status_code)
+ */
+struct dev_reset_comp {
+ u8 status;
+ u8 rsvd[15];
+};
+
+#define IONIC_IDENTITY_VERSION_1 1
+
+/**
+ * struct dev_identify_cmd - Driver/device identify command
+ * @opcode: opcode
+ * @ver: Highest version of identify supported by driver
+ */
+struct dev_identify_cmd {
+ u8 opcode;
+ u8 ver;
+ u8 rsvd[62];
+};
+
+/**
+ * struct dev_identify_comp - Driver/device identify command completion
+ * @status: The status of the command (enum status_code)
+ * @ver: Version of identify returned by device
+ */
+struct dev_identify_comp {
+ u8 status;
+ u8 ver;
+ u8 rsvd[14];
+};
+
+enum os_type {
+ IONIC_OS_TYPE_LINUX = 1,
+ IONIC_OS_TYPE_WIN = 2,
+ IONIC_OS_TYPE_DPDK = 3,
+ IONIC_OS_TYPE_FREEBSD = 4,
+ IONIC_OS_TYPE_IPXE = 5,
+ IONIC_OS_TYPE_ESXI = 6,
+};
+
+/**
+ * union drv_identity - driver identity information
+ * @os_type: OS type (see enum os_type)
+ * @os_dist: OS distribution, numeric format
+ * @os_dist_str: OS distribution, string format
+ * @kernel_ver: Kernel version, numeric format
+ * @kernel_ver_str: Kernel version, string format
+ * @driver_ver_str: Driver version, string format
+ */
+union drv_identity {
+ struct {
+ __le32 os_type;
+ __le32 os_dist;
+ char os_dist_str[128];
+ __le32 kernel_ver;
+ char kernel_ver_str[32];
+ char driver_ver_str[32];
+ };
+ __le32 words[512];
+};
+
+/**
+ * union dev_identity - device identity information
+ * @version: Version of device identify
+ * @type: Identify type (0 for now)
+ * @nports: Number of ports provisioned
+ * @nlifs: Number of LIFs provisioned
+ * @nintrs: Number of interrupts provisioned
+ * @ndbpgs_per_lif: Number of doorbell pages per LIF
+ * @intr_coal_mult: Interrupt coalescing multiplication factor.
+ * Scale user-supplied interrupt coalescing
+ * value in usecs to device units using:
+ * device units = usecs * mult / div
+ * @intr_coal_div: Interrupt coalescing division factor.
+ * Scale user-supplied interrupt coalescing
+ * value in usecs to device units using:
+ * device units = usecs * mult / div
+ *
+ */
+union dev_identity {
+ struct {
+ u8 version;
+ u8 type;
+ u8 rsvd[2];
+ u8 nports;
+ u8 rsvd2[3];
+ __le32 nlifs;
+ __le32 nintrs;
+ __le32 ndbpgs_per_lif;
+ __le32 intr_coal_mult;
+ __le32 intr_coal_div;
+ };
+ __le32 words[512];
+};
+
+enum lif_type {
+ IONIC_LIF_TYPE_CLASSIC = 0,
+ IONIC_LIF_TYPE_MACVLAN = 1,
+ IONIC_LIF_TYPE_NETQUEUE = 2,
+};
+
+/**
+ * struct lif_identify_cmd - lif identify command
+ * @opcode: opcode
+ * @type: lif type (enum lif_type)
+ * @ver: version of identify returned by device
+ */
+struct lif_identify_cmd {
+ u8 opcode;
+ u8 type;
+ u8 ver;
+ u8 rsvd[61];
+};
+
+/**
+ * struct lif_identify_comp - lif identify command completion
+ * @status: status of the command (enum status_code)
+ * @ver: version of identify returned by device
+ */
+struct lif_identify_comp {
+ u8 status;
+ u8 ver;
+ u8 rsvd2[14];
+};
+
+enum lif_capability {
+ IONIC_LIF_CAP_ETH = BIT(0),
+ IONIC_LIF_CAP_RDMA = BIT(1),
+};
+
+/**
+ * Logical Queue Types
+ */
+enum logical_qtype {
+ IONIC_QTYPE_ADMINQ = 0,
+ IONIC_QTYPE_NOTIFYQ = 1,
+ IONIC_QTYPE_RXQ = 2,
+ IONIC_QTYPE_TXQ = 3,
+ IONIC_QTYPE_EQ = 4,
+ IONIC_QTYPE_MAX = 16,
+};
+
+/**
+ * struct lif_logical_qtype - Descriptor of logical to hardware queue type.
+ * @qtype: Hardware Queue Type.
+ * @qid_count: Number of Queue IDs of the logical type.
+ * @qid_base: Minimum Queue ID of the logical type.
+ */
+struct lif_logical_qtype {
+ u8 qtype;
+ u8 rsvd[3];
+ __le32 qid_count;
+ __le32 qid_base;
+};
+
+enum lif_state {
+ IONIC_LIF_DISABLE = 0,
+ IONIC_LIF_ENABLE = 1,
+ IONIC_LIF_HANG_RESET = 2,
+};
+
+/**
+ * LIF configuration
+ * @state: lif state (enum lif_state)
+ * @name: lif name
+ * @mtu: mtu
+ * @mac: station mac address
+ * @features: features (enum eth_hw_features)
+ * @queue_count: queue counts per queue-type
+ */
+union lif_config {
+ struct {
+ u8 state;
+ u8 rsvd[3];
+ char name[IONIC_IFNAMSIZ];
+ __le32 mtu;
+ u8 mac[6];
+ u8 rsvd2[2];
+ __le64 features;
+ __le32 queue_count[IONIC_QTYPE_MAX];
+ };
+ __le32 words[64];
+};
+
+/**
+ * struct lif_identity - lif identity information (type-specific)
+ *
+ * @capabilities LIF capabilities
+ *
+ * Ethernet:
+ * @version: Ethernet identify structure version.
+ * @features: Ethernet features supported on this lif type.
+ * @max_ucast_filters: Number of perfect unicast addresses supported.
+ * @max_mcast_filters: Number of perfect multicast addresses supported.
+ * @min_frame_size: Minimum size of frames to be sent
+ * @max_frame_size: Maximim size of frames to be sent
+ * @config: LIF config struct with features, mtu, mac, q counts
+ *
+ * RDMA:
+ * @version: RDMA version of opcodes and queue descriptors.
+ * @qp_opcodes: Number of rdma queue pair opcodes supported.
+ * @admin_opcodes: Number of rdma admin opcodes supported.
+ * @npts_per_lif: Page table size per lif
+ * @nmrs_per_lif: Number of memory regions per lif
+ * @nahs_per_lif: Number of address handles per lif
+ * @max_stride: Max work request stride.
+ * @cl_stride: Cache line stride.
+ * @pte_stride: Page table entry stride.
+ * @rrq_stride: Remote RQ work request stride.
+ * @rsq_stride: Remote SQ work request stride.
+ * @dcqcn_profiles: Number of DCQCN profiles
+ * @aq_qtype: RDMA Admin Qtype.
+ * @sq_qtype: RDMA Send Qtype.
+ * @rq_qtype: RDMA Receive Qtype.
+ * @cq_qtype: RDMA Completion Qtype.
+ * @eq_qtype: RDMA Event Qtype.
+ */
+union lif_identity {
+ struct {
+ __le64 capabilities;
+
+ struct {
+ u8 version;
+ u8 rsvd[3];
+ __le32 max_ucast_filters;
+ __le32 max_mcast_filters;
+ __le16 rss_ind_tbl_sz;
+ __le32 min_frame_size;
+ __le32 max_frame_size;
+ u8 rsvd2[106];
+ union lif_config config;
+ } eth;
+
+ struct {
+ u8 version;
+ u8 qp_opcodes;
+ u8 admin_opcodes;
+ u8 rsvd;
+ __le32 npts_per_lif;
+ __le32 nmrs_per_lif;
+ __le32 nahs_per_lif;
+ u8 max_stride;
+ u8 cl_stride;
+ u8 pte_stride;
+ u8 rrq_stride;
+ u8 rsq_stride;
+ u8 dcqcn_profiles;
+ u8 rsvd_dimensions[10];
+ struct lif_logical_qtype aq_qtype;
+ struct lif_logical_qtype sq_qtype;
+ struct lif_logical_qtype rq_qtype;
+ struct lif_logical_qtype cq_qtype;
+ struct lif_logical_qtype eq_qtype;
+ } rdma;
+ };
+ __le32 words[512];
+};
+
+/**
+ * struct lif_init_cmd - LIF init command
+ * @opcode: opcode
+ * @type: LIF type (enum lif_type)
+ * @index: LIF index
+ * @info_pa: destination address for lif info (struct lif_info)
+ */
+struct lif_init_cmd {
+ u8 opcode;
+ u8 type;
+ __le16 index;
+ __le32 rsvd;
+ __le64 info_pa;
+ u8 rsvd2[48];
+};
+
+/**
+ * struct lif_init_comp - LIF init command completion
+ * @status: The status of the command (enum status_code)
+ */
+struct lif_init_comp {
+ u8 status;
+ u8 rsvd;
+ __le16 hw_index;
+ u8 rsvd2[12];
+};
+
+/**
+ * struct q_init_cmd - Queue init command
+ * @opcode: opcode
+ * @type: Logical queue type
+ * @ver: Queue version (defines opcode/descriptor scope)
+ * @lif_index: LIF index
+ * @index: (lif, qtype) relative admin queue index
+ * @intr_index: Interrupt control register index
+ * @pid: Process ID
+ * @flags:
+ * IRQ: Interrupt requested on completion
+ * ENA: Enable the queue. If ENA=0 the queue is initialized
+ * but remains disabled, to be later enabled with the
+ * Queue Enable command. If ENA=1, then queue is
+ * initialized and then enabled.
+ * SG: Enable Scatter-Gather on the queue.
+ * in number of descs. The actual ring size is
+ * (1 << ring_size). For example, to
+ * select a ring size of 64 descriptors write
+ * ring_size = 6. The minimum ring_size value is 2
+ * for a ring size of 4 descriptors. The maximum
+ * ring_size value is 16 for a ring size of 64k
+ * descriptors. Values of ring_size <2 and >16 are
+ * reserved.
+ * EQ: Enable the Event Queue
+ * @cos: Class of service for this queue.
+ * @ring_size: Queue ring size, encoded as a log2(size)
+ * @ring_base: Queue ring base address
+ * @cq_ring_base: Completion queue ring base address
+ * @sg_ring_base: Scatter/Gather ring base address
+ * @eq_index: Event queue index
+ */
+struct q_init_cmd {
+ u8 opcode;
+ u8 rsvd;
+ __le16 lif_index;
+ u8 type;
+ u8 ver;
+ u8 rsvd1[2];
+ __le32 index;
+ __le16 pid;
+ __le16 intr_index;
+ __le16 flags;
+#define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */
+#define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */
+#define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */
+#define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */
+#define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */
+ u8 cos;
+ u8 ring_size;
+ __le64 ring_base;
+ __le64 cq_ring_base;
+ __le64 sg_ring_base;
+ __le32 eq_index;
+ u8 rsvd2[16];
+};
+
+/**
+ * struct q_init_comp - Queue init command completion
+ * @status: The status of the command (enum status_code)
+ * @ver: Queue version (defines opcode/descriptor scope)
+ * @comp_index: The index in the descriptor ring for which this
+ * is the completion.
+ * @hw_index: Hardware Queue ID
+ * @hw_type: Hardware Queue type
+ * @color: Color
+ */
+struct q_init_comp {
+ u8 status;
+ u8 ver;
+ __le16 comp_index;
+ __le32 hw_index;
+ u8 hw_type;
+ u8 rsvd2[6];
+ u8 color;
+};
+
+/* the device's internal addressing uses up to 52 bits */
+#define IONIC_ADDR_LEN 52
+#define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
+
+enum txq_desc_opcode {
+ IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
+ IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
+ IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
+ IONIC_TXQ_DESC_OPCODE_TSO = 3,
+};
+
+/**
+ * struct txq_desc - Ethernet Tx queue descriptor format
+ * @opcode: Tx operation, see TXQ_DESC_OPCODE_*:
+ *
+ * IONIC_TXQ_DESC_OPCODE_CSUM_NONE:
+ *
+ * Non-offload send. No segmentation,
+ * fragmentation or checksum calc/insertion is
+ * performed by device; packet is prepared
+ * to send by software stack and requires
+ * no further manipulation from device.
+ *
+ * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:
+ *
+ * Offload 16-bit L4 checksum
+ * calculation/insertion. The device will
+ * calculate the L4 checksum value and
+ * insert the result in the packet's L4
+ * header checksum field. The L4 checksum
+ * is calculated starting at @csum_start bytes
+ * into the packet to the end of the packet.
+ * The checksum insertion position is given
+ * in @csum_offset. This feature is only
+ * applicable to protocols such as TCP, UDP
+ * and ICMP where a standard (i.e. the
+ * 'IP-style' checksum) one's complement
+ * 16-bit checksum is used, using an IP
+ * pseudo-header to seed the calculation.
+ * Software will preload the L4 checksum
+ * field with the IP pseudo-header checksum.
+ *
+ * For tunnel encapsulation, @csum_start and
+ * @csum_offset refer to the inner L4
+ * header. Supported tunnels encapsulations
+ * are: IPIP, GRE, and UDP. If the @encap
+ * is clear, no further processing by the
+ * device is required; software will
+ * calculate the outer header checksums. If
+ * the @encap is set, the device will
+ * offload the outer header checksums using
+ * LCO (local checksum offload) (see
+ * Documentation/networking/checksum-
+ * offloads.txt for more info).
+ *
+ * IONIC_TXQ_DESC_OPCODE_CSUM_HW:
+ *
+ * Offload 16-bit checksum computation to hardware.
+ * If @csum_l3 is set then the packet's L3 checksum is
+ * updated. Similarly, if @csum_l4 is set the the L4
+ * checksum is updated. If @encap is set then encap header
+ * checksums are also updated.
+ *
+ * IONIC_TXQ_DESC_OPCODE_TSO:
+ *
+ * Device preforms TCP segmentation offload
+ * (TSO). @hdr_len is the number of bytes
+ * to the end of TCP header (the offset to
+ * the TCP payload). @mss is the desired
+ * MSS, the TCP payload length for each
+ * segment. The device will calculate/
+ * insert IP (IPv4 only) and TCP checksums
+ * for each segment. In the first data
+ * buffer containing the header template,
+ * the driver will set IPv4 checksum to 0
+ * and preload TCP checksum with the IP
+ * pseudo header calculated with IP length = 0.
+ *
+ * Supported tunnel encapsulations are IPIP,
+ * layer-3 GRE, and UDP. @hdr_len includes
+ * both outer and inner headers. The driver
+ * will set IPv4 checksum to zero and
+ * preload TCP checksum with IP pseudo
+ * header on the inner header.
+ *
+ * TCP ECN offload is supported. The device
+ * will set CWR flag in the first segment if
+ * CWR is set in the template header, and
+ * clear CWR in remaining segments.
+ * @flags:
+ * vlan:
+ * Insert an L2 VLAN header using @vlan_tci.
+ * encap:
+ * Calculate encap header checksum.
+ * csum_l3:
+ * Compute L3 header checksum.
+ * csum_l4:
+ * Compute L4 header checksum.
+ * tso_sot:
+ * TSO start
+ * tso_eot:
+ * TSO end
+ * @num_sg_elems: Number of scatter-gather elements in SG
+ * descriptor
+ * @addr: First data buffer's DMA address.
+ * (Subsequent data buffers are on txq_sg_desc).
+ * @len: First data buffer's length, in bytes
+ * @vlan_tci: VLAN tag to insert in the packet (if requested
+ * by @V-bit). Includes .1p and .1q tags
+ * @hdr_len: Length of packet headers, including
+ * encapsulating outer header, if applicable.
+ * Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and
+ * TXQ_DESC_OPCODE_TSO. Should be set to zero for
+ * all other modes. For
+ * TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length
+ * of headers up to inner-most L4 header. For
+ * TXQ_DESC_OPCODE_TSO, @hdr_len is up to
+ * inner-most L4 payload, so inclusive of
+ * inner-most L4 header.
+ * @mss: Desired MSS value for TSO. Only applicable for
+ * TXQ_DESC_OPCODE_TSO.
+ * @csum_start: Offset into inner-most L3 header of checksum
+ * @csum_offset: Offset into inner-most L4 header of checksum
+ */
+
+#define IONIC_TXQ_DESC_OPCODE_MASK 0xf
+#define IONIC_TXQ_DESC_OPCODE_SHIFT 4
+#define IONIC_TXQ_DESC_FLAGS_MASK 0xf
+#define IONIC_TXQ_DESC_FLAGS_SHIFT 0
+#define IONIC_TXQ_DESC_NSGE_MASK 0xf
+#define IONIC_TXQ_DESC_NSGE_SHIFT 8
+#define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
+#define IONIC_TXQ_DESC_ADDR_SHIFT 12
+
+/* common flags */
+#define IONIC_TXQ_DESC_FLAG_VLAN 0x1
+#define IONIC_TXQ_DESC_FLAG_ENCAP 0x2
+
+/* flags for csum_hw opcode */
+#define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4
+#define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8
+
+/* flags for tso opcode */
+#define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4
+#define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8
+
+struct txq_desc {
+ __le64 cmd;
+ __le16 len;
+ union {
+ __le16 vlan_tci;
+ __le16 hword0;
+ };
+ union {
+ __le16 csum_start;
+ __le16 hdr_len;
+ __le16 hword1;
+ };
+ union {
+ __le16 csum_offset;
+ __le16 mss;
+ __le16 hword2;
+ };
+};
+
+static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
+ u8 nsge, u64 addr)
+{
+ u64 cmd;
+
+ cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT;
+ cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT;
+ cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;
+ cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;
+
+ return cmd;
+};
+
+static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
+ u8 *nsge, u64 *addr)
+{
+ *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK;
+ *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK;
+ *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;
+ *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;
+};
+
+#define IONIC_TX_MAX_SG_ELEMS 8
+#define IONIC_RX_MAX_SG_ELEMS 8
+
+/**
+ * struct txq_sg_desc - Transmit scatter-gather (SG) list
+ * @addr: DMA address of SG element data buffer
+ * @len: Length of SG element data buffer, in bytes
+ */
+struct txq_sg_desc {
+ struct txq_sg_elem {
+ __le64 addr;
+ __le16 len;
+ __le16 rsvd[3];
+ } elems[IONIC_TX_MAX_SG_ELEMS];
+};
+
+/**
+ * struct txq_comp - Ethernet transmit queue completion descriptor
+ * @status: The status of the command (enum status_code)
+ * @comp_index: The index in the descriptor ring for which this
+ * is the completion.
+ * @color: Color bit.
+ */
+struct txq_comp {
+ u8 status;
+ u8 rsvd;
+ __le16 comp_index;
+ u8 rsvd2[11];
+ u8 color;
+};
+
+enum rxq_desc_opcode {
+ RXQ_DESC_OPCODE_SIMPLE = 0,
+ RXQ_DESC_OPCODE_SG = 1,
+};
+
+/**
+ * struct rxq_desc - Ethernet Rx queue descriptor format
+ * @opcode: Rx operation, see RXQ_DESC_OPCODE_*:
+ *
+ * RXQ_DESC_OPCODE_SIMPLE:
+ *
+ * Receive full packet into data buffer
+ * starting at @addr. Results of
+ * receive, including actual bytes received,
+ * are recorded in Rx completion descriptor.
+ *
+ * @len: Data buffer's length, in bytes.
+ * @addr: Data buffer's DMA address
+ */
+struct rxq_desc {
+ u8 opcode;
+ u8 rsvd[5];
+ __le16 len;
+ __le64 addr;
+};
+
+/**
+ * struct rxq_sg_desc - Receive scatter-gather (SG) list
+ * @addr: DMA address of SG element data buffer
+ * @len: Length of SG element data buffer, in bytes
+ */
+struct rxq_sg_desc {
+ struct rxq_sg_elem {
+ __le64 addr;
+ __le16 len;
+ __le16 rsvd[3];
+ } elems[IONIC_RX_MAX_SG_ELEMS];
+};
+
+/**
+ * struct rxq_comp - Ethernet receive queue completion descriptor
+ * @status: The status of the command (enum status_code)
+ * @num_sg_elems: Number of SG elements used by this descriptor
+ * @comp_index: The index in the descriptor ring for which this
+ * is the completion.
+ * @rss_hash: 32-bit RSS hash
+ * @csum: 16-bit sum of the packet's L2 payload.
+ * If the packet's L2 payload is odd length, an extra
+ * zero-value byte is included in the @csum calculation but
+ * not included in @len.
+ * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is
+ * set. Includes .1p and .1q tags.
+ * @len: Received packet length, in bytes. Excludes FCS.
+ * @csum_calc L2 payload checksum is computed or not
+ * @csum_tcp_ok: The TCP checksum calculated by the device
+ * matched the checksum in the receive packet's
+ * TCP header
+ * @csum_tcp_bad: The TCP checksum calculated by the device did
+ * not match the checksum in the receive packet's
+ * TCP header.
+ * @csum_udp_ok: The UDP checksum calculated by the device
+ * matched the checksum in the receive packet's
+ * UDP header
+ * @csum_udp_bad: The UDP checksum calculated by the device did
+ * not match the checksum in the receive packet's
+ * UDP header.
+ * @csum_ip_ok: The IPv4 checksum calculated by the device
+ * matched the checksum in the receive packet's
+ * first IPv4 header. If the receive packet
+ * contains both a tunnel IPv4 header and a
+ * transport IPv4 header, the device validates the
+ * checksum for the both IPv4 headers.
+ * @csum_ip_bad: The IPv4 checksum calculated by the device did
+ * not match the checksum in the receive packet's
+ * first IPv4 header. If the receive packet
+ * contains both a tunnel IPv4 header and a
+ * transport IPv4 header, the device validates the
+ * checksum for both IP headers.
+ * @VLAN: VLAN header was stripped and placed in @vlan_tci.
+ * @pkt_type: Packet type
+ * @color: Color bit.
+ */
+struct rxq_comp {
+ u8 status;
+ u8 num_sg_elems;
+ __le16 comp_index;
+ __le32 rss_hash;
+ __le16 csum;
+ __le16 vlan_tci;
+ __le16 len;
+ u8 csum_flags;
+#define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01
+#define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02
+#define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04
+#define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08
+#define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10
+#define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20
+#define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40
+#define IONIC_RXQ_COMP_CSUM_F_CALC 0x80
+ u8 pkt_type_color;
+#define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x0f
+};
+
+enum pkt_type {
+ PKT_TYPE_NON_IP = 0x000,
+ PKT_TYPE_IPV4 = 0x001,
+ PKT_TYPE_IPV4_TCP = 0x003,
+ PKT_TYPE_IPV4_UDP = 0x005,
+ PKT_TYPE_IPV6 = 0x008,
+ PKT_TYPE_IPV6_TCP = 0x018,
+ PKT_TYPE_IPV6_UDP = 0x028,
+};
+
+enum eth_hw_features {
+ ETH_HW_VLAN_TX_TAG = BIT(0),
+ ETH_HW_VLAN_RX_STRIP = BIT(1),
+ ETH_HW_VLAN_RX_FILTER = BIT(2),
+ ETH_HW_RX_HASH = BIT(3),
+ ETH_HW_RX_CSUM = BIT(4),
+ ETH_HW_TX_SG = BIT(5),
+ ETH_HW_RX_SG = BIT(6),
+ ETH_HW_TX_CSUM = BIT(7),
+ ETH_HW_TSO = BIT(8),
+ ETH_HW_TSO_IPV6 = BIT(9),
+ ETH_HW_TSO_ECN = BIT(10),
+ ETH_HW_TSO_GRE = BIT(11),
+ ETH_HW_TSO_GRE_CSUM = BIT(12),
+ ETH_HW_TSO_IPXIP4 = BIT(13),
+ ETH_HW_TSO_IPXIP6 = BIT(14),
+ ETH_HW_TSO_UDP = BIT(15),
+ ETH_HW_TSO_UDP_CSUM = BIT(16),
+};
+
+/**
+ * struct q_control_cmd - Queue control command
+ * @opcode: opcode
+ * @type: Queue type
+ * @lif_index: LIF index
+ * @index: Queue index
+ * @oper: Operation (enum q_control_oper)
+ */
+struct q_control_cmd {
+ u8 opcode;
+ u8 type;
+ __le16 lif_index;
+ __le32 index;
+ u8 oper;
+ u8 rsvd[55];
+};
+
+typedef struct admin_comp q_control_comp;
+
+enum q_control_oper {
+ IONIC_Q_DISABLE = 0,
+ IONIC_Q_ENABLE = 1,
+ IONIC_Q_HANG_RESET = 2,
+};
+
+/**
+ * Physical connection type
+ */
+enum phy_type {
+ PHY_TYPE_NONE = 0,
+ PHY_TYPE_COPPER = 1,
+ PHY_TYPE_FIBER = 2,
+};
+
+/**
+ * Transceiver status
+ */
+enum xcvr_state {
+ XCVR_STATE_REMOVED = 0,
+ XCVR_STATE_INSERTED = 1,
+ XCVR_STATE_PENDING = 2,
+ XCVR_STATE_SPROM_READ = 3,
+ XCVR_STATE_SPROM_READ_ERR = 4,
+};
+
+/**
+ * Supported link modes
+ */
+enum xcvr_pid {
+ XCVR_PID_UNKNOWN = 0,
+
+ /* CU */
+ XCVR_PID_QSFP_100G_CR4 = 1,
+ XCVR_PID_QSFP_40GBASE_CR4 = 2,
+ XCVR_PID_SFP_25GBASE_CR_S = 3,
+ XCVR_PID_SFP_25GBASE_CR_L = 4,
+ XCVR_PID_SFP_25GBASE_CR_N = 5,
+
+ /* Fiber */
+ XCVR_PID_QSFP_100G_AOC = 50,
+ XCVR_PID_QSFP_100G_ACC = 51,
+ XCVR_PID_QSFP_100G_SR4 = 52,
+ XCVR_PID_QSFP_100G_LR4 = 53,
+ XCVR_PID_QSFP_100G_ER4 = 54,
+ XCVR_PID_QSFP_40GBASE_ER4 = 55,
+ XCVR_PID_QSFP_40GBASE_SR4 = 56,
+ XCVR_PID_QSFP_40GBASE_LR4 = 57,
+ XCVR_PID_QSFP_40GBASE_AOC = 58,
+ XCVR_PID_SFP_25GBASE_SR = 59,
+ XCVR_PID_SFP_25GBASE_LR = 60,
+ XCVR_PID_SFP_25GBASE_ER = 61,
+ XCVR_PID_SFP_25GBASE_AOC = 62,
+ XCVR_PID_SFP_10GBASE_SR = 63,
+ XCVR_PID_SFP_10GBASE_LR = 64,
+ XCVR_PID_SFP_10GBASE_LRM = 65,
+ XCVR_PID_SFP_10GBASE_ER = 66,
+ XCVR_PID_SFP_10GBASE_AOC = 67,
+ XCVR_PID_SFP_10GBASE_CU = 68,
+};
+
+/**
+ * Port types
+ */
+enum PortType {
+ PORT_TYPE_NONE = 0, /* port type not configured */
+ PORT_TYPE_ETH = 1, /* port carries ethernet traffic (inband) */
+ PORT_TYPE_MGMT = 2, /* port carries mgmt traffic (out-of-band) */
+};
+
+/**
+ * Port config state
+ */
+enum PortAdminState {
+ PORT_ADMIN_STATE_NONE = 0, /* port admin state not configured */
+ PORT_ADMIN_STATE_DOWN = 1, /* port is admin disabled */
+ PORT_ADMIN_STATE_UP = 2, /* port is admin enabled */
+};
+
+/**
+ * Port operational status
+ */
+enum port_oper_status {
+ PORT_OPER_STATUS_NONE = 0, /* port is disabled */
+ PORT_OPER_STATUS_UP = 1, /* port is linked up */
+ PORT_OPER_STATUS_DOWN = 2, /* port link status is down */
+};
+
+/**
+ * Ethernet Forward error correction (fec) modes
+ */
+enum port_fec_type {
+ PORT_FEC_TYPE_NONE = 0, /* Disabled */
+ PORT_FEC_TYPE_FC = 1, /* FireCode */
+ PORT_FEC_TYPE_RS = 2, /* ReedSolomon */
+};
+
+/**
+ * Ethernet pause (flow control) modes
+ */
+enum port_pause_type {
+ PORT_PAUSE_TYPE_NONE = 0, /* Disable Pause */
+ PORT_PAUSE_TYPE_LINK = 1, /* Link level pause */
+ PORT_PAUSE_TYPE_PFC = 2, /* Priority-Flow control */
+};
+
+/**
+ * Loopback modes
+ */
+enum port_loopback_mode {
+ PORT_LOOPBACK_MODE_NONE = 0, /* Disable loopback */
+ PORT_LOOPBACK_MODE_MAC = 1, /* MAC loopback */
+ PORT_LOOPBACK_MODE_PHY = 2, /* PHY/Serdes loopback */
+};
+
+/**
+ * Transceiver Status information
+ * @state: Transceiver status (enum xcvr_state)
+ * @phy: Physical connection type (enum phy_type)
+ * @pid: Transceiver link mode (enum pid)
+ * @sprom: Transceiver sprom contents
+ */
+struct xcvr_status {
+ u8 state;
+ u8 phy;
+ __le16 pid;
+ u8 sprom[256];
+};
+
+/**
+ * Port configuration
+ * @speed: port speed (in Mbps)
+ * @mtu: mtu
+ * @state: port admin state (enum port_admin_state)
+ * @an_enable: autoneg enable
+ * @fec_type: fec type (enum port_fec_type)
+ * @pause_type: pause type (enum port_pause_type)
+ * @loopback_mode: loopback mode (enum port_loopback_mode)
+ */
+union port_config {
+ struct {
+#define IONIC_SPEED_100G 100000 /* 100G in Mbps */
+#define IONIC_SPEED_50G 50000 /* 50G in Mbps */
+#define IONIC_SPEED_40G 40000 /* 40G in Mbps */
+#define IONIC_SPEED_25G 25000 /* 25G in Mbps */
+#define IONIC_SPEED_10G 10000 /* 10G in Mbps */
+#define IONIC_SPEED_1G 1000 /* 1G in Mbps */
+ __le32 speed;
+ __le32 mtu;
+ u8 state;
+ u8 an_enable;
+ u8 fec_type;
+#define IONIC_PAUSE_TYPE_MASK 0x0f
+#define IONIC_PAUSE_FLAGS_MASK 0xf0
+#define IONIC_PAUSE_F_TX 0x10
+#define IONIC_PAUSE_F_RX 0x20
+ u8 pause_type;
+ u8 loopback_mode;
+ };
+ __le32 words[64];
+};
+
+/**
+ * Port Status information
+ * @status: link status (enum port_oper_status)
+ * @id: port id
+ * @speed: link speed (in Mbps)
+ * @xcvr: tranceiver status
+ */
+struct port_status {
+ __le32 id;
+ __le32 speed;
+ u8 status;
+ u8 rsvd[51];
+ struct xcvr_status xcvr;
+};
+
+/**
+ * struct port_identify_cmd - Port identify command
+ * @opcode: opcode
+ * @index: port index
+ * @ver: Highest version of identify supported by driver
+ */
+struct port_identify_cmd {
+ u8 opcode;
+ u8 index;
+ u8 ver;
+ u8 rsvd[61];
+};
+
+/**
+ * struct port_identify_comp - Port identify command completion
+ * @status: The status of the command (enum status_code)
+ * @ver: Version of identify returned by device
+ */
+struct port_identify_comp {
+ u8 status;
+ u8 ver;
+ u8 rsvd[14];
+};
+
+/**
+ * struct port_init_cmd - Port initialization command
+ * @opcode: opcode
+ * @index: port index
+ * @info_pa: destination address for port info (struct port_info)
+ */
+struct port_init_cmd {
+ u8 opcode;
+ u8 index;
+ u8 rsvd[6];
+ __le64 info_pa;
+ u8 rsvd2[48];
+};
+
+/**
+ * struct port_init_comp - Port initialization command completion
+ * @status: The status of the command (enum status_code)
+ */
+struct port_init_comp {
+ u8 status;
+ u8 rsvd[15];
+};
+
+/**
+ * struct port_reset_cmd - Port reset command
+ * @opcode: opcode
+ * @index: port index
+ */
+struct port_reset_cmd {
+ u8 opcode;
+ u8 index;
+ u8 rsvd[62];
+};
+
+/**
+ * struct port_reset_comp - Port reset command completion
+ * @status: The status of the command (enum status_code)
+ */
+struct port_reset_comp {
+ u8 status;
+ u8 rsvd[15];
+};
+
+/**
+ * enum ionic_port_attr - List of device attributes
+ */
+enum ionic_port_attr {
+ IONIC_PORT_ATTR_STATE = 0,
+ IONIC_PORT_ATTR_SPEED = 1,
+ IONIC_PORT_ATTR_MTU = 2,
+ IONIC_PORT_ATTR_AUTONEG = 3,
+ IONIC_PORT_ATTR_FEC = 4,
+ IONIC_PORT_ATTR_PAUSE = 5,
+ IONIC_PORT_ATTR_LOOPBACK = 6,
+};
+
+/**
+ * struct port_setattr_cmd - Set port attributes on the NIC
+ * @opcode: Opcode
+ * @index: port index
+ * @attr: Attribute type (enum ionic_port_attr)
+ */
+struct port_setattr_cmd {
+ u8 opcode;
+ u8 index;
+ u8 attr;
+ u8 rsvd;
+ union {
+ u8 state;
+ __le32 speed;
+ __le32 mtu;
+ u8 an_enable;
+ u8 fec_type;
+ u8 pause_type;
+ u8 loopback_mode;
+ u8 rsvd2[60];
+ };
+};
+
+/**
+ * struct port_setattr_comp - Port set attr command completion
+ * @status: The status of the command (enum status_code)
+ * @color: Color bit
+ */
+struct port_setattr_comp {
+ u8 status;
+ u8 rsvd[14];
+ u8 color;
+};
+
+/**
+ * struct port_getattr_cmd - Get port attributes from the NIC
+ * @opcode: Opcode
+ * @index: port index
+ * @attr: Attribute type (enum ionic_port_attr)
+ */
+struct port_getattr_cmd {
+ u8 opcode;
+ u8 index;
+ u8 attr;
+ u8 rsvd[61];
+};
+
+/**
+ * struct port_getattr_comp - Port get attr command completion
+ * @status: The status of the command (enum status_code)
+ * @color: Color bit
+ */
+struct port_getattr_comp {
+ u8 status;
+ u8 rsvd[3];
+ union {
+ u8 state;
+ __le32 speed;
+ __le32 mtu;
+ u8 an_enable;
+ u8 fec_type;
+ u8 pause_type;
+ u8 loopback_mode;
+ u8 rsvd2[11];
+ };
+ u8 color;
+};
+
+/**
+ * struct lif_status - Lif status register
+ * @eid: most recent NotifyQ event id
+ * @port_num: port the lif is connected to
+ * @link_status: port status (enum port_oper_status)
+ * @link_speed: speed of link in Mbps
+ * @link_down_count: number of times link status changes
+ */
+struct lif_status {
+ __le64 eid;
+ u8 port_num;
+ u8 rsvd;
+ __le16 link_status;
+ __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */
+ __le16 link_down_count;
+ u8 rsvd2[46];
+};
+
+/**
+ * struct lif_reset_cmd - LIF reset command
+ * @opcode: opcode
+ * @index: LIF index
+ */
+struct lif_reset_cmd {
+ u8 opcode;
+ u8 rsvd;
+ __le16 index;
+ __le32 rsvd2[15];
+};
+
+typedef struct admin_comp lif_reset_comp;
+
+enum dev_state {
+ IONIC_DEV_DISABLE = 0,
+ IONIC_DEV_ENABLE = 1,
+ IONIC_DEV_HANG_RESET = 2,
+};
+
+/**
+ * enum dev_attr - List of device attributes
+ */
+enum dev_attr {
+ IONIC_DEV_ATTR_STATE = 0,
+ IONIC_DEV_ATTR_NAME = 1,
+ IONIC_DEV_ATTR_FEATURES = 2,
+};
+
+/**
+ * struct dev_setattr_cmd - Set Device attributes on the NIC
+ * @opcode: Opcode
+ * @attr: Attribute type (enum dev_attr)
+ * @state: Device state (enum dev_state)
+ * @name: The bus info, e.g. PCI slot-device-function, 0 terminated
+ * @features: Device features
+ */
+struct dev_setattr_cmd {
+ u8 opcode;
+ u8 attr;
+ __le16 rsvd;
+ union {
+ u8 state;
+ char name[IONIC_IFNAMSIZ];
+ __le64 features;
+ u8 rsvd2[60];
+ };
+};
+
+/**
+ * struct dev_setattr_comp - Device set attr command completion
+ * @status: The status of the command (enum status_code)
+ * @features: Device features
+ * @color: Color bit
+ */
+struct dev_setattr_comp {
+ u8 status;
+ u8 rsvd[3];
+ union {
+ __le64 features;
+ u8 rsvd2[11];
+ };
+ u8 color;
+};
+
+/**
+ * struct dev_getattr_cmd - Get Device attributes from the NIC
+ * @opcode: opcode
+ * @attr: Attribute type (enum dev_attr)
+ */
+struct dev_getattr_cmd {
+ u8 opcode;
+ u8 attr;
+ u8 rsvd[62];
+};
+
+/**
+ * struct dev_setattr_comp - Device set attr command completion
+ * @status: The status of the command (enum status_code)
+ * @features: Device features
+ * @color: Color bit
+ */
+struct dev_getattr_comp {
+ u8 status;
+ u8 rsvd[3];
+ union {
+ __le64 features;
+ u8 rsvd2[11];
+ };
+ u8 color;
+};
+
+/**
+ * RSS parameters
+ */
+#define IONIC_RSS_HASH_KEY_SIZE 40
+
+enum rss_hash_types {
+ IONIC_RSS_TYPE_IPV4 = BIT(0),
+ IONIC_RSS_TYPE_IPV4_TCP = BIT(1),
+ IONIC_RSS_TYPE_IPV4_UDP = BIT(2),
+ IONIC_RSS_TYPE_IPV6 = BIT(3),
+ IONIC_RSS_TYPE_IPV6_TCP = BIT(4),
+ IONIC_RSS_TYPE_IPV6_UDP = BIT(5),
+};
+
+/**
+ * enum lif_attr - List of LIF attributes
+ */
+enum lif_attr {
+ IONIC_LIF_ATTR_STATE = 0,
+ IONIC_LIF_ATTR_NAME = 1,
+ IONIC_LIF_ATTR_MTU = 2,
+ IONIC_LIF_ATTR_MAC = 3,
+ IONIC_LIF_ATTR_FEATURES = 4,
+ IONIC_LIF_ATTR_RSS = 5,
+};
+
+/**
+ * struct lif_setattr_cmd - Set LIF attributes on the NIC
+ * @opcode: Opcode
+ * @type: Attribute type (enum lif_attr)
+ * @index: LIF index
+ * @state: lif state (enum lif_state)
+ * @name: The netdev name string, 0 terminated
+ * @mtu: Mtu
+ * @mac: Station mac
+ * @features: Features (enum eth_hw_features)
+ * @rss: RSS properties
+ * @types: The hash types to enable (see rss_hash_types).
+ * @key: The hash secret key.
+ * @addr: Address for the indirection table shared memory.
+ */
+struct lif_setattr_cmd {
+ u8 opcode;
+ u8 attr;
+ __le16 index;
+ union {
+ u8 state;
+ char name[IONIC_IFNAMSIZ];
+ __le32 mtu;
+ u8 mac[6];
+ __le64 features;
+ struct {
+ __le16 types;
+ u8 key[IONIC_RSS_HASH_KEY_SIZE];
+ u8 rsvd[6];
+ __le64 addr;
+ } rss;
+ u8 rsvd[60];
+ };
+};
+
+/**
+ * struct lif_setattr_comp - LIF set attr command completion
+ * @status: The status of the command (enum status_code)
+ * @comp_index: The index in the descriptor ring for which this
+ * is the completion.
+ * @features: features (enum eth_hw_features)
+ * @color: Color bit
+ */
+struct lif_setattr_comp {
+ u8 status;
+ u8 rsvd;
+ __le16 comp_index;
+ union {
+ __le64 features;
+ u8 rsvd2[11];
+ };
+ u8 color;
+};
+
+/**
+ * struct lif_getattr_cmd - Get LIF attributes from the NIC
+ * @opcode: Opcode
+ * @attr: Attribute type (enum lif_attr)
+ * @index: LIF index
+ */
+struct lif_getattr_cmd {
+ u8 opcode;
+ u8 attr;
+ __le16 index;
+ u8 rsvd[60];
+};
+
+/**
+ * struct lif_getattr_comp - LIF get attr command completion
+ * @status: The status of the command (enum status_code)
+ * @comp_index: The index in the descriptor ring for which this
+ * is the completion.
+ * @state: lif state (enum lif_state)
+ * @name: The netdev name string, 0 terminated
+ * @mtu: Mtu
+ * @mac: Station mac
+ * @features: Features (enum eth_hw_features)
+ * @color: Color bit
+ */
+struct lif_getattr_comp {
+ u8 status;
+ u8 rsvd;
+ __le16 comp_index;
+ union {
+ u8 state;
+ __le32 mtu;
+ u8 mac[6];
+ __le64 features;
+ u8 rsvd2[11];
+ };
+ u8 color;
+};
+
+enum rx_mode {
+ RX_MODE_F_UNICAST = BIT(0),
+ RX_MODE_F_MULTICAST = BIT(1),
+ RX_MODE_F_BROADCAST = BIT(2),
+ RX_MODE_F_PROMISC = BIT(3),
+ RX_MODE_F_ALLMULTI = BIT(4),
+};
+
+/**
+ * struct rx_mode_set_cmd - Set LIF's Rx mode command
+ * @opcode: opcode
+ * @lif_index: LIF index
+ * @rx_mode: Rx mode flags:
+ * RX_MODE_F_UNICAST: Accept known unicast packets.
+ * RX_MODE_F_MULTICAST: Accept known multicast packets.
+ * RX_MODE_F_BROADCAST: Accept broadcast packets.
+ * RX_MODE_F_PROMISC: Accept any packets.
+ * RX_MODE_F_ALLMULTI: Accept any multicast packets.
+ */
+struct rx_mode_set_cmd {
+ u8 opcode;
+ u8 rsvd;
+ __le16 lif_index;
+ __le16 rx_mode;
+ __le16 rsvd2[29];
+};
+
+typedef struct admin_comp rx_mode_set_comp;
+
+enum rx_filter_match_type {
+ RX_FILTER_MATCH_VLAN = 0,
+ RX_FILTER_MATCH_MAC,
+ RX_FILTER_MATCH_MAC_VLAN,
+};
+
+/**
+ * struct rx_filter_add_cmd - Add LIF Rx filter command
+ * @opcode: opcode
+ * @qtype: Queue type
+ * @lif_index: LIF index
+ * @qid: Queue ID
+ * @match: Rx filter match type. (See RX_FILTER_MATCH_xxx)
+ * @vlan: VLAN ID
+ * @addr: MAC address (network-byte order)
+ */
+struct rx_filter_add_cmd {
+ u8 opcode;
+ u8 qtype;
+ __le16 lif_index;
+ __le32 qid;
+ __le16 match;
+ union {
+ struct {
+ __le16 vlan;
+ } vlan;
+ struct {
+ u8 addr[6];
+ } mac;
+ struct {
+ __le16 vlan;
+ u8 addr[6];
+ } mac_vlan;
+ u8 rsvd[54];
+ };
+};
+
+/**
+ * struct rx_filter_add_comp - Add LIF Rx filter command completion
+ * @status: The status of the command (enum status_code)
+ * @comp_index: The index in the descriptor ring for which this
+ * is the completion.
+ * @filter_id: Filter ID
+ * @color: Color bit.
+ */
+struct rx_filter_add_comp {
+ u8 status;
+ u8 rsvd;
+ __le16 comp_index;
+ __le32 filter_id;
+ u8 rsvd2[7];
+ u8 color;
+};
+
+/**
+ * struct rx_filter_del_cmd - Delete LIF Rx filter command
+ * @opcode: opcode
+ * @lif_index: LIF index
+ * @filter_id: Filter ID
+ */
+struct rx_filter_del_cmd {
+ u8 opcode;
+ u8 rsvd;
+ __le16 lif_index;
+ __le32 filter_id;
+ u8 rsvd2[56];
+};
+
+typedef struct admin_comp rx_filter_del_comp;
+
+/**
+ * struct qos_identify_cmd - QoS identify command
+ * @opcode: opcode
+ * @ver: Highest version of identify supported by driver
+ *
+ */
+struct qos_identify_cmd {
+ u8 opcode;
+ u8 ver;
+ u8 rsvd[62];
+};
+
+/**
+ * struct qos_identify_comp - QoS identify command completion
+ * @status: The status of the command (enum status_code)
+ * @ver: Version of identify returned by device
+ */
+struct qos_identify_comp {
+ u8 status;
+ u8 ver;
+ u8 rsvd[14];
+};
+
+#define IONIC_QOS_CLASS_MAX 7
+#define IONIC_QOS_CLASS_NAME_SZ 32
+#define IONIC_QOS_DSCP_MAX_VALUES 64
+
+/**
+ * enum qos_class
+ */
+enum qos_class {
+ QOS_CLASS_DEFAULT = 0,
+ QOS_CLASS_USER_DEFINED_1 = 1,
+ QOS_CLASS_USER_DEFINED_2 = 2,
+ QOS_CLASS_USER_DEFINED_3 = 3,
+ QOS_CLASS_USER_DEFINED_4 = 4,
+ QOS_CLASS_USER_DEFINED_5 = 5,
+ QOS_CLASS_USER_DEFINED_6 = 6,
+};
+
+/**
+ * enum qos_class_type - Traffic classification criteria
+ */
+enum qos_class_type {
+ QOS_CLASS_TYPE_NONE = 0,
+ QOS_CLASS_TYPE_PCP = 1, /* Dot1Q pcp */
+ QOS_CLASS_TYPE_DSCP = 2, /* IP dscp */
+};
+
+/**
+ * enum qos_sched_type - Qos class scheduling type
+ */
+enum qos_sched_type {
+ QOS_SCHED_TYPE_STRICT = 0, /* Strict priority */
+ QOS_SCHED_TYPE_DWRR = 1, /* Deficit weighted round-robin */
+};
+
+/**
+ * union qos_config - Qos configuration structure
+ * @flags: Configuration flags
+ * IONIC_QOS_CONFIG_F_ENABLE enable
+ * IONIC_QOS_CONFIG_F_DROP drop/nodrop
+ * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite
+ * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite
+ * @sched_type: Qos class scheduling type (enum qos_sched_type)
+ * @class_type: Qos class type (enum qos_class_type)
+ * @pause_type: Qos pause type (enum qos_pause_type)
+ * @name: Qos class name
+ * @mtu: MTU of the class
+ * @pfc_dot1q_pcp: Pcp value for pause frames (valid iff F_NODROP)
+ * @dwrr_weight: Qos class scheduling weight
+ * @strict_rlmt: Rate limit for strict priority scheduling
+ * @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP)
+ * @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP)
+ * @dot1q_pcp: Dot1q pcp value
+ * @ndscp: Number of valid dscp values in the ip_dscp field
+ * @ip_dscp: IP dscp values
+ */
+union qos_config {
+ struct {
+#define IONIC_QOS_CONFIG_F_ENABLE BIT(0)
+#define IONIC_QOS_CONFIG_F_DROP BIT(1)
+#define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2)
+#define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3)
+ u8 flags;
+ u8 sched_type;
+ u8 class_type;
+ u8 pause_type;
+ char name[IONIC_QOS_CLASS_NAME_SZ];
+ __le32 mtu;
+ /* flow control */
+ u8 pfc_cos;
+ /* scheduler */
+ union {
+ u8 dwrr_weight;
+ __le64 strict_rlmt;
+ };
+ /* marking */
+ union {
+ u8 rw_dot1q_pcp;
+ u8 rw_ip_dscp;
+ };
+ /* classification */
+ union {
+ u8 dot1q_pcp;
+ struct {
+ u8 ndscp;
+ u8 ip_dscp[IONIC_QOS_DSCP_MAX_VALUES];
+ };
+ };
+ };
+ __le32 words[64];
+};
+
+/**
+ * union qos_identity - QoS identity structure
+ * @version: Version of the identify structure
+ * @type: QoS system type
+ * @nclasses: Number of usable QoS classes
+ * @config: Current configuration of classes
+ */
+union qos_identity {
+ struct {
+ u8 version;
+ u8 type;
+ u8 rsvd[62];
+ union qos_config config[IONIC_QOS_CLASS_MAX];
+ };
+ __le32 words[512];
+};
+
+/**
+ * struct qos_init_cmd - QoS config init command
+ * @opcode: Opcode
+ * @group: Qos class id
+ * @info_pa: destination address for qos info
+ */
+struct qos_init_cmd {
+ u8 opcode;
+ u8 group;
+ u8 rsvd[6];
+ __le64 info_pa;
+ u8 rsvd1[48];
+};
+
+typedef struct admin_comp qos_init_comp;
+
+/**
+ * struct qos_reset_cmd - Qos config reset command
+ * @opcode: Opcode
+ */
+struct qos_reset_cmd {
+ u8 opcode;
+ u8 group;
+ u8 rsvd[62];
+};
+
+typedef struct admin_comp qos_reset_comp;
+
+/**
+ * struct fw_download_cmd - Firmware download command
+ * @opcode: opcode
+ * @addr: dma address of the firmware buffer
+ * @offset: offset of the firmware buffer within the full image
+ * @length: number of valid bytes in the firmware buffer
+ */
+struct fw_download_cmd {
+ u8 opcode;
+ u8 rsvd[3];
+ __le32 offset;
+ __le64 addr;
+ __le32 length;
+};
+
+typedef struct admin_comp fw_download_comp;
+
+enum fw_control_oper {
+ IONIC_FW_RESET = 0, /* Reset firmware */
+ IONIC_FW_INSTALL = 1, /* Install firmware */
+ IONIC_FW_ACTIVATE = 2, /* Activate firmware */
+};
+
+/**
+ * struct fw_control_cmd - Firmware control command
+ * @opcode: opcode
+ * @oper: firmware control operation (enum fw_control_oper)
+ * @slot: slot to activate
+ */
+struct fw_control_cmd {
+ u8 opcode;
+ u8 rsvd[3];
+ u8 oper;
+ u8 slot;
+ u8 rsvd1[58];
+};
+
+/**
+ * struct fw_control_comp - Firmware control copletion
+ * @opcode: opcode
+ * @slot: slot where the firmware was installed
+ */
+struct fw_control_comp {
+ u8 status;
+ u8 rsvd;
+ __le16 comp_index;
+ u8 slot;
+ u8 rsvd1[10];
+ u8 color;
+};
+
+/******************************************************************
+ ******************* RDMA Commands ********************************
+ ******************************************************************/
+
+/**
+ * struct rdma_reset_cmd - Reset RDMA LIF cmd
+ * @opcode: opcode
+ * @lif_index: lif index
+ *
+ * There is no rdma specific dev command completion struct. Completion uses
+ * the common struct admin_comp. Only the status is indicated. Nonzero status
+ * means the LIF does not support rdma.
+ **/
+struct rdma_reset_cmd {
+ u8 opcode;
+ u8 rsvd;
+ __le16 lif_index;
+ u8 rsvd2[60];
+};
+
+/**
+ * struct rdma_queue_cmd - Create RDMA Queue command
+ * @opcode: opcode, 52, 53
+ * @lif_index lif index
+ * @qid_ver: (qid | (rdma version << 24))
+ * @cid: intr, eq_id, or cq_id
+ * @dbid: doorbell page id
+ * @depth_log2: log base two of queue depth
+ * @stride_log2: log base two of queue stride
+ * @dma_addr: address of the queue memory
+ * @xxx_table_index: temporary, but should not need pgtbl for contig. queues.
+ *
+ * The same command struct is used to create an rdma event queue, completion
+ * queue, or rdma admin queue. The cid is an interrupt number for an event
+ * queue, an event queue id for a completion queue, or a completion queue id
+ * for an rdma admin queue.
+ *
+ * The queue created via a dev command must be contiguous in dma space.
+ *
+ * The dev commands are intended only to be used during driver initialization,
+ * to create queues supporting the rdma admin queue. Other queues, and other
+ * types of rdma resources like memory regions, will be created and registered
+ * via the rdma admin queue, and will support a more complete interface
+ * providing scatter gather lists for larger, scattered queue buffers and
+ * memory registration.
+ *
+ * There is no rdma specific dev command completion struct. Completion uses
+ * the common struct admin_comp. Only the status is indicated.
+ **/
+struct rdma_queue_cmd {
+ u8 opcode;
+ u8 rsvd;
+ __le16 lif_index;
+ __le32 qid_ver;
+ __le32 cid;
+ __le16 dbid;
+ u8 depth_log2;
+ u8 stride_log2;
+ __le64 dma_addr;
+ u8 rsvd2[36];
+ __le32 xxx_table_index;
+};
+
+/******************************************************************
+ ******************* Notify Events ********************************
+ ******************************************************************/
+
+/**
+ * struct notifyq_event
+ * @eid: event number
+ * @ecode: event code
+ * @data: unspecified data about the event
+ *
+ * This is the generic event report struct from which the other
+ * actual events will be formed.
+ */
+struct notifyq_event {
+ __le64 eid;
+ __le16 ecode;
+ u8 data[54];
+};
+
+/**
+ * struct link_change_event
+ * @eid: event number
+ * @ecode: event code = EVENT_OPCODE_LINK_CHANGE
+ * @link_status: link up or down, with error bits (enum port_status)
+ * @link_speed: speed of the network link
+ *
+ * Sent when the network link state changes between UP and DOWN
+ */
+struct link_change_event {
+ __le64 eid;
+ __le16 ecode;
+ __le16 link_status;
+ __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */
+ u8 rsvd[48];
+};
+
+/**
+ * struct reset_event
+ * @eid: event number
+ * @ecode: event code = EVENT_OPCODE_RESET
+ * @reset_code: reset type
+ * @state: 0=pending, 1=complete, 2=error
+ *
+ * Sent when the NIC or some subsystem is going to be or
+ * has been reset.
+ */
+struct reset_event {
+ __le64 eid;
+ __le16 ecode;
+ u8 reset_code;
+ u8 state;
+ u8 rsvd[52];
+};
+
+/**
+ * struct heartbeat_event
+ * @eid: event number
+ * @ecode: event code = EVENT_OPCODE_HEARTBEAT
+ *
+ * Sent periodically by the NIC to indicate continued health
+ */
+struct heartbeat_event {
+ __le64 eid;
+ __le16 ecode;
+ u8 rsvd[54];
+};
+
+/**
+ * struct log_event
+ * @eid: event number
+ * @ecode: event code = EVENT_OPCODE_LOG
+ * @data: log data
+ *
+ * Sent to notify the driver of an internal error.
+ */
+struct log_event {
+ __le64 eid;
+ __le16 ecode;
+ u8 data[54];
+};
+
+/**
+ * struct port_stats
+ */
+struct port_stats {
+ __le64 frames_rx_ok;
+ __le64 frames_rx_all;
+ __le64 frames_rx_bad_fcs;
+ __le64 frames_rx_bad_all;
+ __le64 octets_rx_ok;
+ __le64 octets_rx_all;
+ __le64 frames_rx_unicast;
+ __le64 frames_rx_multicast;
+ __le64 frames_rx_broadcast;
+ __le64 frames_rx_pause;
+ __le64 frames_rx_bad_length;
+ __le64 frames_rx_undersized;
+ __le64 frames_rx_oversized;
+ __le64 frames_rx_fragments;
+ __le64 frames_rx_jabber;
+ __le64 frames_rx_pripause;
+ __le64 frames_rx_stomped_crc;
+ __le64 frames_rx_too_long;
+ __le64 frames_rx_vlan_good;
+ __le64 frames_rx_dropped;
+ __le64 frames_rx_less_than_64b;
+ __le64 frames_rx_64b;
+ __le64 frames_rx_65b_127b;
+ __le64 frames_rx_128b_255b;
+ __le64 frames_rx_256b_511b;
+ __le64 frames_rx_512b_1023b;
+ __le64 frames_rx_1024b_1518b;
+ __le64 frames_rx_1519b_2047b;
+ __le64 frames_rx_2048b_4095b;
+ __le64 frames_rx_4096b_8191b;
+ __le64 frames_rx_8192b_9215b;
+ __le64 frames_rx_other;
+ __le64 frames_tx_ok;
+ __le64 frames_tx_all;
+ __le64 frames_tx_bad;
+ __le64 octets_tx_ok;
+ __le64 octets_tx_total;
+ __le64 frames_tx_unicast;
+ __le64 frames_tx_multicast;
+ __le64 frames_tx_broadcast;
+ __le64 frames_tx_pause;
+ __le64 frames_tx_pripause;
+ __le64 frames_tx_vlan;
+ __le64 frames_tx_less_than_64b;
+ __le64 frames_tx_64b;
+ __le64 frames_tx_65b_127b;
+ __le64 frames_tx_128b_255b;
+ __le64 frames_tx_256b_511b;
+ __le64 frames_tx_512b_1023b;
+ __le64 frames_tx_1024b_1518b;
+ __le64 frames_tx_1519b_2047b;
+ __le64 frames_tx_2048b_4095b;
+ __le64 frames_tx_4096b_8191b;
+ __le64 frames_tx_8192b_9215b;
+ __le64 frames_tx_other;
+ __le64 frames_tx_pri_0;
+ __le64 frames_tx_pri_1;
+ __le64 frames_tx_pri_2;
+ __le64 frames_tx_pri_3;
+ __le64 frames_tx_pri_4;
+ __le64 frames_tx_pri_5;
+ __le64 frames_tx_pri_6;
+ __le64 frames_tx_pri_7;
+ __le64 frames_rx_pri_0;
+ __le64 frames_rx_pri_1;
+ __le64 frames_rx_pri_2;
+ __le64 frames_rx_pri_3;
+ __le64 frames_rx_pri_4;
+ __le64 frames_rx_pri_5;
+ __le64 frames_rx_pri_6;
+ __le64 frames_rx_pri_7;
+ __le64 tx_pripause_0_1us_count;
+ __le64 tx_pripause_1_1us_count;
+ __le64 tx_pripause_2_1us_count;
+ __le64 tx_pripause_3_1us_count;
+ __le64 tx_pripause_4_1us_count;
+ __le64 tx_pripause_5_1us_count;
+ __le64 tx_pripause_6_1us_count;
+ __le64 tx_pripause_7_1us_count;
+ __le64 rx_pripause_0_1us_count;
+ __le64 rx_pripause_1_1us_count;
+ __le64 rx_pripause_2_1us_count;
+ __le64 rx_pripause_3_1us_count;
+ __le64 rx_pripause_4_1us_count;
+ __le64 rx_pripause_5_1us_count;
+ __le64 rx_pripause_6_1us_count;
+ __le64 rx_pripause_7_1us_count;
+ __le64 rx_pause_1us_count;
+ __le64 frames_tx_truncated;
+};
+
+struct mgmt_port_stats {
+ __le64 frames_rx_ok;
+ __le64 frames_rx_all;
+ __le64 frames_rx_bad_fcs;
+ __le64 frames_rx_bad_all;
+ __le64 octets_rx_ok;
+ __le64 octets_rx_all;
+ __le64 frames_rx_unicast;
+ __le64 frames_rx_multicast;
+ __le64 frames_rx_broadcast;
+ __le64 frames_rx_pause;
+ __le64 frames_rx_bad_length0;
+ __le64 frames_rx_undersized1;
+ __le64 frames_rx_oversized2;
+ __le64 frames_rx_fragments3;
+ __le64 frames_rx_jabber4;
+ __le64 frames_rx_64b5;
+ __le64 frames_rx_65b_127b6;
+ __le64 frames_rx_128b_255b7;
+ __le64 frames_rx_256b_511b8;
+ __le64 frames_rx_512b_1023b9;
+ __le64 frames_rx_1024b_1518b0;
+ __le64 frames_rx_gt_1518b1;
+ __le64 frames_rx_fifo_full2;
+ __le64 frames_tx_ok3;
+ __le64 frames_tx_all4;
+ __le64 frames_tx_bad5;
+ __le64 octets_tx_ok6;
+ __le64 octets_tx_total7;
+ __le64 frames_tx_unicast8;
+ __le64 frames_tx_multicast9;
+ __le64 frames_tx_broadcast0;
+ __le64 frames_tx_pause1;
+};
+
+/**
+ * struct port_identity - port identity structure
+ * @version: identity structure version
+ * @type: type of port (enum port_type)
+ * @num_lanes: number of lanes for the port
+ * @autoneg: autoneg supported
+ * @min_frame_size: minimum frame size supported
+ * @max_frame_size: maximum frame size supported
+ * @fec_type: supported fec types
+ * @pause_type: supported pause types
+ * @loopback_mode: supported loopback mode
+ * @speeds: supported speeds
+ * @config: current port configuration
+ */
+union port_identity {
+ struct {
+ u8 version;
+ u8 type;
+ u8 num_lanes;
+ u8 autoneg;
+ __le32 min_frame_size;
+ __le32 max_frame_size;
+ u8 fec_type[4];
+ u8 pause_type[2];
+ u8 loopback_mode[2];
+ __le32 speeds[16];
+ u8 rsvd2[44];
+ union port_config config;
+ };
+ __le32 words[512];
+};
+
+/**
+ * struct port_info - port info structure
+ * @port_status: port status
+ * @port_stats: port stats
+ */
+struct port_info {
+ union port_config config;
+ struct port_status status;
+ struct port_stats stats;
+};
+
+/**
+ * struct lif_stats
+ */
+struct lif_stats {
+ /* RX */
+ __le64 rx_ucast_bytes;
+ __le64 rx_ucast_packets;
+ __le64 rx_mcast_bytes;
+ __le64 rx_mcast_packets;
+ __le64 rx_bcast_bytes;
+ __le64 rx_bcast_packets;
+ __le64 rsvd0;
+ __le64 rsvd1;
+ /* RX drops */
+ __le64 rx_ucast_drop_bytes;
+ __le64 rx_ucast_drop_packets;
+ __le64 rx_mcast_drop_bytes;
+ __le64 rx_mcast_drop_packets;
+ __le64 rx_bcast_drop_bytes;
+ __le64 rx_bcast_drop_packets;
+ __le64 rx_dma_error;
+ __le64 rsvd2;
+ /* TX */
+ __le64 tx_ucast_bytes;
+ __le64 tx_ucast_packets;
+ __le64 tx_mcast_bytes;
+ __le64 tx_mcast_packets;
+ __le64 tx_bcast_bytes;
+ __le64 tx_bcast_packets;
+ __le64 rsvd3;
+ __le64 rsvd4;
+ /* TX drops */
+ __le64 tx_ucast_drop_bytes;
+ __le64 tx_ucast_drop_packets;
+ __le64 tx_mcast_drop_bytes;
+ __le64 tx_mcast_drop_packets;
+ __le64 tx_bcast_drop_bytes;
+ __le64 tx_bcast_drop_packets;
+ __le64 tx_dma_error;
+ __le64 rsvd5;
+ /* Rx Queue/Ring drops */
+ __le64 rx_queue_disabled;
+ __le64 rx_queue_empty;
+ __le64 rx_queue_error;
+ __le64 rx_desc_fetch_error;
+ __le64 rx_desc_data_error;
+ __le64 rsvd6;
+ __le64 rsvd7;
+ __le64 rsvd8;
+ /* Tx Queue/Ring drops */
+ __le64 tx_queue_disabled;
+ __le64 tx_queue_error;
+ __le64 tx_desc_fetch_error;
+ __le64 tx_desc_data_error;
+ __le64 rsvd9;
+ __le64 rsvd10;
+ __le64 rsvd11;
+ __le64 rsvd12;
+
+ /* RDMA/ROCE TX */
+ __le64 tx_rdma_ucast_bytes;
+ __le64 tx_rdma_ucast_packets;
+ __le64 tx_rdma_mcast_bytes;
+ __le64 tx_rdma_mcast_packets;
+ __le64 tx_rdma_cnp_packets;
+ __le64 rsvd13;
+ __le64 rsvd14;
+ __le64 rsvd15;
+
+ /* RDMA/ROCE RX */
+ __le64 rx_rdma_ucast_bytes;
+ __le64 rx_rdma_ucast_packets;
+ __le64 rx_rdma_mcast_bytes;
+ __le64 rx_rdma_mcast_packets;
+ __le64 rx_rdma_cnp_packets;
+ __le64 rx_rdma_ecn_packets;
+ __le64 rsvd16;
+ __le64 rsvd17;
+
+ __le64 rsvd18;
+ __le64 rsvd19;
+ __le64 rsvd20;
+ __le64 rsvd21;
+ __le64 rsvd22;
+ __le64 rsvd23;
+ __le64 rsvd24;
+ __le64 rsvd25;
+
+ __le64 rsvd26;
+ __le64 rsvd27;
+ __le64 rsvd28;
+ __le64 rsvd29;
+ __le64 rsvd30;
+ __le64 rsvd31;
+ __le64 rsvd32;
+ __le64 rsvd33;
+
+ __le64 rsvd34;
+ __le64 rsvd35;
+ __le64 rsvd36;
+ __le64 rsvd37;
+ __le64 rsvd38;
+ __le64 rsvd39;
+ __le64 rsvd40;
+ __le64 rsvd41;
+
+ __le64 rsvd42;
+ __le64 rsvd43;
+ __le64 rsvd44;
+ __le64 rsvd45;
+ __le64 rsvd46;
+ __le64 rsvd47;
+ __le64 rsvd48;
+ __le64 rsvd49;
+
+ /* RDMA/ROCE REQ Error/Debugs (768 - 895) */
+ __le64 rdma_req_rx_pkt_seq_err;
+ __le64 rdma_req_rx_rnr_retry_err;
+ __le64 rdma_req_rx_remote_access_err;
+ __le64 rdma_req_rx_remote_inv_req_err;
+ __le64 rdma_req_rx_remote_oper_err;
+ __le64 rdma_req_rx_implied_nak_seq_err;
+ __le64 rdma_req_rx_cqe_err;
+ __le64 rdma_req_rx_cqe_flush_err;
+
+ __le64 rdma_req_rx_dup_responses;
+ __le64 rdma_req_rx_invalid_packets;
+ __le64 rdma_req_tx_local_access_err;
+ __le64 rdma_req_tx_local_oper_err;
+ __le64 rdma_req_tx_memory_mgmt_err;
+ __le64 rsvd52;
+ __le64 rsvd53;
+ __le64 rsvd54;
+
+ /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */
+ __le64 rdma_resp_rx_dup_requests;
+ __le64 rdma_resp_rx_out_of_buffer;
+ __le64 rdma_resp_rx_out_of_seq_pkts;
+ __le64 rdma_resp_rx_cqe_err;
+ __le64 rdma_resp_rx_cqe_flush_err;
+ __le64 rdma_resp_rx_local_len_err;
+ __le64 rdma_resp_rx_inv_request_err;
+ __le64 rdma_resp_rx_local_qp_oper_err;
+
+ __le64 rdma_resp_rx_out_of_atomic_resource;
+ __le64 rdma_resp_tx_pkt_seq_err;
+ __le64 rdma_resp_tx_remote_inv_req_err;
+ __le64 rdma_resp_tx_remote_access_err;
+ __le64 rdma_resp_tx_remote_oper_err;
+ __le64 rdma_resp_tx_rnr_retry_err;
+ __le64 rsvd57;
+ __le64 rsvd58;
+};
+
+/**
+ * struct lif_info - lif info structure
+ */
+struct lif_info {
+ union lif_config config;
+ struct lif_status status;
+ struct lif_stats stats;
+};
+
+union dev_cmd {
+ u32 words[16];
+ struct admin_cmd cmd;
+ struct nop_cmd nop;
+
+ struct dev_identify_cmd identify;
+ struct dev_init_cmd init;
+ struct dev_reset_cmd reset;
+ struct dev_getattr_cmd getattr;
+ struct dev_setattr_cmd setattr;
+
+ struct port_identify_cmd port_identify;
+ struct port_init_cmd port_init;
+ struct port_reset_cmd port_reset;
+ struct port_getattr_cmd port_getattr;
+ struct port_setattr_cmd port_setattr;
+
+ struct lif_identify_cmd lif_identify;
+ struct lif_init_cmd lif_init;
+ struct lif_reset_cmd lif_reset;
+
+ struct qos_identify_cmd qos_identify;
+ struct qos_init_cmd qos_init;
+ struct qos_reset_cmd qos_reset;
+
+ struct q_init_cmd q_init;
+};
+
+union dev_cmd_comp {
+ u32 words[4];
+ u8 status;
+ struct admin_comp comp;
+ struct nop_comp nop;
+
+ struct dev_identify_comp identify;
+ struct dev_init_comp init;
+ struct dev_reset_comp reset;
+ struct dev_getattr_comp getattr;
+ struct dev_setattr_comp setattr;
+
+ struct port_identify_comp port_identify;
+ struct port_init_comp port_init;
+ struct port_reset_comp port_reset;
+ struct port_getattr_comp port_getattr;
+ struct port_setattr_comp port_setattr;
+
+ struct lif_identify_comp lif_identify;
+ struct lif_init_comp lif_init;
+ lif_reset_comp lif_reset;
+
+ struct qos_identify_comp qos_identify;
+ qos_init_comp qos_init;
+ qos_reset_comp qos_reset;
+
+ struct q_init_comp q_init;
+};
+
+/**
+ * union dev_info - Device info register format (read-only)
+ * @signature: Signature value of 0x44455649 ('DEVI').
+ * @version: Current version of info.
+ * @asic_type: Asic type.
+ * @asic_rev: Asic revision.
+ * @fw_status: Firmware status.
+ * @fw_heartbeat: Firmware heartbeat counter.
+ * @serial_num: Serial number.
+ * @fw_version: Firmware version.
+ */
+union dev_info_regs {
+#define IONIC_DEVINFO_FWVERS_BUFLEN 32
+#define IONIC_DEVINFO_SERIAL_BUFLEN 32
+ struct {
+ u32 signature;
+ u8 version;
+ u8 asic_type;
+ u8 asic_rev;
+ u8 fw_status;
+ u32 fw_heartbeat;
+ char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
+ char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
+ };
+ u32 words[512];
+};
+
+/**
+ * union dev_cmd_regs - Device command register format (read-write)
+ * @doorbell: Device Cmd Doorbell, write-only.
+ * Write a 1 to signal device to process cmd,
+ * poll done for completion.
+ * @done: Done indicator, bit 0 == 1 when command is complete.
+ * @cmd: Opcode-specific command bytes
+ * @comp: Opcode-specific response bytes
+ * @data: Opcode-specific side-data
+ */
+union dev_cmd_regs {
+ struct {
+ u32 doorbell;
+ u32 done;
+ union dev_cmd cmd;
+ union dev_cmd_comp comp;
+ u8 rsvd[48];
+ u32 data[478];
+ };
+ u32 words[512];
+};
+
+/**
+ * union dev_regs - Device register format in for bar 0 page 0
+ * @info: Device info registers
+ * @devcmd: Device command registers
+ */
+union dev_regs {
+ struct {
+ union dev_info_regs info;
+ union dev_cmd_regs devcmd;
+ };
+ __le32 words[1024];
+};
+
+union adminq_cmd {
+ struct admin_cmd cmd;
+ struct nop_cmd nop;
+ struct q_init_cmd q_init;
+ struct q_control_cmd q_control;
+ struct lif_setattr_cmd lif_setattr;
+ struct lif_getattr_cmd lif_getattr;
+ struct rx_mode_set_cmd rx_mode_set;
+ struct rx_filter_add_cmd rx_filter_add;
+ struct rx_filter_del_cmd rx_filter_del;
+ struct rdma_reset_cmd rdma_reset;
+ struct rdma_queue_cmd rdma_queue;
+ struct fw_download_cmd fw_download;
+ struct fw_control_cmd fw_control;
+};
+
+union adminq_comp {
+ struct admin_comp comp;
+ struct nop_comp nop;
+ struct q_init_comp q_init;
+ struct lif_setattr_comp lif_setattr;
+ struct lif_getattr_comp lif_getattr;
+ struct rx_filter_add_comp rx_filter_add;
+ struct fw_control_comp fw_control;
+};
+
+#define IONIC_BARS_MAX 6
+#define IONIC_PCI_BAR_DBELL 1
+
+/* BAR0 */
+#define BAR0_SIZE 0x8000
+
+#define BAR0_DEV_INFO_REGS_OFFSET 0x0000
+#define BAR0_DEV_CMD_REGS_OFFSET 0x0800
+#define BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
+#define BAR0_INTR_STATUS_OFFSET 0x1000
+#define BAR0_INTR_CTRL_OFFSET 0x2000
+#define DEV_CMD_DONE 0x00000001
+
+#define ASIC_TYPE_CAPRI 0
+
+/**
+ * struct doorbell - Doorbell register layout
+ * @p_index: Producer index
+ * @ring: Selects the specific ring of the queue to update.
+ * Type-specific meaning:
+ * ring=0: Default producer/consumer queue.
+ * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs
+ * send events to EQs when armed. EQs send
+ * interrupts when armed.
+ * @qid: The queue id selects the queue destination for the
+ * producer index and flags.
+ */
+struct doorbell {
+ __le16 p_index;
+ u8 ring;
+ u8 qid_lo;
+ __le16 qid_hi;
+ u16 rsvd2;
+};
+
+/**
+ * struct intr_ctrl - Interrupt control register
+ * @coalescing_init: Coalescing timer initial value, in
+ * device units. Use @identity->intr_coal_mult
+ * and @identity->intr_coal_div to convert from
+ * usecs to device units:
+ *
+ * coal_init = coal_usecs * coal_mutl / coal_div
+ *
+ * When an interrupt is sent the interrupt
+ * coalescing timer current value
+ * (@coalescing_curr) is initialized with this
+ * value and begins counting down. No more
+ * interrupts are sent until the coalescing
+ * timer reaches 0. When @coalescing_init=0
+ * interrupt coalescing is effectively disabled
+ * and every interrupt assert results in an
+ * interrupt. Reset value: 0.
+ * @mask: Interrupt mask. When @mask=1 the interrupt
+ * resource will not send an interrupt. When
+ * @mask=0 the interrupt resource will send an
+ * interrupt if an interrupt event is pending
+ * or on the next interrupt assertion event.
+ * Reset value: 1.
+ * @int_credits: Interrupt credits. This register indicates
+ * how many interrupt events the hardware has
+ * sent. When written by software this
+ * register atomically decrements @int_credits
+ * by the value written. When @int_credits
+ * becomes 0 then the "pending interrupt" bit
+ * in the Interrupt Status register is cleared
+ * by the hardware and any pending but unsent
+ * interrupts are cleared.
+ * !!!IMPORTANT!!! This is a signed register.
+ * @flags: Interrupt control flags
+ * @unmask -- When this bit is written with a 1
+ * the interrupt resource will set mask=0.
+ * @coal_timer_reset -- When this
+ * bit is written with a 1 the
+ * @coalescing_curr will be reloaded with
+ * @coalescing_init to reset the coalescing
+ * timer.
+ * @mask_on_assert: Automatically mask on assertion. When
+ * @mask_on_assert=1 the interrupt resource
+ * will set @mask=1 whenever an interrupt is
+ * sent. When using interrupts in Legacy
+ * Interrupt mode the driver must select
+ * @mask_on_assert=0 for proper interrupt
+ * operation.
+ * @coalescing_curr: Coalescing timer current value, in
+ * microseconds. When this value reaches 0
+ * the interrupt resource is again eligible to
+ * send an interrupt. If an interrupt event
+ * is already pending when @coalescing_curr
+ * reaches 0 the pending interrupt will be
+ * sent, otherwise an interrupt will be sent
+ * on the next interrupt assertion event.
+ */
+struct intr_ctrl {
+ u8 coalescing_init;
+ u8 rsvd[3];
+ u8 mask;
+ u8 rsvd2[3];
+ u16 int_credits;
+ u16 flags;
+#define INTR_F_UNMASK 0x0001
+#define INTR_F_TIMER_RESET 0x0002
+ u8 mask_on_assert;
+ u8 rsvd3[3];
+ u8 coalescing_curr;
+ u8 rsvd4[3];
+ u32 rsvd6[3];
+};
+
+#define INTR_CTRL_REGS_MAX 2048
+#define INTR_CTRL_COAL_MAX 0x3F
+
+#define intr_to_coal(intr_ctrl) \
+ ((void __iomem *)&(intr_ctrl)->coalescing_init)
+#define intr_to_mask(intr_ctrl) \
+ ((void __iomem *)&(intr_ctrl)->mask)
+#define intr_to_credits(intr_ctrl) \
+ ((void __iomem *)&(intr_ctrl)->int_credits)
+#define intr_to_mask_on_assert(intr_ctrl)\
+ ((void __iomem *)&(intr_ctrl)->mask_on_assert)
+
+struct intr_status {
+ u32 status[2];
+};
+
+struct notifyq_cmd {
+ __le32 data; /* Not used but needed for qcq structure */
+};
+
+union notifyq_comp {
+ struct notifyq_event event;
+ struct link_change_event link_change;
+ struct reset_event reset;
+ struct heartbeat_event heartbeat;
+ struct log_event log;
+};
+
+/* Deprecate */
+struct identity {
+ union drv_identity drv;
+ union dev_identity dev;
+ union lif_identity lif;
+ union port_identity port;
+ union qos_identity qos;
+};
+
+#pragma pack(pop)
+
+#endif /* _IONIC_IF_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_main.c b/drivers/net/ethernet/pensando/ionic/ionic_main.c
index fb49c0ca5095..567ed259b398 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_main.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_main.c
@@ -8,14 +8,309 @@
#include "ionic.h"
#include "ionic_bus.h"
+#include "ionic_debugfs.h"
MODULE_DESCRIPTION(DRV_DESCRIPTION);
MODULE_AUTHOR("Pensando Systems, Inc");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
+static const char *ionic_error_to_str(enum status_code code)
+{
+ switch (code) {
+ case IONIC_RC_SUCCESS:
+ return "IONIC_RC_SUCCESS";
+ case IONIC_RC_EVERSION:
+ return "IONIC_RC_EVERSION";
+ case IONIC_RC_EOPCODE:
+ return "IONIC_RC_EOPCODE";
+ case IONIC_RC_EIO:
+ return "IONIC_RC_EIO";
+ case IONIC_RC_EPERM:
+ return "IONIC_RC_EPERM";
+ case IONIC_RC_EQID:
+ return "IONIC_RC_EQID";
+ case IONIC_RC_EQTYPE:
+ return "IONIC_RC_EQTYPE";
+ case IONIC_RC_ENOENT:
+ return "IONIC_RC_ENOENT";
+ case IONIC_RC_EINTR:
+ return "IONIC_RC_EINTR";
+ case IONIC_RC_EAGAIN:
+ return "IONIC_RC_EAGAIN";
+ case IONIC_RC_ENOMEM:
+ return "IONIC_RC_ENOMEM";
+ case IONIC_RC_EFAULT:
+ return "IONIC_RC_EFAULT";
+ case IONIC_RC_EBUSY:
+ return "IONIC_RC_EBUSY";
+ case IONIC_RC_EEXIST:
+ return "IONIC_RC_EEXIST";
+ case IONIC_RC_EINVAL:
+ return "IONIC_RC_EINVAL";
+ case IONIC_RC_ENOSPC:
+ return "IONIC_RC_ENOSPC";
+ case IONIC_RC_ERANGE:
+ return "IONIC_RC_ERANGE";
+ case IONIC_RC_BAD_ADDR:
+ return "IONIC_RC_BAD_ADDR";
+ case IONIC_RC_DEV_CMD:
+ return "IONIC_RC_DEV_CMD";
+ case IONIC_RC_ERROR:
+ return "IONIC_RC_ERROR";
+ case IONIC_RC_ERDMA:
+ return "IONIC_RC_ERDMA";
+ default:
+ return "IONIC_RC_UNKNOWN";
+ }
+}
+
+static int ionic_error_to_errno(enum status_code code)
+{
+ switch (code) {
+ case IONIC_RC_SUCCESS:
+ return 0;
+ case IONIC_RC_EVERSION:
+ case IONIC_RC_EQTYPE:
+ case IONIC_RC_EQID:
+ case IONIC_RC_EINVAL:
+ return -EINVAL;
+ case IONIC_RC_EPERM:
+ return -EPERM;
+ case IONIC_RC_ENOENT:
+ return -ENOENT;
+ case IONIC_RC_EAGAIN:
+ return -EAGAIN;
+ case IONIC_RC_ENOMEM:
+ return -ENOMEM;
+ case IONIC_RC_EFAULT:
+ return -EFAULT;
+ case IONIC_RC_EBUSY:
+ return -EBUSY;
+ case IONIC_RC_EEXIST:
+ return -EEXIST;
+ case IONIC_RC_ENOSPC:
+ return -ENOSPC;
+ case IONIC_RC_ERANGE:
+ return -ERANGE;
+ case IONIC_RC_BAD_ADDR:
+ return -EFAULT;
+ case IONIC_RC_EOPCODE:
+ case IONIC_RC_EINTR:
+ case IONIC_RC_DEV_CMD:
+ case IONIC_RC_ERROR:
+ case IONIC_RC_ERDMA:
+ case IONIC_RC_EIO:
+ default:
+ return -EIO;
+ }
+}
+
+static const char *ionic_opcode_to_str(enum cmd_opcode opcode)
+{
+ switch (opcode) {
+ case CMD_OPCODE_NOP:
+ return "CMD_OPCODE_NOP";
+ case CMD_OPCODE_INIT:
+ return "CMD_OPCODE_INIT";
+ case CMD_OPCODE_RESET:
+ return "CMD_OPCODE_RESET";
+ case CMD_OPCODE_IDENTIFY:
+ return "CMD_OPCODE_IDENTIFY";
+ case CMD_OPCODE_GETATTR:
+ return "CMD_OPCODE_GETATTR";
+ case CMD_OPCODE_SETATTR:
+ return "CMD_OPCODE_SETATTR";
+ case CMD_OPCODE_PORT_IDENTIFY:
+ return "CMD_OPCODE_PORT_IDENTIFY";
+ case CMD_OPCODE_PORT_INIT:
+ return "CMD_OPCODE_PORT_INIT";
+ case CMD_OPCODE_PORT_RESET:
+ return "CMD_OPCODE_PORT_RESET";
+ case CMD_OPCODE_PORT_GETATTR:
+ return "CMD_OPCODE_PORT_GETATTR";
+ case CMD_OPCODE_PORT_SETATTR:
+ return "CMD_OPCODE_PORT_SETATTR";
+ case CMD_OPCODE_LIF_INIT:
+ return "CMD_OPCODE_LIF_INIT";
+ case CMD_OPCODE_LIF_RESET:
+ return "CMD_OPCODE_LIF_RESET";
+ case CMD_OPCODE_LIF_IDENTIFY:
+ return "CMD_OPCODE_LIF_IDENTIFY";
+ case CMD_OPCODE_LIF_SETATTR:
+ return "CMD_OPCODE_LIF_SETATTR";
+ case CMD_OPCODE_LIF_GETATTR:
+ return "CMD_OPCODE_LIF_GETATTR";
+ case CMD_OPCODE_RX_MODE_SET:
+ return "CMD_OPCODE_RX_MODE_SET";
+ case CMD_OPCODE_RX_FILTER_ADD:
+ return "CMD_OPCODE_RX_FILTER_ADD";
+ case CMD_OPCODE_RX_FILTER_DEL:
+ return "CMD_OPCODE_RX_FILTER_DEL";
+ case CMD_OPCODE_Q_INIT:
+ return "CMD_OPCODE_Q_INIT";
+ case CMD_OPCODE_Q_CONTROL:
+ return "CMD_OPCODE_Q_CONTROL";
+ case CMD_OPCODE_RDMA_RESET_LIF:
+ return "CMD_OPCODE_RDMA_RESET_LIF";
+ case CMD_OPCODE_RDMA_CREATE_EQ:
+ return "CMD_OPCODE_RDMA_CREATE_EQ";
+ case CMD_OPCODE_RDMA_CREATE_CQ:
+ return "CMD_OPCODE_RDMA_CREATE_CQ";
+ case CMD_OPCODE_RDMA_CREATE_ADMINQ:
+ return "CMD_OPCODE_RDMA_CREATE_ADMINQ";
+ case CMD_OPCODE_FW_DOWNLOAD:
+ return "CMD_OPCODE_FW_DOWNLOAD";
+ case CMD_OPCODE_FW_CONTROL:
+ return "CMD_OPCODE_FW_CONTROL";
+ default:
+ return "DEVCMD_UNKNOWN";
+ }
+}
+
+int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_seconds)
+{
+ struct ionic_dev *idev = &ionic->idev;
+ unsigned long max_wait, start_time, duration;
+ int opcode;
+ int done;
+ int err;
+
+ WARN_ON(in_interrupt());
+
+ /* Wait for dev cmd to complete, retrying if we get EAGAIN,
+ * but don't wait any longer than max_seconds.
+ */
+ max_wait = jiffies + (max_seconds * HZ);
+try_again:
+ start_time = jiffies;
+ do {
+ done = ionic_dev_cmd_done(idev);
+ if (done)
+ break;
+ msleep(20);
+ } while (!done && time_before(jiffies, max_wait));
+ duration = jiffies - start_time;
+
+ opcode = idev->dev_cmd_regs->cmd.cmd.opcode;
+ dev_dbg(ionic->dev, "DEVCMD %s (%d) done=%d took %ld secs (%ld jiffies)\n",
+ ionic_opcode_to_str(opcode), opcode,
+ done, duration / HZ, duration);
+
+ if (!done && !time_before(jiffies, max_wait)) {
+ dev_warn(ionic->dev, "DEVCMD %s (%d) timeout after %ld secs\n",
+ ionic_opcode_to_str(opcode), opcode, max_seconds);
+ return -ETIMEDOUT;
+ }
+
+ err = ionic_dev_cmd_status(&ionic->idev);
+ if (err) {
+ if (err == IONIC_RC_EAGAIN && !time_after(jiffies, max_wait)) {
+ dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s (%d) retrying...\n",
+ ionic_opcode_to_str(opcode), opcode,
+ ionic_error_to_str(err), err);
+
+ msleep(1000);
+ iowrite32(0, &idev->dev_cmd_regs->done);
+ iowrite32(1, &idev->dev_cmd_regs->doorbell);
+ goto try_again;
+ }
+
+ dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s (%d) failed\n",
+ ionic_opcode_to_str(opcode), opcode,
+ ionic_error_to_str(err), err);
+
+ return ionic_error_to_errno(err);
+ }
+
+ return 0;
+}
+
+int ionic_setup(struct ionic *ionic)
+{
+ int err;
+
+ err = ionic_dev_setup(ionic);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+int ionic_identify(struct ionic *ionic)
+{
+ struct identity *ident = &ionic->ident;
+ struct ionic_dev *idev = &ionic->idev;
+ size_t sz;
+ int err;
+
+ memset(ident, 0, sizeof(*ident));
+
+ ident->drv.os_type = cpu_to_le32(IONIC_OS_TYPE_LINUX);
+ ident->drv.os_dist = 0;
+ strncpy(ident->drv.os_dist_str, utsname()->release,
+ sizeof(ident->drv.os_dist_str) - 1);
+ ident->drv.kernel_ver = cpu_to_le32(LINUX_VERSION_CODE);
+ strncpy(ident->drv.kernel_ver_str, utsname()->version,
+ sizeof(ident->drv.kernel_ver_str) - 1);
+ strncpy(ident->drv.driver_ver_str, DRV_VERSION,
+ sizeof(ident->drv.driver_ver_str) - 1);
+
+ mutex_lock(&ionic->dev_cmd_lock);
+
+ sz = min(sizeof(ident->drv), sizeof(idev->dev_cmd_regs->data));
+ memcpy_toio(&idev->dev_cmd_regs->data, &ident->drv, sz);
+
+ ionic_dev_cmd_identify(idev, IONIC_IDENTITY_VERSION_1);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ if (!err) {
+ sz = min(sizeof(ident->dev), sizeof(idev->dev_cmd_regs->data));
+ memcpy_fromio(&ident->dev, &idev->dev_cmd_regs->data, sz);
+ }
+
+ mutex_unlock(&ionic->dev_cmd_lock);
+
+ if (err)
+ goto err_out_unmap;
+
+ ionic_debugfs_add_ident(ionic);
+
+ return 0;
+
+err_out_unmap:
+ return err;
+}
+
+int ionic_init(struct ionic *ionic)
+{
+ struct ionic_dev *idev = &ionic->idev;
+ int err;
+
+ mutex_lock(&ionic->dev_cmd_lock);
+ ionic_dev_cmd_init(idev);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ mutex_unlock(&ionic->dev_cmd_lock);
+
+ return err;
+}
+
+int ionic_reset(struct ionic *ionic)
+{
+ struct ionic_dev *idev = &ionic->idev;
+ int err;
+
+ mutex_lock(&ionic->dev_cmd_lock);
+ ionic_dev_cmd_reset(idev);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ mutex_unlock(&ionic->dev_cmd_lock);
+
+ return err;
+}
+
static int __init ionic_init_module(void)
{
+ ionic_struct_size_checks();
+ ionic_debugfs_create();
pr_info("%s %s, ver %s\n", DRV_NAME, DRV_DESCRIPTION, DRV_VERSION);
return ionic_bus_register_driver();
}
@@ -23,6 +318,7 @@ static int __init ionic_init_module(void)
static void __exit ionic_cleanup_module(void)
{
ionic_bus_unregister_driver();
+ ionic_debugfs_destroy();
}
module_init(ionic_init_module);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_regs.h b/drivers/net/ethernet/pensando/ionic/ionic_regs.h
new file mode 100644
index 000000000000..3523915061ed
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_regs.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */
+/* Copyright (c) 2018-2019 Pensando Systems, Inc. All rights reserved. */
+
+#ifndef IONIC_REGS_H
+#define IONIC_REGS_H
+
+#include <linux/io.h>
+
+/** struct ionic_intr - interrupt control register set.
+ * @coal_init: coalesce timer initial value.
+ * @mask: interrupt mask value.
+ * @credits: interrupt credit count and return.
+ * @mask_assert: interrupt mask value on assert.
+ * @coal: coalesce timer time remaining.
+ */
+struct ionic_intr {
+ u32 coal_init;
+ u32 mask;
+ u32 credits;
+ u32 mask_assert;
+ u32 coal;
+ u32 rsvd[3];
+};
+
+/** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
+ * @IONIC_INTR_MASK_CLEAR: unmask interrupt.
+ * @IONIC_INTR_MASK_SET: mask interrupt.
+ */
+enum ionic_intr_mask_vals {
+ IONIC_INTR_MASK_CLEAR = 0,
+ IONIC_INTR_MASK_SET = 1,
+};
+
+/** enum ionic_intr_credits_bits - bitwise composition of credits values.
+ * @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed.
+ * @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit.
+ * @IONIC_INTR_CRED_UNMASK: unmask the interrupt.
+ * @IONIC_INTR_CRED_RESET_COALESCE: reset the coalesce timer.
+ * @IONIC_INTR_CRED_REARM: unmask the and reset the timer.
+ */
+enum ionic_intr_credits_bits {
+ IONIC_INTR_CRED_COUNT = 0x7fffu,
+ IONIC_INTR_CRED_COUNT_SIGNED = 0xffffu,
+ IONIC_INTR_CRED_UNMASK = 0x10000u,
+ IONIC_INTR_CRED_RESET_COALESCE = 0x20000u,
+ IONIC_INTR_CRED_REARM = (IONIC_INTR_CRED_UNMASK |
+ IONIC_INTR_CRED_RESET_COALESCE),
+};
+
+static inline void ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl,
+ int intr_idx, u32 coal)
+{
+ iowrite32(coal, &intr_ctrl[intr_idx].coal_init);
+}
+
+static inline void ionic_intr_mask(struct ionic_intr __iomem *intr_ctrl,
+ int intr_idx, u32 mask)
+{
+ iowrite32(mask, &intr_ctrl[intr_idx].mask);
+}
+
+static inline void ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl,
+ int intr_idx, u32 cred, u32 flags)
+{
+ if (WARN_ON_ONCE(cred > IONIC_INTR_CRED_COUNT)) {
+ cred = ioread32(&intr_ctrl[intr_idx].credits);
+ cred &= IONIC_INTR_CRED_COUNT_SIGNED;
+ }
+
+ iowrite32(cred | flags, &intr_ctrl[intr_idx].credits);
+}
+
+static inline void ionic_intr_clean(struct ionic_intr __iomem *intr_ctrl,
+ int intr_idx)
+{
+ u32 cred;
+
+ cred = ioread32(&intr_ctrl[intr_idx].credits);
+ cred &= IONIC_INTR_CRED_COUNT_SIGNED;
+ cred |= IONIC_INTR_CRED_RESET_COALESCE;
+ iowrite32(cred, &intr_ctrl[intr_idx].credits);
+}
+
+static inline void ionic_intr_mask_assert(struct ionic_intr __iomem *intr_ctrl,
+ int intr_idx, u32 mask)
+{
+ iowrite32(mask, &intr_ctrl[intr_idx].mask_assert);
+}
+
+/** enum ionic_dbell_bits - bitwise composition of dbell values.
+ *
+ * @IONIC_DBELL_QID_MASK: unshifted mask of valid queue id bits.
+ * @IONIC_DBELL_QID_SHIFT: queue id shift amount in dbell value.
+ * @IONIC_DBELL_QID: macro to build QID component of dbell value.
+ *
+ * @IONIC_DBELL_RING_MASK: unshifted mask of valid ring bits.
+ * @IONIC_DBELL_RING_SHIFT: ring shift amount in dbell value.
+ * @IONIC_DBELL_RING: macro to build ring component of dbell value.
+ *
+ * @IONIC_DBELL_RING_0: ring zero dbell component value.
+ * @IONIC_DBELL_RING_1: ring one dbell component value.
+ * @IONIC_DBELL_RING_2: ring two dbell component value.
+ * @IONIC_DBELL_RING_3: ring three dbell component value.
+ *
+ * @IONIC_DBELL_INDEX_MASK: bit mask of valid index bits, no shift needed.
+ */
+enum ionic_dbell_bits {
+ IONIC_DBELL_QID_MASK = 0xffffff,
+ IONIC_DBELL_QID_SHIFT = 24,
+
+#define IONIC_DBELL_QID(n) \
+ (((u64)(n) & IONIC_DBELL_QID_MASK) << IONIC_DBELL_QID_SHIFT)
+
+ IONIC_DBELL_RING_MASK = 0x7,
+ IONIC_DBELL_RING_SHIFT = 16,
+
+#define IONIC_DBELL_RING(n) \
+ (((u64)(n) & IONIC_DBELL_RING_MASK) << IONIC_DBELL_RING_SHIFT)
+
+ IONIC_DBELL_RING_0 = 0,
+ IONIC_DBELL_RING_1 = IONIC_DBELL_RING(1),
+ IONIC_DBELL_RING_2 = IONIC_DBELL_RING(2),
+ IONIC_DBELL_RING_3 = IONIC_DBELL_RING(3),
+
+ IONIC_DBELL_INDEX_MASK = 0xffff,
+};
+
+static inline void ionic_dbell_ring(u64 __iomem *db_page, int qtype, u64 val)
+{
+ writeq(val, &db_page[qtype]);
+}
+
+#endif /* IONIC_REGS_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands
2019-07-22 21:40 ` [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands Shannon Nelson
@ 2019-07-23 21:18 ` David Miller
2019-07-23 22:50 ` Shannon Nelson
2019-07-23 23:47 ` Saeed Mahameed
1 sibling, 1 reply; 69+ messages in thread
From: David Miller @ 2019-07-23 21:18 UTC (permalink / raw)
To: snelson; +Cc: netdev
From: Shannon Nelson <snelson@pensando.io>
Date: Mon, 22 Jul 2019 14:40:06 -0700
> +void ionic_init_devinfo(struct ionic_dev *idev)
> +{
> + idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
> + idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
> +
> + memcpy_fromio(idev->dev_info.fw_version,
> + idev->dev_info_regs->fw_version,
> + IONIC_DEVINFO_FWVERS_BUFLEN);
> +
> + memcpy_fromio(idev->dev_info.serial_num,
> + idev->dev_info_regs->serial_num,
> + IONIC_DEVINFO_SERIAL_BUFLEN);
...
> + sig = ioread32(&idev->dev_info_regs->signature);
I think if you are going to use the io{read,write}{8,16,32,64}()
interfaces then you should use io{read,write}{8,16,32,64}_rep()
instead of memcpy_{to,from}io().
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands
2019-07-23 21:18 ` David Miller
@ 2019-07-23 22:50 ` Shannon Nelson
2019-07-23 23:05 ` David Miller
0 siblings, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-23 22:50 UTC (permalink / raw)
To: David Miller; +Cc: netdev
On 7/23/19 2:18 PM, David Miller wrote:
> From: Shannon Nelson <snelson@pensando.io>
> Date: Mon, 22 Jul 2019 14:40:06 -0700
>
>> +void ionic_init_devinfo(struct ionic_dev *idev)
>> +{
>> + idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
>> + idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
>> +
>> + memcpy_fromio(idev->dev_info.fw_version,
>> + idev->dev_info_regs->fw_version,
>> + IONIC_DEVINFO_FWVERS_BUFLEN);
>> +
>> + memcpy_fromio(idev->dev_info.serial_num,
>> + idev->dev_info_regs->serial_num,
>> + IONIC_DEVINFO_SERIAL_BUFLEN);
> ...
>> + sig = ioread32(&idev->dev_info_regs->signature);
> I think if you are going to use the io{read,write}{8,16,32,64}()
> interfaces then you should use io{read,write}{8,16,32,64}_rep()
> instead of memcpy_{to,from}io().
>
Sure.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands
2019-07-23 22:50 ` Shannon Nelson
@ 2019-07-23 23:05 ` David Miller
2019-07-23 23:23 ` Shannon Nelson
2019-07-24 17:49 ` Shannon Nelson
0 siblings, 2 replies; 69+ messages in thread
From: David Miller @ 2019-07-23 23:05 UTC (permalink / raw)
To: snelson; +Cc: netdev
From: Shannon Nelson <snelson@pensando.io>
Date: Tue, 23 Jul 2019 15:50:22 -0700
> On 7/23/19 2:18 PM, David Miller wrote:
>> From: Shannon Nelson <snelson@pensando.io>
>> Date: Mon, 22 Jul 2019 14:40:06 -0700
>>
>>> +void ionic_init_devinfo(struct ionic_dev *idev)
>>> +{
>>> + idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
>>> + idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
>>> +
>>> + memcpy_fromio(idev->dev_info.fw_version,
>>> + idev->dev_info_regs->fw_version,
>>> + IONIC_DEVINFO_FWVERS_BUFLEN);
>>> +
>>> + memcpy_fromio(idev->dev_info.serial_num,
>>> + idev->dev_info_regs->serial_num,
>>> + IONIC_DEVINFO_SERIAL_BUFLEN);
>> ...
>>> + sig = ioread32(&idev->dev_info_regs->signature);
>> I think if you are going to use the io{read,write}{8,16,32,64}()
>> interfaces then you should use io{read,write}{8,16,32,64}_rep()
>> instead of memcpy_{to,from}io().
>>
> Sure.
Note, I could be wrong. Please test.
I think the operation of the two things might be different.
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands
2019-07-23 23:05 ` David Miller
@ 2019-07-23 23:23 ` Shannon Nelson
2019-07-24 17:49 ` Shannon Nelson
1 sibling, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-23 23:23 UTC (permalink / raw)
To: David Miller; +Cc: netdev
On 7/23/19 4:05 PM, David Miller wrote:
> From: Shannon Nelson <snelson@pensando.io>
> Date: Tue, 23 Jul 2019 15:50:22 -0700
>
>> On 7/23/19 2:18 PM, David Miller wrote:
>>> From: Shannon Nelson <snelson@pensando.io>
>>> Date: Mon, 22 Jul 2019 14:40:06 -0700
>>>
>>>> +void ionic_init_devinfo(struct ionic_dev *idev)
>>>> +{
>>>> + idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
>>>> + idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
>>>> +
>>>> + memcpy_fromio(idev->dev_info.fw_version,
>>>> + idev->dev_info_regs->fw_version,
>>>> + IONIC_DEVINFO_FWVERS_BUFLEN);
>>>> +
>>>> + memcpy_fromio(idev->dev_info.serial_num,
>>>> + idev->dev_info_regs->serial_num,
>>>> + IONIC_DEVINFO_SERIAL_BUFLEN);
>>> ...
>>>> + sig = ioread32(&idev->dev_info_regs->signature);
>>> I think if you are going to use the io{read,write}{8,16,32,64}()
>>> interfaces then you should use io{read,write}{8,16,32,64}_rep()
>>> instead of memcpy_{to,from}io().
>>>
>> Sure.
> Note, I could be wrong. Please test.
>
> I think the operation of the two things might be different.
It seems to me that memcpy() usually just does the right thing in most
cases, so that's what I went with. Looking into some of the
definitions, and at how I used memcpy_...(), I think there are some
appropriate ways to use ioread32_rep() in a couple of my cases, and
another case or two where the memcpy variant may not make much
difference with ioread8_rep(). It's also possible that sparse may have
an opinion. I'll look at them.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands
2019-07-23 23:05 ` David Miller
2019-07-23 23:23 ` Shannon Nelson
@ 2019-07-24 17:49 ` Shannon Nelson
2019-07-24 20:07 ` David Miller
1 sibling, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-24 17:49 UTC (permalink / raw)
To: David Miller; +Cc: netdev
On 7/23/19 4:05 PM, David Miller wrote:
> From: Shannon Nelson <snelson@pensando.io>
> Date: Tue, 23 Jul 2019 15:50:22 -0700
>
>> On 7/23/19 2:18 PM, David Miller wrote:
>>> From: Shannon Nelson <snelson@pensando.io>
>>> Date: Mon, 22 Jul 2019 14:40:06 -0700
>>>
>>>> +void ionic_init_devinfo(struct ionic_dev *idev)
>>>> +{
>>>> + idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
>>>> + idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
>>>> +
>>>> + memcpy_fromio(idev->dev_info.fw_version,
>>>> + idev->dev_info_regs->fw_version,
>>>> + IONIC_DEVINFO_FWVERS_BUFLEN);
>>>> +
>>>> + memcpy_fromio(idev->dev_info.serial_num,
>>>> + idev->dev_info_regs->serial_num,
>>>> + IONIC_DEVINFO_SERIAL_BUFLEN);
>>> ...
>>>> + sig = ioread32(&idev->dev_info_regs->signature);
>>> I think if you are going to use the io{read,write}{8,16,32,64}()
>>> interfaces then you should use io{read,write}{8,16,32,64}_rep()
>>> instead of memcpy_{to,from}io().
>>>
>> Sure.
> Note, I could be wrong. Please test.
>
> I think the operation of the two things might be different.
Yes, they are different things, the iowrite*_rep() functions write each
value from a buffer all to the same single address, rather than copy a
buffer into another buffer, and the ioread*_rep() functions repeatedly
read from the same address to fill a buffer.
For example, the iowrite32_rep() boils down to this:
do {
__raw_writel(*buf++, addr);
} while (--count);
Not quite what I need.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands
2019-07-24 17:49 ` Shannon Nelson
@ 2019-07-24 20:07 ` David Miller
0 siblings, 0 replies; 69+ messages in thread
From: David Miller @ 2019-07-24 20:07 UTC (permalink / raw)
To: snelson; +Cc: netdev
From: Shannon Nelson <snelson@pensando.io>
Date: Wed, 24 Jul 2019 10:49:09 -0700
> On 7/23/19 4:05 PM, David Miller wrote:
>> From: Shannon Nelson <snelson@pensando.io>
>> Date: Tue, 23 Jul 2019 15:50:22 -0700
>>
>>> On 7/23/19 2:18 PM, David Miller wrote:
>>>> From: Shannon Nelson <snelson@pensando.io>
>>>> Date: Mon, 22 Jul 2019 14:40:06 -0700
>>>>
>>>>> +void ionic_init_devinfo(struct ionic_dev *idev)
>>>>> +{
>>>>> + idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
>>>>> + idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
>>>>> +
>>>>> + memcpy_fromio(idev->dev_info.fw_version,
>>>>> + idev->dev_info_regs->fw_version,
>>>>> + IONIC_DEVINFO_FWVERS_BUFLEN);
>>>>> +
>>>>> + memcpy_fromio(idev->dev_info.serial_num,
>>>>> + idev->dev_info_regs->serial_num,
>>>>> + IONIC_DEVINFO_SERIAL_BUFLEN);
>>>> ...
>>>>> + sig = ioread32(&idev->dev_info_regs->signature);
>>>> I think if you are going to use the io{read,write}{8,16,32,64}()
>>>> interfaces then you should use io{read,write}{8,16,32,64}_rep()
>>>> instead of memcpy_{to,from}io().
>>>>
>>> Sure.
>> Note, I could be wrong. Please test.
>>
>> I think the operation of the two things might be different.
> Yes, they are different things, the iowrite*_rep() functions write
> each value from a buffer all to the same single address, rather than
> copy a buffer into another buffer, and the ioread*_rep() functions
> repeatedly read from the same address to fill a buffer.
>
> For example, the iowrite32_rep() boils down to this:
> do {
> __raw_writel(*buf++, addr);
> } while (--count);
>
> Not quite what I need.
That's what I suspected.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands
2019-07-22 21:40 ` [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands Shannon Nelson
2019-07-23 21:18 ` David Miller
@ 2019-07-23 23:47 ` Saeed Mahameed
2019-07-24 0:25 ` Shannon Nelson
1 sibling, 1 reply; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-23 23:47 UTC (permalink / raw)
To: snelson, netdev, davem
On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> The ionic device has a small set of PCI registers, including a
> device control and data space, and a large set of message
> commands.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
> ---
> drivers/net/ethernet/pensando/ionic/Makefile | 2 +-
> drivers/net/ethernet/pensando/ionic/ionic.h | 20 +
> .../net/ethernet/pensando/ionic/ionic_bus.h | 1 +
> .../ethernet/pensando/ionic/ionic_bus_pci.c | 140 +-
> .../ethernet/pensando/ionic/ionic_debugfs.c | 67 +
> .../ethernet/pensando/ionic/ionic_debugfs.h | 28 +
> .../net/ethernet/pensando/ionic/ionic_dev.c | 132 +
> .../net/ethernet/pensando/ionic/ionic_dev.h | 144 +
> .../net/ethernet/pensando/ionic/ionic_if.h | 2552
> +++++++++++++++++
> .../net/ethernet/pensando/ionic/ionic_main.c | 296 ++
> .../net/ethernet/pensando/ionic/ionic_regs.h | 133 +
> 11 files changed, 3512 insertions(+), 3 deletions(-)
> create mode 100644
> drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
> create mode 100644
> drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_dev.c
> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_dev.h
> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_if.h
> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_regs.h
>
[...]
> static void ionic_remove(struct pci_dev *pdev)
> {
> struct ionic *ionic = pci_get_drvdata(pdev);
>
> - devm_kfree(&pdev->dev, ionic);
> + if (ionic) {
nit, in case you are doing another re-spin maybe early return here:
if (!ionic)
return;
//do stuff
> + ionic_reset(ionic);
> + ionic_dev_teardown(ionic);
> + ionic_unmap_bars(ionic);
> + pci_release_regions(pdev);
> + pci_clear_master(pdev);
> + pci_disable_sriov(pdev);
> + pci_disable_device(pdev);
> + ionic_debugfs_del_dev(ionic);
> + mutex_destroy(&ionic->dev_cmd_lock);
> +
> + devm_kfree(&pdev->dev, ionic);
> + }
> }
>
[...]
>
> +
> +/* Devcmd Interface */
> +u8 ionic_dev_cmd_status(struct ionic_dev *idev)
> +{
> + return ioread8(&idev->dev_cmd_regs->comp.comp.status);
> +}
> +
> +bool ionic_dev_cmd_done(struct ionic_dev *idev)
> +{
> + return ioread32(&idev->dev_cmd_regs->done) & DEV_CMD_DONE;
> +}
> +
> +void ionic_dev_cmd_comp(struct ionic_dev *idev, union dev_cmd_comp
> *comp)
> +{
> + memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp));
> +}
> +
> +void ionic_dev_cmd_go(struct ionic_dev *idev, union dev_cmd *cmd)
> +{
> + memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd));
> + iowrite32(0, &idev->dev_cmd_regs->done);
> + iowrite32(1, &idev->dev_cmd_regs->doorbell);
> +}
> +
> +/* Device commands */
> +void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver)
> +{
> + union dev_cmd cmd = {
> + .identify.opcode = CMD_OPCODE_IDENTIFY,
> + .identify.ver = ver,
> + };
> +
> + ionic_dev_cmd_go(idev, &cmd);
> +}
> +
> +void ionic_dev_cmd_init(struct ionic_dev *idev)
> +{
> + union dev_cmd cmd = {
> + .init.opcode = CMD_OPCODE_INIT,
> + .init.type = 0,
> + };
> +
> + ionic_dev_cmd_go(idev, &cmd);
> +}
> +
> +void ionic_dev_cmd_reset(struct ionic_dev *idev)
> +{
> + union dev_cmd cmd = {
> + .reset.opcode = CMD_OPCODE_RESET,
> + };
> +
> + ionic_dev_cmd_go(idev, &cmd);
> +}
[...]
> +int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long
> max_seconds)
> +{
> + struct ionic_dev *idev = &ionic->idev;
> + unsigned long max_wait, start_time, duration;
> + int opcode;
> + int done;
> + int err;
> +
> + WARN_ON(in_interrupt());
> +
> + /* Wait for dev cmd to complete, retrying if we get EAGAIN,
> + * but don't wait any longer than max_seconds.
> + */
> + max_wait = jiffies + (max_seconds * HZ);
> +try_again:
> + start_time = jiffies;
> + do {
> + done = ionic_dev_cmd_done(idev);
READ_ONCE required here ? to read from coherent memory modified
by the device and read by the driver ?
> + if (done)
> + break;
> + msleep(20);
> + } while (!done && time_before(jiffies, max_wait));
so your command interface is busy polling based, i am relating here to
Dave's comment regarding async command completion, is it possible to
have interrupt (MSIX?) based command completion in this hw ?
> + duration = jiffies - start_time;
> +
> + opcode = idev->dev_cmd_regs->cmd.cmd.opcode;
> + dev_dbg(ionic->dev, "DEVCMD %s (%d) done=%d took %ld secs (%ld
> jiffies)\n",
> + ionic_opcode_to_str(opcode), opcode,
> + done, duration / HZ, duration);
> +
> + if (!done && !time_before(jiffies, max_wait)) {
> + dev_warn(ionic->dev, "DEVCMD %s (%d) timeout after %ld
> secs\n",
> + ionic_opcode_to_str(opcode), opcode,
> max_seconds);
> + return -ETIMEDOUT;
> + }
> +
> + err = ionic_dev_cmd_status(&ionic->idev);
> + if (err) {
> + if (err == IONIC_RC_EAGAIN && !time_after(jiffies,
> max_wait)) {
> + dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s
> (%d) retrying...\n",
> + ionic_opcode_to_str(opcode), opcode,
> + ionic_error_to_str(err), err);
> +
> + msleep(1000);
> + iowrite32(0, &idev->dev_cmd_regs->done);
> + iowrite32(1, &idev->dev_cmd_regs->doorbell);
> + goto try_again;
> + }
> +
> + dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s (%d)
> failed\n",
> + ionic_opcode_to_str(opcode), opcode,
> + ionic_error_to_str(err), err);
> +
> + return ionic_error_to_errno(err);
> + }
> +
> + return 0;
> +}
> +
>
[...]
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands
2019-07-23 23:47 ` Saeed Mahameed
@ 2019-07-24 0:25 ` Shannon Nelson
2019-07-24 20:23 ` Shannon Nelson
0 siblings, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-24 0:25 UTC (permalink / raw)
To: Saeed Mahameed, netdev, davem
On 7/23/19 4:47 PM, Saeed Mahameed wrote:
> On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
>> The ionic device has a small set of PCI registers, including a
>> device control and data space, and a large set of message
>> commands.
>>
>> Signed-off-by: Shannon Nelson <snelson@pensando.io>
>> ---
>> drivers/net/ethernet/pensando/ionic/Makefile | 2 +-
>> drivers/net/ethernet/pensando/ionic/ionic.h | 20 +
>> .../net/ethernet/pensando/ionic/ionic_bus.h | 1 +
>> .../ethernet/pensando/ionic/ionic_bus_pci.c | 140 +-
>> .../ethernet/pensando/ionic/ionic_debugfs.c | 67 +
>> .../ethernet/pensando/ionic/ionic_debugfs.h | 28 +
>> .../net/ethernet/pensando/ionic/ionic_dev.c | 132 +
>> .../net/ethernet/pensando/ionic/ionic_dev.h | 144 +
>> .../net/ethernet/pensando/ionic/ionic_if.h | 2552
>> +++++++++++++++++
>> .../net/ethernet/pensando/ionic/ionic_main.c | 296 ++
>> .../net/ethernet/pensando/ionic/ionic_regs.h | 133 +
>> 11 files changed, 3512 insertions(+), 3 deletions(-)
>> create mode 100644
>> drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
>> create mode 100644
>> drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
>> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_dev.c
>> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_dev.h
>> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_if.h
>> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_regs.h
>>
> [...]
>
>> static void ionic_remove(struct pci_dev *pdev)
>> {
>> struct ionic *ionic = pci_get_drvdata(pdev);
>>
>> - devm_kfree(&pdev->dev, ionic);
>> + if (ionic) {
> nit, in case you are doing another re-spin maybe early return here:
> if (!ionic)
> return;
> //do stuff
Sure
>
>> + ionic_reset(ionic);
>> + ionic_dev_teardown(ionic);
>> + ionic_unmap_bars(ionic);
>> + pci_release_regions(pdev);
>> + pci_clear_master(pdev);
>> + pci_disable_sriov(pdev);
>> + pci_disable_device(pdev);
>> + ionic_debugfs_del_dev(ionic);
>> + mutex_destroy(&ionic->dev_cmd_lock);
>> +
>> + devm_kfree(&pdev->dev, ionic);
>> + }
>> }
>>
> [...]
>
>>
>> +
>> +/* Devcmd Interface */
>> +u8 ionic_dev_cmd_status(struct ionic_dev *idev)
>> +{
>> + return ioread8(&idev->dev_cmd_regs->comp.comp.status);
>> +}
>> +
>> +bool ionic_dev_cmd_done(struct ionic_dev *idev)
>> +{
>> + return ioread32(&idev->dev_cmd_regs->done) & DEV_CMD_DONE;
>> +}
>> +
>> +void ionic_dev_cmd_comp(struct ionic_dev *idev, union dev_cmd_comp
>> *comp)
>> +{
>> + memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp));
>> +}
>> +
>> +void ionic_dev_cmd_go(struct ionic_dev *idev, union dev_cmd *cmd)
>> +{
>> + memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd));
>> + iowrite32(0, &idev->dev_cmd_regs->done);
>> + iowrite32(1, &idev->dev_cmd_regs->doorbell);
>> +}
>> +
>> +/* Device commands */
>> +void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver)
>> +{
>> + union dev_cmd cmd = {
>> + .identify.opcode = CMD_OPCODE_IDENTIFY,
>> + .identify.ver = ver,
>> + };
>> +
>> + ionic_dev_cmd_go(idev, &cmd);
>> +}
>> +
>> +void ionic_dev_cmd_init(struct ionic_dev *idev)
>> +{
>> + union dev_cmd cmd = {
>> + .init.opcode = CMD_OPCODE_INIT,
>> + .init.type = 0,
>> + };
>> +
>> + ionic_dev_cmd_go(idev, &cmd);
>> +}
>> +
>> +void ionic_dev_cmd_reset(struct ionic_dev *idev)
>> +{
>> + union dev_cmd cmd = {
>> + .reset.opcode = CMD_OPCODE_RESET,
>> + };
>> +
>> + ionic_dev_cmd_go(idev, &cmd);
>> +}
> [...]
>
>> +int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long
>> max_seconds)
>> +{
>> + struct ionic_dev *idev = &ionic->idev;
>> + unsigned long max_wait, start_time, duration;
>> + int opcode;
>> + int done;
>> + int err;
>> +
>> + WARN_ON(in_interrupt());
>> +
>> + /* Wait for dev cmd to complete, retrying if we get EAGAIN,
>> + * but don't wait any longer than max_seconds.
>> + */
>> + max_wait = jiffies + (max_seconds * HZ);
>> +try_again:
>> + start_time = jiffies;
>> + do {
>> + done = ionic_dev_cmd_done(idev);
> READ_ONCE required here ? to read from coherent memory modified
> by the device and read by the driver ?
Good idea, I'll add that in.
>
>> + if (done)
>> + break;
>> + msleep(20);
>> + } while (!done && time_before(jiffies, max_wait));
> so your command interface is busy polling based, i am relating here to
> Dave's comment regarding async command completion, is it possible to
> have interrupt (MSIX?) based command completion in this hw ?
As I wrote elsewhere, this is only the low-level dev_cmd that does
polling; the adminq does a wait that is completed by an MSI-x handler.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands
2019-07-24 0:25 ` Shannon Nelson
@ 2019-07-24 20:23 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-24 20:23 UTC (permalink / raw)
To: Saeed Mahameed, netdev, davem
On 7/23/19 5:25 PM, Shannon Nelson wrote:
> On 7/23/19 4:47 PM, Saeed Mahameed wrote:
>> On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
>> +
>> + /* Wait for dev cmd to complete, retrying if we get EAGAIN,
>> + * but don't wait any longer than max_seconds.
>> + */
>> + max_wait = jiffies + (max_seconds * HZ);
>> +try_again:
>> + start_time = jiffies;
>> + do {
>> + done = ionic_dev_cmd_done(idev);
>> READ_ONCE required here ? to read from coherent memory modified
>> by the device and read by the driver ?
>
> Good idea, I'll add that in.
Looking closer at this, it is more for coordinating memory reads between
threads and irq handlers. This is polling a PCI register, which is
already marked as volatile and in at least some definitions (e.g. x86)
has a barrier.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 03/19] ionic: Add port management commands
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
2019-07-22 21:40 ` [PATCH v4 net-next 01/19] ionic: Add basic framework for IONIC Network device driver Shannon Nelson
2019-07-22 21:40 ` [PATCH v4 net-next 02/19] ionic: Add hardware init and device commands Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-22 21:40 ` [PATCH v4 net-next 04/19] ionic: Add basic lif support Shannon Nelson
` (15 subsequent siblings)
18 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
The port management commands apply to the physical port
associated with the PCI device, which might be shared among
several logical interfaces.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/ionic.h | 4 +
.../ethernet/pensando/ionic/ionic_bus_pci.c | 16 +++
.../net/ethernet/pensando/ionic/ionic_dev.c | 116 ++++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_dev.h | 15 +++
.../net/ethernet/pensando/ionic/ionic_main.c | 95 ++++++++++++++
5 files changed, 246 insertions(+)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
index 4fd0ae86556a..f77712feef5c 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -42,4 +42,8 @@ int ionic_identify(struct ionic *ionic);
int ionic_init(struct ionic *ionic);
int ionic_reset(struct ionic *ionic);
+int ionic_port_identify(struct ionic *ionic);
+int ionic_port_init(struct ionic *ionic);
+int ionic_port_reset(struct ionic *ionic);
+
#endif /* _IONIC_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
index 7eb23f0e87ac..7a41f8995c35 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -137,8 +137,23 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
goto err_out_teardown;
}
+ /* Configure the ports */
+ err = ionic_port_identify(ionic);
+ if (err) {
+ dev_err(dev, "Cannot identify port: %d, aborting\n", err);
+ goto err_out_reset;
+ }
+
+ err = ionic_port_init(ionic);
+ if (err) {
+ dev_err(dev, "Cannot init port: %d, aborting\n", err);
+ goto err_out_reset;
+ }
+
return 0;
+err_out_reset:
+ ionic_reset(ionic);
err_out_teardown:
ionic_dev_teardown(ionic);
err_out_unmap_bars:
@@ -162,6 +177,7 @@ static void ionic_remove(struct pci_dev *pdev)
struct ionic *ionic = pci_get_drvdata(pdev);
if (ionic) {
+ ionic_port_reset(ionic);
ionic_reset(ionic);
ionic_dev_teardown(ionic);
ionic_unmap_bars(ionic);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.c b/drivers/net/ethernet/pensando/ionic/ionic_dev.c
index ca2ef0a1f620..e2eda2bedac6 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_dev.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.c
@@ -130,3 +130,119 @@ void ionic_dev_cmd_reset(struct ionic_dev *idev)
ionic_dev_cmd_go(idev, &cmd);
}
+
+/* Port commands */
+void ionic_dev_cmd_port_identify(struct ionic_dev *idev)
+{
+ union dev_cmd cmd = {
+ .port_init.opcode = CMD_OPCODE_PORT_IDENTIFY,
+ .port_init.index = 0,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_port_init(struct ionic_dev *idev)
+{
+ union dev_cmd cmd = {
+ .port_init.opcode = CMD_OPCODE_PORT_INIT,
+ .port_init.index = 0,
+ .port_init.info_pa = cpu_to_le64(idev->port_info_pa),
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_port_reset(struct ionic_dev *idev)
+{
+ union dev_cmd cmd = {
+ .port_reset.opcode = CMD_OPCODE_PORT_RESET,
+ .port_reset.index = 0,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state)
+{
+ union dev_cmd cmd = {
+ .port_setattr.opcode = CMD_OPCODE_PORT_SETATTR,
+ .port_setattr.index = 0,
+ .port_setattr.attr = IONIC_PORT_ATTR_STATE,
+ .port_setattr.state = state,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed)
+{
+ union dev_cmd cmd = {
+ .port_setattr.opcode = CMD_OPCODE_PORT_SETATTR,
+ .port_setattr.index = 0,
+ .port_setattr.attr = IONIC_PORT_ATTR_SPEED,
+ .port_setattr.speed = cpu_to_le32(speed),
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_port_mtu(struct ionic_dev *idev, u32 mtu)
+{
+ union dev_cmd cmd = {
+ .port_setattr.opcode = CMD_OPCODE_PORT_SETATTR,
+ .port_setattr.index = 0,
+ .port_setattr.attr = IONIC_PORT_ATTR_MTU,
+ .port_setattr.mtu = cpu_to_le32(mtu),
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable)
+{
+ union dev_cmd cmd = {
+ .port_setattr.opcode = CMD_OPCODE_PORT_SETATTR,
+ .port_setattr.index = 0,
+ .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
+ .port_setattr.an_enable = an_enable,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type)
+{
+ union dev_cmd cmd = {
+ .port_setattr.opcode = CMD_OPCODE_PORT_SETATTR,
+ .port_setattr.index = 0,
+ .port_setattr.attr = IONIC_PORT_ATTR_FEC,
+ .port_setattr.fec_type = fec_type,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type)
+{
+ union dev_cmd cmd = {
+ .port_setattr.opcode = CMD_OPCODE_PORT_SETATTR,
+ .port_setattr.index = 0,
+ .port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
+ .port_setattr.pause_type = pause_type,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_port_loopback(struct ionic_dev *idev, u8 loopback_mode)
+{
+ union dev_cmd cmd = {
+ .port_setattr.opcode = CMD_OPCODE_PORT_SETATTR,
+ .port_setattr.index = 0,
+ .port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK,
+ .port_setattr.loopback_mode = loopback_mode,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
index 66afab3ee396..fe5e1b0e8d55 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_dev.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
@@ -123,6 +123,10 @@ struct ionic_dev {
struct ionic_intr __iomem *intr_ctrl;
u64 __iomem *intr_status;
+ struct port_info *port_info;
+ dma_addr_t port_info_pa;
+ u32 port_info_sz;
+
struct ionic_devinfo dev_info;
};
@@ -141,4 +145,15 @@ void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver);
void ionic_dev_cmd_init(struct ionic_dev *idev);
void ionic_dev_cmd_reset(struct ionic_dev *idev);
+void ionic_dev_cmd_port_identify(struct ionic_dev *idev);
+void ionic_dev_cmd_port_init(struct ionic_dev *idev);
+void ionic_dev_cmd_port_reset(struct ionic_dev *idev);
+void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state);
+void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed);
+void ionic_dev_cmd_port_mtu(struct ionic_dev *idev, u32 mtu);
+void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable);
+void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type);
+void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type);
+void ionic_dev_cmd_port_loopback(struct ionic_dev *idev, u8 loopback_mode);
+
#endif /* _IONIC_DEV_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_main.c b/drivers/net/ethernet/pensando/ionic/ionic_main.c
index 567ed259b398..78eab326b067 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_main.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_main.c
@@ -307,6 +307,101 @@ int ionic_reset(struct ionic *ionic)
return err;
}
+int ionic_port_identify(struct ionic *ionic)
+{
+ struct identity *ident = &ionic->ident;
+ struct ionic_dev *idev = &ionic->idev;
+ struct device *dev = ionic->dev;
+ size_t sz;
+ int err;
+
+ mutex_lock(&ionic->dev_cmd_lock);
+
+ ionic_dev_cmd_port_identify(idev);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ if (!err) {
+ sz = min(sizeof(ident->port), sizeof(idev->dev_cmd_regs->data));
+ memcpy_fromio(&ident->port, &idev->dev_cmd_regs->data, sz);
+ }
+
+ mutex_unlock(&ionic->dev_cmd_lock);
+
+ dev_dbg(dev, "speed %d\n", ident->port.config.speed);
+ dev_dbg(dev, "mtu %d\n", ident->port.config.mtu);
+ dev_dbg(dev, "state %d\n", ident->port.config.state);
+ dev_dbg(dev, "an_enable %d\n", ident->port.config.an_enable);
+ dev_dbg(dev, "fec_type %d\n", ident->port.config.fec_type);
+ dev_dbg(dev, "pause_type %d\n", ident->port.config.pause_type);
+ dev_dbg(dev, "loopback_mode %d\n", ident->port.config.loopback_mode);
+
+ return err;
+}
+
+int ionic_port_init(struct ionic *ionic)
+{
+ struct identity *ident = &ionic->ident;
+ struct ionic_dev *idev = &ionic->idev;
+ size_t sz;
+ int err;
+
+ if (idev->port_info)
+ return 0;
+
+ idev->port_info_sz = ALIGN(sizeof(*idev->port_info), PAGE_SIZE);
+ idev->port_info = dma_alloc_coherent(ionic->dev, idev->port_info_sz,
+ &idev->port_info_pa,
+ GFP_KERNEL);
+ if (!idev->port_info) {
+ dev_err(ionic->dev, "Failed to allocate port info, aborting\n");
+ return -ENOMEM;
+ }
+
+ sz = min(sizeof(ident->port.config), sizeof(idev->dev_cmd_regs->data));
+
+ mutex_lock(&ionic->dev_cmd_lock);
+
+ memcpy_toio(&idev->dev_cmd_regs->data, &ident->port.config, sz);
+ ionic_dev_cmd_port_init(idev);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+
+ ionic_dev_cmd_port_state(&ionic->idev, PORT_ADMIN_STATE_UP);
+ (void)ionic_dev_cmd_wait(ionic, devcmd_timeout);
+
+ mutex_unlock(&ionic->dev_cmd_lock);
+ if (err) {
+ dev_err(ionic->dev, "Failed to init port\n");
+ return err;
+ }
+
+ return 0;
+}
+
+int ionic_port_reset(struct ionic *ionic)
+{
+ struct ionic_dev *idev = &ionic->idev;
+ int err;
+
+ if (!idev->port_info)
+ return 0;
+
+ mutex_lock(&ionic->dev_cmd_lock);
+ ionic_dev_cmd_port_reset(idev);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ mutex_unlock(&ionic->dev_cmd_lock);
+ if (err) {
+ dev_err(ionic->dev, "Failed to reset port\n");
+ return err;
+ }
+
+ dma_free_coherent(ionic->dev, idev->port_info_sz,
+ idev->port_info, idev->port_info_pa);
+
+ idev->port_info = NULL;
+ idev->port_info_pa = 0;
+
+ return err;
+}
+
static int __init ionic_init_module(void)
{
ionic_struct_size_checks();
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* [PATCH v4 net-next 04/19] ionic: Add basic lif support
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (2 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 03/19] ionic: Add port management commands Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-22 21:40 ` [PATCH v4 net-next 05/19] ionic: Add interrupts and doorbells Shannon Nelson
` (14 subsequent siblings)
18 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
The LIF is the Logical Interface, which represents the external
connections. The NIC can multiplex many LIFs to a single port,
but in most setups, LIF0 is the primary control for the port.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/Makefile | 3 +-
drivers/net/ethernet/pensando/ionic/ionic.h | 8 +-
.../net/ethernet/pensando/ionic/ionic_bus.h | 2 +
.../ethernet/pensando/ionic/ionic_bus_pci.c | 48 +++
.../ethernet/pensando/ionic/ionic_debugfs.c | 47 +++
.../ethernet/pensando/ionic/ionic_debugfs.h | 6 +
.../net/ethernet/pensando/ionic/ionic_dev.c | 34 ++
.../net/ethernet/pensando/ionic/ionic_dev.h | 7 +
.../net/ethernet/pensando/ionic/ionic_lif.c | 292 ++++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_lif.h | 70 +++++
.../net/ethernet/pensando/ionic/ionic_main.c | 1 +
11 files changed, 516 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_lif.c
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_lif.h
diff --git a/drivers/net/ethernet/pensando/ionic/Makefile b/drivers/net/ethernet/pensando/ionic/Makefile
index 49a8e28a5c84..04d519d00be6 100644
--- a/drivers/net/ethernet/pensando/ionic/Makefile
+++ b/drivers/net/ethernet/pensando/ionic/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_IONIC) := ionic.o
-ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_debugfs.o
+ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_debugfs.o \
+ ionic_lif.o
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
index f77712feef5c..afff2e074f1a 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -6,7 +6,6 @@
#include "ionic_if.h"
#include "ionic_dev.h"
-#include "ionic_debugfs.h"
#define DRV_NAME "ionic"
#define DRV_DESCRIPTION "Pensando Ethernet NIC Driver"
@@ -32,6 +31,13 @@ struct ionic {
struct ionic_dev_bar bars[IONIC_BARS_MAX];
unsigned int num_bars;
struct identity ident;
+ struct list_head lifs;
+ unsigned int nnqs_per_lif;
+ unsigned int neqs_per_lif;
+ unsigned int ntxqs_per_lif;
+ unsigned int nrxqs_per_lif;
+ DECLARE_BITMAP(lifbits, IONIC_LIFS_MAX);
+ unsigned int nintrs;
};
int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_wait);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus.h b/drivers/net/ethernet/pensando/ionic/ionic_bus.h
index 24b4c01ec03f..3b1e2d0ebf8f 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus.h
@@ -5,6 +5,8 @@
#define _IONIC_BUS_H_
const char *ionic_bus_info(struct ionic *ionic);
+int ionic_bus_alloc_irq_vectors(struct ionic *ionic, unsigned int nintrs);
+void ionic_bus_free_irq_vectors(struct ionic *ionic);
int ionic_bus_register_driver(void);
void ionic_bus_unregister_driver(void);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
index 7a41f8995c35..0ed724efe117 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -8,6 +8,8 @@
#include "ionic.h"
#include "ionic_bus.h"
+#include "ionic_lif.h"
+#include "ionic_debugfs.h"
/* Supported devices */
static const struct pci_device_id ionic_id_table[] = {
@@ -22,6 +24,17 @@ const char *ionic_bus_info(struct ionic *ionic)
return pci_name(ionic->pdev);
}
+int ionic_bus_alloc_irq_vectors(struct ionic *ionic, unsigned int nintrs)
+{
+ return pci_alloc_irq_vectors(ionic->pdev, nintrs, nintrs,
+ PCI_IRQ_MSIX);
+}
+
+void ionic_bus_free_irq_vectors(struct ionic *ionic)
+{
+ pci_free_irq_vectors(ionic->pdev);
+}
+
static int ionic_map_bars(struct ionic *ionic)
{
struct pci_dev *pdev = ionic->pdev;
@@ -150,8 +163,40 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
goto err_out_reset;
}
+ /* Configure LIFs */
+ err = ionic_lif_identify(ionic, IONIC_LIF_TYPE_CLASSIC,
+ &ionic->ident.lif);
+ if (err) {
+ dev_err(dev, "Cannot identify LIFs: %d, aborting\n", err);
+ goto err_out_port_reset;
+ }
+
+ err = ionic_lifs_size(ionic);
+ if (err) {
+ dev_err(dev, "Cannot size LIFs: %d, aborting\n", err);
+ goto err_out_port_reset;
+ }
+
+ err = ionic_lifs_alloc(ionic);
+ if (err) {
+ dev_err(dev, "Cannot allocate LIFs: %d, aborting\n", err);
+ goto err_out_free_irqs;
+ }
+
+ err = ionic_lifs_init(ionic);
+ if (err) {
+ dev_err(dev, "Cannot init LIFs: %d, aborting\n", err);
+ goto err_out_free_lifs;
+ }
+
return 0;
+err_out_free_lifs:
+ ionic_lifs_free(ionic);
+err_out_free_irqs:
+ ionic_bus_free_irq_vectors(ionic);
+err_out_port_reset:
+ ionic_port_reset(ionic);
err_out_reset:
ionic_reset(ionic);
err_out_teardown:
@@ -177,6 +222,9 @@ static void ionic_remove(struct pci_dev *pdev)
struct ionic *ionic = pci_get_drvdata(pdev);
if (ionic) {
+ ionic_lifs_deinit(ionic);
+ ionic_lifs_free(ionic);
+ ionic_bus_free_irq_vectors(ionic);
ionic_port_reset(ionic);
ionic_reset(ionic);
ionic_dev_teardown(ionic);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
index c33a8bfcbcd4..a2a566695f63 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
@@ -1,10 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+#include <linux/pci.h>
#include <linux/netdevice.h>
#include "ionic.h"
#include "ionic_bus.h"
+#include "ionic_lif.h"
#include "ionic_debugfs.h"
#ifdef CONFIG_DEBUG_FS
@@ -64,4 +66,49 @@ int ionic_debugfs_add_ident(struct ionic *ionic)
ionic, &identity_fops) ? 0 : -ENOTSUPP;
}
+int ionic_debugfs_add_sizes(struct ionic *ionic)
+{
+ debugfs_create_u32("nlifs", 0400, ionic->dentry,
+ (u32 *)&ionic->ident.dev.nlifs);
+ debugfs_create_u32("nintrs", 0400, ionic->dentry, &ionic->nintrs);
+
+ debugfs_create_u32("ntxqs_per_lif", 0400, ionic->dentry,
+ (u32 *)&ionic->ident.lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);
+ debugfs_create_u32("nrxqs_per_lif", 0400, ionic->dentry,
+ (u32 *)&ionic->ident.lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);
+
+ return 0;
+}
+
+static int netdev_show(struct seq_file *seq, void *v)
+{
+ struct net_device *netdev = seq->private;
+
+ seq_printf(seq, "%s\n", netdev->name);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(netdev);
+
+int ionic_debugfs_add_lif(struct lif *lif)
+{
+ struct dentry *netdev_dentry;
+
+ lif->dentry = debugfs_create_dir(lif->name, lif->ionic->dentry);
+ if (IS_ERR_OR_NULL(lif->dentry))
+ return PTR_ERR(lif->dentry);
+
+ netdev_dentry = debugfs_create_file("netdev", 0400, lif->dentry,
+ lif->netdev, &netdev_fops);
+ if (IS_ERR_OR_NULL(netdev_dentry))
+ return PTR_ERR(netdev_dentry);
+
+ return 0;
+}
+
+void ionic_debugfs_del_lif(struct lif *lif)
+{
+ debugfs_remove_recursive(lif->dentry);
+ lif->dentry = NULL;
+}
#endif
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
index c3958b0c15b1..cb00166e7c30 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
@@ -15,6 +15,9 @@ void ionic_debugfs_del_dev(struct ionic *ionic);
int ionic_debugfs_add_bars(struct ionic *ionic);
int ionic_debugfs_add_dev_cmd(struct ionic *ionic);
int ionic_debugfs_add_ident(struct ionic *ionic);
+int ionic_debugfs_add_sizes(struct ionic *ionic);
+int ionic_debugfs_add_lif(struct lif *lif);
+void ionic_debugfs_del_lif(struct lif *lif);
#else
static inline void ionic_debugfs_create(void) { }
static inline void ionic_debugfs_destroy(void) { }
@@ -23,6 +26,9 @@ static inline void ionic_debugfs_del_dev(struct ionic *ionic) { }
static inline int ionic_debugfs_add_bars(struct ionic *ionic) { return 0; }
static inline int ionic_debugfs_add_dev_cmd(struct ionic *ionic) { return 0; }
static inline int ionic_debugfs_add_ident(struct ionic *ionic) { return 0; }
+static inline int ionic_debugfs_add_sizes(struct ionic *ionic) { return 0; }
+static inline int ionic_debugfs_add_lif(struct lif *lif) { return 0; }
+static inline void ionic_debugfs_del_lif(struct lif *lif) { return 0; }
#endif
#endif /* _IONIC_DEBUGFS_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.c b/drivers/net/ethernet/pensando/ionic/ionic_dev.c
index e2eda2bedac6..59d863e45072 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_dev.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.c
@@ -246,3 +246,37 @@ void ionic_dev_cmd_port_loopback(struct ionic_dev *idev, u8 loopback_mode)
ionic_dev_cmd_go(idev, &cmd);
}
+
+/* LIF commands */
+void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver)
+{
+ union dev_cmd cmd = {
+ .lif_identify.opcode = CMD_OPCODE_LIF_IDENTIFY,
+ .lif_identify.type = type,
+ .lif_identify.ver = ver,
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
+ dma_addr_t info_pa)
+{
+ union dev_cmd cmd = {
+ .lif_init.opcode = CMD_OPCODE_LIF_INIT,
+ .lif_init.index = cpu_to_le16(lif_index),
+ .lif_init.info_pa = cpu_to_le64(info_pa),
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
+void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index)
+{
+ union dev_cmd cmd = {
+ .lif_init.opcode = CMD_OPCODE_LIF_RESET,
+ .lif_init.index = cpu_to_le16(lif_index),
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
index fe5e1b0e8d55..a8a84734b433 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_dev.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
@@ -10,6 +10,8 @@
#include "ionic_if.h"
#include "ionic_regs.h"
+#define IONIC_LIFS_MAX 1024
+
struct ionic_dev_bar {
void __iomem *vaddr;
phys_addr_t bus_addr;
@@ -156,4 +158,9 @@ void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type);
void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type);
void ionic_dev_cmd_port_loopback(struct ionic_dev *idev, u8 loopback_mode);
+void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver);
+void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
+ dma_addr_t addr);
+void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index);
+
#endif /* _IONIC_DEV_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
new file mode 100644
index 000000000000..e32ce2a3d0ce
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/cpumask.h>
+
+#include "ionic.h"
+#include "ionic_bus.h"
+#include "ionic_lif.h"
+#include "ionic_debugfs.h"
+
+static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
+{
+ struct device *dev = ionic->dev;
+ struct net_device *netdev;
+ struct lif *lif;
+ int err;
+
+ netdev = alloc_etherdev_mqs(sizeof(*lif),
+ ionic->ntxqs_per_lif, ionic->ntxqs_per_lif);
+ if (!netdev) {
+ dev_err(dev, "Cannot allocate netdev, aborting\n");
+ return ERR_PTR(-ENOMEM);
+ }
+ netif_set_real_num_tx_queues(netdev, ionic->ntxqs_per_lif);
+ netif_set_real_num_rx_queues(netdev, ionic->nrxqs_per_lif);
+
+ SET_NETDEV_DEV(netdev, dev);
+
+ lif = netdev_priv(netdev);
+ lif->netdev = netdev;
+
+ lif->neqs = ionic->neqs_per_lif;
+ lif->nxqs = ionic->ntxqs_per_lif;
+
+ lif->ionic = ionic;
+ lif->index = index;
+
+ snprintf(lif->name, sizeof(lif->name), "lif%u", index);
+
+ /* allocate lif info */
+ lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
+ lif->info = dma_alloc_coherent(dev, lif->info_sz,
+ &lif->info_pa, GFP_KERNEL);
+ if (!lif->info) {
+ dev_err(dev, "Failed to allocate lif info, aborting\n");
+ err = -ENOMEM;
+ goto err_out_free_netdev;
+ }
+
+ list_add_tail(&lif->list, &ionic->lifs);
+
+ return lif;
+
+err_out_free_netdev:
+ free_netdev(lif->netdev);
+ lif = NULL;
+
+ return ERR_PTR(err);
+}
+
+int ionic_lifs_alloc(struct ionic *ionic)
+{
+ struct lif *lif;
+
+ INIT_LIST_HEAD(&ionic->lifs);
+
+ /* only build the first lif, others are for later features */
+ set_bit(0, ionic->lifbits);
+ lif = ionic_lif_alloc(ionic, 0);
+
+ return PTR_ERR_OR_ZERO(lif);
+}
+
+static void ionic_lif_reset(struct lif *lif)
+{
+ struct ionic_dev *idev = &lif->ionic->idev;
+
+ mutex_lock(&lif->ionic->dev_cmd_lock);
+ ionic_dev_cmd_lif_reset(idev, lif->index);
+ ionic_dev_cmd_wait(lif->ionic, devcmd_timeout);
+ mutex_unlock(&lif->ionic->dev_cmd_lock);
+}
+
+static void ionic_lif_free(struct lif *lif)
+{
+ struct device *dev = lif->ionic->dev;
+
+ ionic_lif_reset(lif);
+
+ /* free lif info */
+ dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
+ lif->info = NULL;
+ lif->info_pa = 0;
+
+ /* free netdev & lif */
+ ionic_debugfs_del_lif(lif);
+ list_del(&lif->list);
+ free_netdev(lif->netdev);
+}
+
+void ionic_lifs_free(struct ionic *ionic)
+{
+ struct list_head *cur, *tmp;
+ struct lif *lif;
+
+ list_for_each_safe(cur, tmp, &ionic->lifs) {
+ lif = list_entry(cur, struct lif, list);
+
+ ionic_lif_free(lif);
+ }
+}
+
+static void ionic_lif_deinit(struct lif *lif)
+{
+ if (!test_bit(LIF_INITED, lif->state))
+ return;
+
+ clear_bit(LIF_INITED, lif->state);
+
+ ionic_lif_reset(lif);
+}
+
+void ionic_lifs_deinit(struct ionic *ionic)
+{
+ struct list_head *cur, *tmp;
+ struct lif *lif;
+
+ list_for_each_safe(cur, tmp, &ionic->lifs) {
+ lif = list_entry(cur, struct lif, list);
+ ionic_lif_deinit(lif);
+ }
+}
+
+static int ionic_lif_init(struct lif *lif)
+{
+ struct ionic_dev *idev = &lif->ionic->idev;
+ struct lif_init_comp comp;
+ int err;
+
+ ionic_debugfs_add_lif(lif);
+
+ mutex_lock(&lif->ionic->dev_cmd_lock);
+ ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa);
+ err = ionic_dev_cmd_wait(lif->ionic, devcmd_timeout);
+ ionic_dev_cmd_comp(idev, (union dev_cmd_comp *)&comp);
+ mutex_unlock(&lif->ionic->dev_cmd_lock);
+ if (err)
+ return err;
+
+ lif->hw_index = le16_to_cpu(comp.hw_index);
+
+ set_bit(LIF_INITED, lif->state);
+
+ return 0;
+}
+
+int ionic_lifs_init(struct ionic *ionic)
+{
+ struct list_head *cur, *tmp;
+ struct lif *lif;
+ int err;
+
+ list_for_each_safe(cur, tmp, &ionic->lifs) {
+ lif = list_entry(cur, struct lif, list);
+ err = ionic_lif_init(lif);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
+ union lif_identity *lid)
+{
+ struct ionic_dev *idev = &ionic->idev;
+ size_t sz;
+ int err;
+
+ sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data));
+
+ mutex_lock(&ionic->dev_cmd_lock);
+ ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz);
+ mutex_unlock(&ionic->dev_cmd_lock);
+ if (err)
+ return (err);
+
+ dev_dbg(ionic->dev, "capabilities 0x%llx\n",
+ le64_to_cpu(lid->capabilities));
+
+ dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n",
+ le32_to_cpu(lid->eth.max_ucast_filters));
+ dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n",
+ le32_to_cpu(lid->eth.max_mcast_filters));
+ dev_dbg(ionic->dev, "eth.features 0x%llx\n",
+ le64_to_cpu(lid->eth.config.features));
+ dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n",
+ le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ]));
+ dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n",
+ le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]));
+ dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n",
+ le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ]));
+ dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n",
+ le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ]));
+ dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name);
+ dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac);
+ dev_dbg(ionic->dev, "eth.config.mtu %d\n",
+ le32_to_cpu(lid->eth.config.mtu));
+
+ return 0;
+}
+
+int ionic_lifs_size(struct ionic *ionic)
+{
+ struct identity *ident = &ionic->ident;
+ union lif_config *lc = &ident->lif.eth.config;
+ unsigned int nintrs, dev_nintrs;
+ unsigned int ntxqs_per_lif;
+ unsigned int nrxqs_per_lif;
+ unsigned int neqs_per_lif;
+ unsigned int nnqs_per_lif;
+ unsigned int nxqs, neqs;
+ unsigned int min_intrs;
+ int err;
+
+ dev_nintrs = le32_to_cpu(ident->dev.nintrs);
+ neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count);
+ nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]);
+ ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]);
+ nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]);
+
+ nxqs = min(ntxqs_per_lif, nrxqs_per_lif);
+ nxqs = min(nxqs, num_online_cpus());
+ neqs = min(neqs_per_lif, num_online_cpus());
+
+try_again:
+ /* interrupt usage:
+ * 1 for master lif adminq/notifyq
+ * 1 for each CPU for master lif TxRx queue pairs
+ * whatever's left is for RDMA queues
+ */
+ nintrs = 1 + nxqs + neqs;
+ min_intrs = 2; /* adminq + 1 TxRx queue pair */
+
+ if (nintrs > dev_nintrs)
+ goto try_fewer;
+
+ err = ionic_bus_alloc_irq_vectors(ionic, nintrs);
+ if (err < 0 && err != -ENOSPC) {
+ dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err);
+ return err;
+ }
+ if (err == -ENOSPC)
+ goto try_fewer;
+
+ if (err != nintrs) {
+ ionic_bus_free_irq_vectors(ionic);
+ goto try_fewer;
+ }
+
+ ionic->nnqs_per_lif = nnqs_per_lif;
+ ionic->neqs_per_lif = neqs;
+ ionic->ntxqs_per_lif = nxqs;
+ ionic->nrxqs_per_lif = nxqs;
+ ionic->nintrs = nintrs;
+
+ ionic_debugfs_add_sizes(ionic);
+
+ return 0;
+
+try_fewer:
+ if (nnqs_per_lif > 1) {
+ nnqs_per_lif >>= 1;
+ goto try_again;
+ }
+ if (neqs > 1) {
+ neqs >>= 1;
+ goto try_again;
+ }
+ if (nxqs > 1) {
+ nxqs >>= 1;
+ goto try_again;
+ }
+ dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs);
+ return -ENOSPC;
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
new file mode 100644
index 000000000000..37f79d36744a
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#ifndef _IONIC_LIF_H_
+#define _IONIC_LIF_H_
+
+#include <linux/pci.h>
+
+enum lif_state_flags {
+ LIF_INITED,
+
+ /* leave this as last */
+ LIF_STATE_SIZE
+};
+
+#define LIF_NAME_MAX_SZ (32)
+struct lif {
+ char name[LIF_NAME_MAX_SZ];
+ struct list_head list;
+ struct net_device *netdev;
+ DECLARE_BITMAP(state, LIF_STATE_SIZE);
+ struct ionic *ionic;
+ bool registered;
+ unsigned int index;
+ unsigned int hw_index;
+ unsigned int neqs;
+ unsigned int nxqs;
+
+ struct lif_info *info;
+ dma_addr_t info_pa;
+ u32 info_sz;
+
+ struct dentry *dentry;
+ u32 flags;
+};
+
+static inline bool ionic_is_pf(struct ionic *ionic)
+{
+ return ionic->pdev &&
+ ionic->pdev->device == PCI_DEVICE_ID_PENSANDO_IONIC_ETH_PF;
+}
+
+static inline bool ionic_is_vf(struct ionic *ionic)
+{
+ return ionic->pdev &&
+ ionic->pdev->device == PCI_DEVICE_ID_PENSANDO_IONIC_ETH_VF;
+}
+
+static inline bool ionic_is_25g(struct ionic *ionic)
+{
+ return ionic_is_pf(ionic) &&
+ ionic->pdev->subsystem_device == IONIC_SUBDEV_ID_NAPLES_25;
+}
+
+static inline bool ionic_is_100g(struct ionic *ionic)
+{
+ return ionic_is_pf(ionic) &&
+ (ionic->pdev->subsystem_device == IONIC_SUBDEV_ID_NAPLES_100_4 ||
+ ionic->pdev->subsystem_device == IONIC_SUBDEV_ID_NAPLES_100_8);
+}
+
+int ionic_lifs_alloc(struct ionic *ionic);
+void ionic_lifs_free(struct ionic *ionic);
+void ionic_lifs_deinit(struct ionic *ionic);
+int ionic_lifs_init(struct ionic *ionic);
+int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
+ union lif_identity *lif_ident);
+int ionic_lifs_size(struct ionic *ionic);
+
+#endif /* _IONIC_LIF_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_main.c b/drivers/net/ethernet/pensando/ionic/ionic_main.c
index 78eab326b067..b732e7345550 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_main.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_main.c
@@ -8,6 +8,7 @@
#include "ionic.h"
#include "ionic_bus.h"
+#include "ionic_lif.h"
#include "ionic_debugfs.h"
MODULE_DESCRIPTION(DRV_DESCRIPTION);
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* [PATCH v4 net-next 05/19] ionic: Add interrupts and doorbells
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (3 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 04/19] ionic: Add basic lif support Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-23 21:24 ` David Miller
2019-07-22 21:40 ` [PATCH v4 net-next 06/19] ionic: Add basic adminq support Shannon Nelson
` (13 subsequent siblings)
18 siblings, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
The ionic interrupt model is based on interrupt control blocks
accessed through the PCI BAR. Doorbell registers are used by
the driver to signal to the NIC that requests are waiting on
the message queues. Interrupts are used by the NIC to signal
to the driver that answers are waiting on the completion queues.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/ionic.h | 3 +
.../net/ethernet/pensando/ionic/ionic_bus.h | 2 +
.../ethernet/pensando/ionic/ionic_bus_pci.c | 12 ++++
.../net/ethernet/pensando/ionic/ionic_dev.c | 6 ++
.../net/ethernet/pensando/ionic/ionic_dev.h | 21 ++++++
.../net/ethernet/pensando/ionic/ionic_lif.c | 64 +++++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_lif.h | 4 ++
7 files changed, 112 insertions(+)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
index afff2e074f1a..c86a08752b3b 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -4,6 +4,8 @@
#ifndef _IONIC_H_
#define _IONIC_H_
+struct lif;
+
#include "ionic_if.h"
#include "ionic_dev.h"
@@ -38,6 +40,7 @@ struct ionic {
unsigned int nrxqs_per_lif;
DECLARE_BITMAP(lifbits, IONIC_LIFS_MAX);
unsigned int nintrs;
+ DECLARE_BITMAP(intrs, INTR_CTRL_REGS_MAX);
};
int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_wait);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus.h b/drivers/net/ethernet/pensando/ionic/ionic_bus.h
index 3b1e2d0ebf8f..6b29e94f81d6 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus.h
@@ -9,5 +9,7 @@ int ionic_bus_alloc_irq_vectors(struct ionic *ionic, unsigned int nintrs);
void ionic_bus_free_irq_vectors(struct ionic *ionic);
int ionic_bus_register_driver(void);
void ionic_bus_unregister_driver(void);
+void __iomem *ionic_bus_map_dbpage(struct ionic *ionic, int page_num);
+void ionic_bus_unmap_dbpage(struct ionic *ionic, void __iomem *page);
#endif /* _IONIC_BUS_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
index 0ed724efe117..838d7c423b2c 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -87,6 +87,18 @@ static void ionic_unmap_bars(struct ionic *ionic)
}
}
+void __iomem *ionic_bus_map_dbpage(struct ionic *ionic, int page_num)
+{
+ return pci_iomap_range(ionic->pdev,
+ ionic->bars[IONIC_PCI_BAR_DBELL].res_index,
+ (u64)page_num << PAGE_SHIFT, PAGE_SIZE);
+}
+
+void ionic_bus_unmap_dbpage(struct ionic *ionic, void __iomem *page)
+{
+ iounmap(page);
+}
+
static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct device *dev = &pdev->dev;
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.c b/drivers/net/ethernet/pensando/ionic/ionic_dev.c
index 59d863e45072..c0710bf200a5 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_dev.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.c
@@ -9,6 +9,7 @@
#include <linux/etherdevice.h>
#include "ionic.h"
#include "ionic_dev.h"
+#include "ionic_lif.h"
void ionic_init_devinfo(struct ionic_dev *idev)
{
@@ -280,3 +281,8 @@ void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index)
ionic_dev_cmd_go(idev, &cmd);
}
+
+int ionic_db_page_num(struct lif *lif, int pid)
+{
+ return (lif->hw_index * lif->dbid_count) + pid;
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
index a8a84734b433..6d30adeab8c5 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_dev.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
@@ -132,8 +132,27 @@ struct ionic_dev {
struct ionic_devinfo dev_info;
};
+#define INTR_INDEX_NOT_ASSIGNED -1
+#define INTR_NAME_MAX_SZ 32
+
+struct intr {
+ char name[INTR_NAME_MAX_SZ];
+ unsigned int index;
+ unsigned int vector;
+ u64 rearm_count;
+ unsigned int cpu;
+ cpumask_t affinity_mask;
+};
+
struct ionic;
+static inline void ionic_intr_init(struct ionic_dev *idev, struct intr *intr,
+ unsigned long index)
+{
+ ionic_intr_clean(idev->intr_ctrl, index);
+ intr->index = index;
+}
+
void ionic_init_devinfo(struct ionic_dev *idev);
int ionic_dev_setup(struct ionic *ionic);
void ionic_dev_teardown(struct ionic *ionic);
@@ -163,4 +182,6 @@ void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
dma_addr_t addr);
void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index);
+int ionic_db_page_num(struct lif *lif, int pid);
+
#endif /* _IONIC_DEV_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index e32ce2a3d0ce..65ced9b469c9 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -12,6 +12,30 @@
#include "ionic_lif.h"
#include "ionic_debugfs.h"
+static int ionic_intr_alloc(struct lif *lif, struct intr *intr)
+{
+ struct ionic *ionic = lif->ionic;
+ int index;
+
+ index = find_first_zero_bit(ionic->intrs, ionic->nintrs);
+ if (index == ionic->nintrs) {
+ netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n",
+ __func__, index, ionic->nintrs);
+ return -ENOSPC;
+ }
+
+ set_bit(index, ionic->intrs);
+ ionic_intr_init(&ionic->idev, intr, index);
+
+ return 0;
+}
+
+static void ionic_intr_free(struct lif *lif, int index)
+{
+ if (index != INTR_INDEX_NOT_ASSIGNED && index < lif->ionic->nintrs)
+ clear_bit(index, lif->ionic->intrs);
+}
+
static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
{
struct device *dev = ionic->dev;
@@ -96,6 +120,12 @@ static void ionic_lif_free(struct lif *lif)
lif->info = NULL;
lif->info_pa = 0;
+ /* unmap doorbell page */
+ ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
+ lif->kern_dbpage = NULL;
+ kfree(lif->dbid_inuse);
+ lif->dbid_inuse = NULL;
+
/* free netdev & lif */
ionic_debugfs_del_lif(lif);
list_del(&lif->list);
@@ -138,7 +168,9 @@ void ionic_lifs_deinit(struct ionic *ionic)
static int ionic_lif_init(struct lif *lif)
{
struct ionic_dev *idev = &lif->ionic->idev;
+ struct device *dev = lif->ionic->dev;
struct lif_init_comp comp;
+ int dbpage_num;
int err;
ionic_debugfs_add_lif(lif);
@@ -153,9 +185,41 @@ static int ionic_lif_init(struct lif *lif)
lif->hw_index = le16_to_cpu(comp.hw_index);
+ /* now that we have the hw_index we can figure out our doorbell page */
+ lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif);
+ if (!lif->dbid_count) {
+ dev_err(dev, "No doorbell pages, aborting\n");
+ return -EINVAL;
+ }
+
+ lif->dbid_inuse = kzalloc(BITS_TO_LONGS(lif->dbid_count) * sizeof(long),
+ GFP_KERNEL);
+ if (!lif->dbid_inuse) {
+ dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n");
+ return -ENOMEM;
+ }
+
+ /* first doorbell id reserved for kernel (dbid aka pid == zero) */
+ set_bit(0, lif->dbid_inuse);
+ lif->kern_pid = 0;
+
+ dbpage_num = ionic_db_page_num(lif, lif->kern_pid);
+ lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num);
+ if (!lif->kern_dbpage) {
+ dev_err(dev, "Cannot map dbpage, aborting\n");
+ err = -ENOMEM;
+ goto err_out_free_dbid;
+ }
+
set_bit(LIF_INITED, lif->state);
return 0;
+
+err_out_free_dbid:
+ kfree(lif->dbid_inuse);
+ lif->dbid_inuse = NULL;
+
+ return err;
}
int ionic_lifs_init(struct ionic *ionic)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index 37f79d36744a..98d0699234e9 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -23,6 +23,8 @@ struct lif {
bool registered;
unsigned int index;
unsigned int hw_index;
+ unsigned int kern_pid;
+ u64 __iomem *kern_dbpage;
unsigned int neqs;
unsigned int nxqs;
@@ -30,6 +32,8 @@ struct lif {
dma_addr_t info_pa;
u32 info_sz;
+ unsigned long *dbid_inuse;
+ unsigned int dbid_count;
struct dentry *dentry;
u32 flags;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 05/19] ionic: Add interrupts and doorbells
2019-07-22 21:40 ` [PATCH v4 net-next 05/19] ionic: Add interrupts and doorbells Shannon Nelson
@ 2019-07-23 21:24 ` David Miller
2019-07-23 22:50 ` Shannon Nelson
0 siblings, 1 reply; 69+ messages in thread
From: David Miller @ 2019-07-23 21:24 UTC (permalink / raw)
To: snelson; +Cc: netdev
From: Shannon Nelson <snelson@pensando.io>
Date: Mon, 22 Jul 2019 14:40:09 -0700
> The ionic interrupt model is based on interrupt control blocks
> accessed through the PCI BAR. Doorbell registers are used by
> the driver to signal to the NIC that requests are waiting on
> the message queues. Interrupts are used by the NIC to signal
> to the driver that answers are waiting on the completion queues.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
After applying this patch we get a warning:
drivers/net/ethernet/pensando/ionic/ionic_lif.c:33:13: warning: ‘ionic_intr_free’ defined but not used [-Wunused-function]
static void ionic_intr_free(struct lif *lif, int index)
^~~~~~~~~~~~~~~
drivers/net/ethernet/pensando/ionic/ionic_lif.c:15:12: warning: ‘ionic_intr_alloc’ defined but not used [-Wunused-function]
static int ionic_intr_alloc(struct lif *lif, struct intr *intr)
^~~~~~~~~~~~~~~~
Also:
> + lif->dbid_inuse = kzalloc(BITS_TO_LONGS(lif->dbid_count) * sizeof(long),
> + GFP_KERNEL);
You can use bitmap_alloc() and friends from linux/bitmap.h for this kind of stuff.
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 05/19] ionic: Add interrupts and doorbells
2019-07-23 21:24 ` David Miller
@ 2019-07-23 22:50 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-23 22:50 UTC (permalink / raw)
To: David Miller; +Cc: netdev
On 7/23/19 2:24 PM, David Miller wrote:
> From: Shannon Nelson <snelson@pensando.io>
> Date: Mon, 22 Jul 2019 14:40:09 -0700
>
>> The ionic interrupt model is based on interrupt control blocks
>> accessed through the PCI BAR. Doorbell registers are used by
>> the driver to signal to the NIC that requests are waiting on
>> the message queues. Interrupts are used by the NIC to signal
>> to the driver that answers are waiting on the completion queues.
>>
>> Signed-off-by: Shannon Nelson <snelson@pensando.io>
> After applying this patch we get a warning:
>
> drivers/net/ethernet/pensando/ionic/ionic_lif.c:33:13: warning: ‘ionic_intr_free’ defined but not used [-Wunused-function]
> static void ionic_intr_free(struct lif *lif, int index)
> ^~~~~~~~~~~~~~~
> drivers/net/ethernet/pensando/ionic/ionic_lif.c:15:12: warning: ‘ionic_intr_alloc’ defined but not used [-Wunused-function]
> static int ionic_intr_alloc(struct lif *lif, struct intr *intr)
> ^~~~~~~~~~~~~~~~
Yes, and they get used in the next patch. This is so I can keep similar
bits of functionality together in one patch and to keep the next patch a
little smaller.
> Also:
>
>> + lif->dbid_inuse = kzalloc(BITS_TO_LONGS(lif->dbid_count) * sizeof(long),
>> + GFP_KERNEL);
> You can use bitmap_alloc() and friends from linux/bitmap.h for this kind of stuff.
Sure.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 06/19] ionic: Add basic adminq support
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (4 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 05/19] ionic: Add interrupts and doorbells Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-23 21:27 ` David Miller
2019-07-22 21:40 ` [PATCH v4 net-next 07/19] ionic: Add adminq action Shannon Nelson
` (12 subsequent siblings)
18 siblings, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Most of the NIC configuration happens through the AdminQ message
queue. NAPI is used for basic interrupt handling and message
queue management. These routines are set up to be shared among
different types of queues when used in slow-path handling.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/ionic.h | 3 +
.../net/ethernet/pensando/ionic/ionic_bus.h | 1 +
.../ethernet/pensando/ionic/ionic_bus_pci.c | 5 +
.../ethernet/pensando/ionic/ionic_debugfs.c | 149 ++++++++
.../ethernet/pensando/ionic/ionic_debugfs.h | 4 +
.../net/ethernet/pensando/ionic/ionic_dev.c | 247 +++++++++++++
.../net/ethernet/pensando/ionic/ionic_dev.h | 92 +++++
.../net/ethernet/pensando/ionic/ionic_lif.c | 328 ++++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_lif.h | 72 ++++
.../net/ethernet/pensando/ionic/ionic_main.c | 26 ++
10 files changed, 927 insertions(+)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
index c86a08752b3b..c8c93e9efb39 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -43,6 +43,9 @@ struct ionic {
DECLARE_BITMAP(intrs, INTR_CTRL_REGS_MAX);
};
+int ionic_napi(struct napi_struct *napi, int budget, ionic_cq_cb cb,
+ ionic_cq_done_cb done_cb, void *done_arg);
+
int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_wait);
int ionic_set_dma_mask(struct ionic *ionic);
int ionic_setup(struct ionic *ionic);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus.h b/drivers/net/ethernet/pensando/ionic/ionic_bus.h
index 6b29e94f81d6..2f4d08c64910 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus.h
@@ -4,6 +4,7 @@
#ifndef _IONIC_BUS_H_
#define _IONIC_BUS_H_
+int ionic_bus_get_irq(struct ionic *ionic, unsigned int num);
const char *ionic_bus_info(struct ionic *ionic);
int ionic_bus_alloc_irq_vectors(struct ionic *ionic, unsigned int nintrs);
void ionic_bus_free_irq_vectors(struct ionic *ionic);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
index 838d7c423b2c..59d1ae7ce532 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -19,6 +19,11 @@ static const struct pci_device_id ionic_id_table[] = {
};
MODULE_DEVICE_TABLE(pci, ionic_id_table);
+int ionic_bus_get_irq(struct ionic *ionic, unsigned int num)
+{
+ return pci_irq_vector(ionic->pdev, num);
+}
+
const char *ionic_bus_info(struct ionic *ionic)
{
return pci_name(ionic->pdev);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
index a2a566695f63..9af15c69b2a6 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
@@ -80,6 +80,148 @@ int ionic_debugfs_add_sizes(struct ionic *ionic)
return 0;
}
+static int q_tail_show(struct seq_file *seq, void *v)
+{
+ struct queue *q = seq->private;
+
+ seq_printf(seq, "%d\n", q->tail->index);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(q_tail);
+
+static int q_head_show(struct seq_file *seq, void *v)
+{
+ struct queue *q = seq->private;
+
+ seq_printf(seq, "%d\n", q->head->index);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(q_head);
+
+static int cq_tail_show(struct seq_file *seq, void *v)
+{
+ struct cq *cq = seq->private;
+
+ seq_printf(seq, "%d\n", cq->tail->index);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(cq_tail);
+
+static const struct debugfs_reg32 intr_ctrl_regs[] = {
+ { .name = "coal_init", .offset = 0, },
+ { .name = "mask", .offset = 4, },
+ { .name = "credits", .offset = 8, },
+ { .name = "mask_on_assert", .offset = 12, },
+ { .name = "coal_timer", .offset = 16, },
+};
+
+int ionic_debugfs_add_qcq(struct lif *lif, struct qcq *qcq)
+{
+ struct dentry *qcq_dentry, *q_dentry, *cq_dentry, *intr_dentry;
+ struct ionic_dev *idev = &lif->ionic->idev;
+ struct debugfs_regset32 *intr_ctrl_regset;
+ struct debugfs_blob_wrapper *desc_blob;
+ struct device *dev = lif->ionic->dev;
+ struct intr *intr = &qcq->intr;
+ struct queue *q = &qcq->q;
+ struct cq *cq = &qcq->cq;
+
+ qcq_dentry = debugfs_create_dir(q->name, lif->dentry);
+ if (IS_ERR_OR_NULL(qcq_dentry))
+ return PTR_ERR(qcq_dentry);
+ qcq->dentry = qcq_dentry;
+
+ debugfs_create_x32("total_size", 0400, qcq_dentry, &qcq->total_size);
+ debugfs_create_x64("base_pa", 0400, qcq_dentry, &qcq->base_pa);
+
+ q_dentry = debugfs_create_dir("q", qcq_dentry);
+ if (IS_ERR_OR_NULL(q_dentry))
+ return PTR_ERR(q_dentry);
+
+ debugfs_create_u32("index", 0400, q_dentry, &q->index);
+ debugfs_create_x64("base_pa", 0400, q_dentry, &q->base_pa);
+ if (qcq->flags & QCQ_F_SG) {
+ debugfs_create_x64("sg_base_pa", 0400, q_dentry,
+ &q->sg_base_pa);
+ debugfs_create_u32("sg_desc_size", 0400, q_dentry,
+ &q->sg_desc_size);
+ }
+ debugfs_create_u32("num_descs", 0400, q_dentry, &q->num_descs);
+ debugfs_create_u32("desc_size", 0400, q_dentry, &q->desc_size);
+ debugfs_create_u32("pid", 0400, q_dentry, &q->pid);
+ debugfs_create_u32("qid", 0400, q_dentry, &q->hw_index);
+ debugfs_create_u32("qtype", 0400, q_dentry, &q->hw_type);
+ debugfs_create_u64("drop", 0400, q_dentry, &q->drop);
+ debugfs_create_u64("stop", 0400, q_dentry, &q->stop);
+ debugfs_create_u64("wake", 0400, q_dentry, &q->wake);
+
+ debugfs_create_file("tail", 0400, q_dentry, q, &q_tail_fops);
+ debugfs_create_file("head", 0400, q_dentry, q, &q_head_fops);
+
+ desc_blob = devm_kzalloc(dev, sizeof(*desc_blob), GFP_KERNEL);
+ if (!desc_blob)
+ return -ENOMEM;
+ desc_blob->data = q->base;
+ desc_blob->size = (unsigned long)q->num_descs * q->desc_size;
+ debugfs_create_blob("desc_blob", 0400, q_dentry, desc_blob);
+
+ if (qcq->flags & QCQ_F_SG) {
+ desc_blob = devm_kzalloc(dev, sizeof(*desc_blob), GFP_KERNEL);
+ if (!desc_blob)
+ return -ENOMEM;
+ desc_blob->data = q->sg_base;
+ desc_blob->size = (unsigned long)q->num_descs * q->sg_desc_size;
+ debugfs_create_blob("sg_desc_blob", 0400, q_dentry,
+ desc_blob);
+ }
+
+ cq_dentry = debugfs_create_dir("cq", qcq_dentry);
+ if (IS_ERR_OR_NULL(cq_dentry))
+ return PTR_ERR(cq_dentry);
+
+ debugfs_create_x64("base_pa", 0400, cq_dentry, &cq->base_pa);
+ debugfs_create_u32("num_descs", 0400, cq_dentry, &cq->num_descs);
+ debugfs_create_u32("desc_size", 0400, cq_dentry, &cq->desc_size);
+ debugfs_create_u8("done_color", 0400, cq_dentry,
+ (u8 *)&cq->done_color);
+
+ debugfs_create_file("tail", 0400, cq_dentry, cq, &cq_tail_fops);
+
+ desc_blob = devm_kzalloc(dev, sizeof(*desc_blob), GFP_KERNEL);
+ if (!desc_blob)
+ return -ENOMEM;
+ desc_blob->data = cq->base;
+ desc_blob->size = (unsigned long)cq->num_descs * cq->desc_size;
+ debugfs_create_blob("desc_blob", 0400, cq_dentry, desc_blob);
+
+ if (qcq->flags & QCQ_F_INTR) {
+ intr_dentry = debugfs_create_dir("intr", qcq_dentry);
+ if (IS_ERR_OR_NULL(intr_dentry))
+ return PTR_ERR(intr_dentry);
+
+ debugfs_create_u32("index", 0400, intr_dentry,
+ &intr->index);
+ debugfs_create_u32("vector", 0400, intr_dentry,
+ &intr->vector);
+
+ intr_ctrl_regset = devm_kzalloc(dev, sizeof(*intr_ctrl_regset),
+ GFP_KERNEL);
+ if (!intr_ctrl_regset)
+ return -ENOMEM;
+ intr_ctrl_regset->regs = intr_ctrl_regs;
+ intr_ctrl_regset->nregs = ARRAY_SIZE(intr_ctrl_regs);
+ intr_ctrl_regset->base = &idev->intr_ctrl[intr->index];
+
+ debugfs_create_regset32("intr_ctrl", 0400, intr_dentry,
+ intr_ctrl_regset);
+ }
+
+ return 0;
+}
+
static int netdev_show(struct seq_file *seq, void *v)
{
struct net_device *netdev = seq->private;
@@ -111,4 +253,11 @@ void ionic_debugfs_del_lif(struct lif *lif)
debugfs_remove_recursive(lif->dentry);
lif->dentry = NULL;
}
+
+void ionic_debugfs_del_qcq(struct qcq *qcq)
+{
+ debugfs_remove_recursive(qcq->dentry);
+ qcq->dentry = NULL;
+}
+
#endif
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
index cb00166e7c30..fa5030d48763 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.h
@@ -17,7 +17,9 @@ int ionic_debugfs_add_dev_cmd(struct ionic *ionic);
int ionic_debugfs_add_ident(struct ionic *ionic);
int ionic_debugfs_add_sizes(struct ionic *ionic);
int ionic_debugfs_add_lif(struct lif *lif);
+int ionic_debugfs_add_qcq(struct lif *lif, struct qcq *qcq);
void ionic_debugfs_del_lif(struct lif *lif);
+void ionic_debugfs_del_qcq(struct qcq *qcq);
#else
static inline void ionic_debugfs_create(void) { }
static inline void ionic_debugfs_destroy(void) { }
@@ -28,7 +30,9 @@ static inline int ionic_debugfs_add_dev_cmd(struct ionic *ionic) { return 0; }
static inline int ionic_debugfs_add_ident(struct ionic *ionic) { return 0; }
static inline int ionic_debugfs_add_sizes(struct ionic *ionic) { return 0; }
static inline int ionic_debugfs_add_lif(struct lif *lif) { return 0; }
+static inline int ionic_debugfs_add_qcq(struct lif *lif, struct qcq *qcq) { return 0; }
static inline void ionic_debugfs_del_lif(struct lif *lif) { return 0; }
+static inline void ionic_debugfs_del_qcq(struct qcq *qcq) { return 0; }
#endif
#endif /* _IONIC_DEBUGFS_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.c b/drivers/net/ethernet/pensando/ionic/ionic_dev.c
index c0710bf200a5..9694e45b43a6 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_dev.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.c
@@ -282,7 +282,254 @@ void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index)
ionic_dev_cmd_go(idev, &cmd);
}
+void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct qcq *qcq,
+ u16 lif_index, u16 intr_index)
+{
+ struct queue *q = &qcq->q;
+ struct cq *cq = &qcq->cq;
+
+ union dev_cmd cmd = {
+ .q_init.opcode = CMD_OPCODE_Q_INIT,
+ .q_init.lif_index = cpu_to_le16(lif_index),
+ .q_init.type = q->type,
+ .q_init.index = cpu_to_le32(q->index),
+ .q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
+ IONIC_QINIT_F_ENA),
+ .q_init.pid = cpu_to_le16(q->pid),
+ .q_init.intr_index = cpu_to_le16(intr_index),
+ .q_init.ring_size = ilog2(q->num_descs),
+ .q_init.ring_base = cpu_to_le64(q->base_pa),
+ .q_init.cq_ring_base = cpu_to_le64(cq->base_pa),
+ };
+
+ ionic_dev_cmd_go(idev, &cmd);
+}
+
int ionic_db_page_num(struct lif *lif, int pid)
{
return (lif->hw_index * lif->dbid_count) + pid;
}
+
+int ionic_cq_init(struct lif *lif, struct cq *cq, struct intr *intr,
+ unsigned int num_descs, size_t desc_size)
+{
+ unsigned int ring_size;
+ struct cq_info *cur;
+ unsigned int i;
+
+ if (desc_size == 0 || !is_power_of_2(num_descs))
+ return -EINVAL;
+
+ ring_size = ilog2(num_descs);
+ if (ring_size < 2 || ring_size > 16)
+ return -EINVAL;
+
+ cq->lif = lif;
+ cq->bound_intr = intr;
+ cq->num_descs = num_descs;
+ cq->desc_size = desc_size;
+ cq->tail = cq->info;
+ cq->done_color = 1;
+
+ cur = cq->info;
+
+ for (i = 0; i < num_descs; i++) {
+ if (i + 1 == num_descs) {
+ cur->next = cq->info;
+ cur->last = true;
+ } else {
+ cur->next = cur + 1;
+ }
+ cur->index = i;
+ cur++;
+ }
+
+ return 0;
+}
+
+void ionic_cq_map(struct cq *cq, void *base, dma_addr_t base_pa)
+{
+ struct cq_info *cur;
+ unsigned int i;
+
+ cq->base = base;
+ cq->base_pa = base_pa;
+
+ for (i = 0, cur = cq->info; i < cq->num_descs; i++, cur++)
+ cur->cq_desc = base + (i * cq->desc_size);
+}
+
+void ionic_cq_bind(struct cq *cq, struct queue *q)
+{
+ cq->bound_q = q;
+}
+
+unsigned int ionic_cq_service(struct cq *cq, unsigned int work_to_do,
+ ionic_cq_cb cb, ionic_cq_done_cb done_cb,
+ void *done_arg)
+{
+ unsigned int work_done = 0;
+
+ if (work_to_do == 0)
+ return 0;
+
+ while (cb(cq, cq->tail)) {
+ if (cq->tail->last)
+ cq->done_color = !cq->done_color;
+ cq->tail = cq->tail->next;
+ DEBUG_STATS_CQE_CNT(cq);
+
+ if (++work_done >= work_to_do)
+ break;
+ }
+
+ if (work_done && done_cb)
+ done_cb(done_arg);
+
+ return work_done;
+}
+
+int ionic_q_init(struct lif *lif, struct ionic_dev *idev, struct queue *q,
+ unsigned int index, const char *name, unsigned int num_descs,
+ size_t desc_size, size_t sg_desc_size, unsigned int pid)
+{
+ unsigned int ring_size;
+ struct desc_info *cur;
+ unsigned int i;
+
+ if (desc_size == 0 || !is_power_of_2(num_descs))
+ return -EINVAL;
+
+ ring_size = ilog2(num_descs);
+ if (ring_size < 2 || ring_size > 16)
+ return -EINVAL;
+
+ q->lif = lif;
+ q->idev = idev;
+ q->index = index;
+ q->num_descs = num_descs;
+ q->desc_size = desc_size;
+ q->sg_desc_size = sg_desc_size;
+ q->tail = q->info;
+ q->head = q->tail;
+ q->pid = pid;
+
+ snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index);
+
+ cur = q->info;
+
+ for (i = 0; i < num_descs; i++) {
+ if (i + 1 == num_descs)
+ cur->next = q->info;
+ else
+ cur->next = cur + 1;
+ cur->index = i;
+ cur->left = num_descs - i;
+ cur++;
+ }
+
+ return 0;
+}
+
+void ionic_q_map(struct queue *q, void *base, dma_addr_t base_pa)
+{
+ struct desc_info *cur;
+ unsigned int i;
+
+ q->base = base;
+ q->base_pa = base_pa;
+
+ for (i = 0, cur = q->info; i < q->num_descs; i++, cur++)
+ cur->desc = base + (i * q->desc_size);
+}
+
+void ionic_q_sg_map(struct queue *q, void *base, dma_addr_t base_pa)
+{
+ struct desc_info *cur;
+ unsigned int i;
+
+ q->sg_base = base;
+ q->sg_base_pa = base_pa;
+
+ for (i = 0, cur = q->info; i < q->num_descs; i++, cur++)
+ cur->sg_desc = base + (i * q->sg_desc_size);
+}
+
+void ionic_q_post(struct queue *q, bool ring_doorbell, desc_cb cb,
+ void *cb_arg)
+{
+ struct device *dev = q->lif->ionic->dev;
+ struct lif *lif = q->lif;
+
+ q->head->cb = cb;
+ q->head->cb_arg = cb_arg;
+ q->head = q->head->next;
+
+ dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n",
+ q->lif->index, q->name, q->hw_type, q->hw_index,
+ q->head->index, ring_doorbell);
+
+ if (ring_doorbell)
+ ionic_dbell_ring(lif->kern_dbpage, q->hw_type,
+ q->dbval | q->head->index);
+}
+
+unsigned int ionic_q_space_avail(struct queue *q)
+{
+ unsigned int avail = q->tail->index;
+
+ if (q->head->index >= avail)
+ avail += q->head->left - 1;
+ else
+ avail -= q->head->index + 1;
+
+ return avail;
+}
+
+bool ionic_q_has_space(struct queue *q, unsigned int want)
+{
+ return ionic_q_space_avail(q) >= want;
+}
+
+static bool ionic_q_is_posted(struct queue *q, unsigned int pos)
+{
+ unsigned int mask, tail, head;
+
+ mask = q->num_descs - 1;
+ tail = q->tail->index;
+ head = q->head->index;
+
+ return ((pos - tail) & mask) < ((head - tail) & mask);
+}
+
+void ionic_q_service(struct queue *q, struct cq_info *cq_info,
+ unsigned int stop_index)
+{
+ struct desc_info *desc_info;
+ void *cb_arg;
+ desc_cb cb;
+
+ /* check for empty queue */
+ if (q->tail->index == q->head->index)
+ return;
+
+ /* stop index must be for a descriptor that is not yet completed */
+ if (unlikely(!ionic_q_is_posted(q, stop_index)))
+ dev_err(q->lif->ionic->dev,
+ "ionic stop is not posted %s stop %u tail %u head %u\n",
+ q->name, stop_index, q->tail->index, q->head->index);
+
+ do {
+ desc_info = q->tail;
+ q->tail = desc_info->next;
+
+ cb = desc_info->cb;
+ cb_arg = desc_info->cb_arg;
+
+ desc_info->cb = NULL;
+ desc_info->cb_arg = NULL;
+
+ if (cb)
+ cb(q, desc_info, cq_info, cb_arg);
+ } while (desc_info->index != stop_index);
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
index 6d30adeab8c5..8bd1501dd639 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_dev.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
@@ -132,6 +132,59 @@ struct ionic_dev {
struct ionic_devinfo dev_info;
};
+struct cq_info {
+ void *cq_desc;
+ struct cq_info *next;
+ unsigned int index;
+ bool last;
+};
+
+struct queue;
+struct qcq;
+struct desc_info;
+
+typedef void (*desc_cb)(struct queue *q, struct desc_info *desc_info,
+ struct cq_info *cq_info, void *cb_arg);
+
+struct desc_info {
+ void *desc;
+ void *sg_desc;
+ struct desc_info *next;
+ unsigned int index;
+ unsigned int left;
+ desc_cb cb;
+ void *cb_arg;
+};
+
+#define QUEUE_NAME_MAX_SZ 32
+
+struct queue {
+ char name[QUEUE_NAME_MAX_SZ];
+ struct ionic_dev *idev;
+ struct lif *lif;
+ unsigned int index;
+ unsigned int type;
+ unsigned int hw_index;
+ unsigned int hw_type;
+ u64 dbval;
+ void *base;
+ void *sg_base;
+ dma_addr_t base_pa;
+ dma_addr_t sg_base_pa;
+ struct desc_info *info;
+ struct desc_info *tail;
+ struct desc_info *head;
+ unsigned int num_descs;
+ unsigned int desc_size;
+ unsigned int sg_desc_size;
+ void *nop_desc;
+ unsigned int pid;
+ u64 dbell_count;
+ u64 drop;
+ u64 stop;
+ u64 wake;
+};
+
#define INTR_INDEX_NOT_ASSIGNED -1
#define INTR_NAME_MAX_SZ 32
@@ -144,6 +197,20 @@ struct intr {
cpumask_t affinity_mask;
};
+struct cq {
+ void *base;
+ dma_addr_t base_pa;
+ struct lif *lif;
+ struct cq_info *info;
+ struct cq_info *tail;
+ struct queue *bound_q;
+ struct intr *bound_intr;
+ u64 compl_count;
+ unsigned int num_descs;
+ unsigned int desc_size;
+ bool done_color;
+};
+
struct ionic;
static inline void ionic_intr_init(struct ionic_dev *idev, struct intr *intr,
@@ -181,7 +248,32 @@ void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver);
void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
dma_addr_t addr);
void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index);
+void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct qcq *qcq,
+ u16 lif_index, u16 intr_index);
int ionic_db_page_num(struct lif *lif, int pid);
+int ionic_cq_init(struct lif *lif, struct cq *cq, struct intr *intr,
+ unsigned int num_descs, size_t desc_size);
+void ionic_cq_map(struct cq *cq, void *base, dma_addr_t base_pa);
+void ionic_cq_bind(struct cq *cq, struct queue *q);
+typedef bool (*ionic_cq_cb)(struct cq *cq, struct cq_info *cq_info);
+typedef void (*ionic_cq_done_cb)(void *done_arg);
+unsigned int ionic_cq_service(struct cq *cq, unsigned int work_to_do,
+ ionic_cq_cb cb, ionic_cq_done_cb done_cb,
+ void *done_arg);
+
+int ionic_q_init(struct lif *lif, struct ionic_dev *idev, struct queue *q,
+ unsigned int index, const char *name, unsigned int num_descs,
+ size_t desc_size, size_t sg_desc_size, unsigned int pid);
+void ionic_q_map(struct queue *q, void *base, dma_addr_t base_pa);
+void ionic_q_sg_map(struct queue *q, void *base, dma_addr_t base_pa);
+void ionic_q_post(struct queue *q, bool ring_doorbell, desc_cb cb,
+ void *cb_arg);
+void ionic_q_rewind(struct queue *q, struct desc_info *start);
+unsigned int ionic_q_space_avail(struct queue *q);
+bool ionic_q_has_space(struct queue *q, unsigned int want);
+void ionic_q_service(struct queue *q, struct cq_info *cq_info,
+ unsigned int stop_index);
+
#endif /* _IONIC_DEV_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index 65ced9b469c9..19c046502a26 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -12,6 +12,32 @@
#include "ionic_lif.h"
#include "ionic_debugfs.h"
+static bool ionic_adminq_service(struct cq *cq, struct cq_info *cq_info)
+{
+ struct admin_comp *comp = cq_info->cq_desc;
+
+ if (!color_match(comp->color, cq->done_color))
+ return false;
+
+ ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index));
+
+ return true;
+}
+
+static int ionic_adminq_napi(struct napi_struct *napi, int budget)
+{
+ return ionic_napi(napi, budget, ionic_adminq_service, NULL, NULL);
+}
+
+static irqreturn_t ionic_isr(int irq, void *data)
+{
+ struct napi_struct *napi = data;
+
+ napi_schedule_irqoff(napi);
+
+ return IRQ_HANDLED;
+}
+
static int ionic_intr_alloc(struct lif *lif, struct intr *intr)
{
struct ionic *ionic = lif->ionic;
@@ -36,6 +62,191 @@ static void ionic_intr_free(struct lif *lif, int index)
clear_bit(index, lif->ionic->intrs);
}
+static int ionic_qcq_alloc(struct lif *lif, unsigned int type,
+ unsigned int index,
+ const char *name, unsigned int flags,
+ unsigned int num_descs, unsigned int desc_size,
+ unsigned int cq_desc_size,
+ unsigned int sg_desc_size,
+ unsigned int pid, struct qcq **qcq)
+{
+ struct ionic_dev *idev = &lif->ionic->idev;
+ u32 q_size, cq_size, sg_size, total_size;
+ struct device *dev = lif->ionic->dev;
+ void *q_base, *cq_base, *sg_base;
+ dma_addr_t cq_base_pa = 0;
+ dma_addr_t sg_base_pa = 0;
+ dma_addr_t q_base_pa = 0;
+ struct qcq *new;
+ int err;
+
+ *qcq = NULL;
+
+ q_size = num_descs * desc_size;
+ cq_size = num_descs * cq_desc_size;
+ sg_size = num_descs * sg_desc_size;
+
+ total_size = ALIGN(q_size, PAGE_SIZE) + ALIGN(cq_size, PAGE_SIZE);
+ /* Note: aligning q_size/cq_size is not enough due to cq_base
+ * address aligning as q_base could be not aligned to the page.
+ * Adding PAGE_SIZE.
+ */
+ total_size += PAGE_SIZE;
+ if (flags & QCQ_F_SG) {
+ total_size += ALIGN(sg_size, PAGE_SIZE);
+ total_size += PAGE_SIZE;
+ }
+
+ new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL);
+ if (!new) {
+ netdev_err(lif->netdev, "Cannot allocate queue structure\n");
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ new->flags = flags;
+
+ new->q.info = devm_kzalloc(dev, sizeof(*new->q.info) * num_descs,
+ GFP_KERNEL);
+ if (!new->q.info) {
+ netdev_err(lif->netdev, "Cannot allocate queue info\n");
+ err = -ENOMEM;
+ goto err_out;
+ }
+
+ new->q.type = type;
+
+ err = ionic_q_init(lif, idev, &new->q, index, name, num_descs,
+ desc_size, sg_desc_size, pid);
+ if (err) {
+ netdev_err(lif->netdev, "Cannot initialize queue\n");
+ goto err_out;
+ }
+
+ if (flags & QCQ_F_INTR) {
+ err = ionic_intr_alloc(lif, &new->intr);
+ if (err) {
+ netdev_warn(lif->netdev, "no intr for %s: %d\n",
+ name, err);
+ goto err_out;
+ }
+
+ err = ionic_bus_get_irq(lif->ionic, new->intr.index);
+ if (err < 0) {
+ netdev_warn(lif->netdev, "no vector for %s: %d\n",
+ name, err);
+ goto err_out_free_intr;
+ }
+ new->intr.vector = err;
+ ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index,
+ IONIC_INTR_MASK_SET);
+
+ new->intr.cpu = new->intr.index % num_online_cpus();
+ if (cpu_online(new->intr.cpu))
+ cpumask_set_cpu(new->intr.cpu,
+ &new->intr.affinity_mask);
+ } else {
+ new->intr.index = INTR_INDEX_NOT_ASSIGNED;
+ }
+
+ new->cq.info = devm_kzalloc(dev, sizeof(*new->cq.info) * num_descs,
+ GFP_KERNEL);
+ if (!new->cq.info) {
+ netdev_err(lif->netdev, "Cannot allocate completion queue info\n");
+ err = -ENOMEM;
+ goto err_out_free_intr;
+ }
+
+ err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size);
+ if (err) {
+ netdev_err(lif->netdev, "Cannot initialize completion queue\n");
+ goto err_out_free_intr;
+ }
+
+ new->base = dma_alloc_coherent(dev, total_size, &new->base_pa,
+ GFP_KERNEL);
+ if (!new->base) {
+ netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n");
+ err = -ENOMEM;
+ goto err_out_free_intr;
+ }
+
+ new->total_size = total_size;
+
+ q_base = new->base;
+ q_base_pa = new->base_pa;
+
+ cq_base = (void *)ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);
+ cq_base_pa = ALIGN(q_base_pa + q_size, PAGE_SIZE);
+
+ if (flags & QCQ_F_SG) {
+ sg_base = (void *)ALIGN((uintptr_t)cq_base + cq_size,
+ PAGE_SIZE);
+ sg_base_pa = ALIGN(cq_base_pa + cq_size, PAGE_SIZE);
+ ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
+ }
+
+ ionic_q_map(&new->q, q_base, q_base_pa);
+ ionic_cq_map(&new->cq, cq_base, cq_base_pa);
+ ionic_cq_bind(&new->cq, &new->q);
+
+ *qcq = new;
+
+ return 0;
+
+err_out_free_intr:
+ ionic_intr_free(lif, new->intr.index);
+err_out:
+ dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err);
+ return err;
+}
+
+static void ionic_qcq_free(struct lif *lif, struct qcq *qcq)
+{
+ struct device *dev = lif->ionic->dev;
+
+ if (!qcq)
+ return;
+
+ dma_free_coherent(dev, qcq->total_size, qcq->base, qcq->base_pa);
+ qcq->base = NULL;
+ qcq->base_pa = 0;
+
+ if (qcq->flags & QCQ_F_INTR)
+ ionic_intr_free(lif, qcq->intr.index);
+
+ devm_kfree(dev, qcq->cq.info);
+ qcq->cq.info = NULL;
+ devm_kfree(dev, qcq->q.info);
+ qcq->q.info = NULL;
+ devm_kfree(dev, qcq);
+}
+
+static int ionic_qcqs_alloc(struct lif *lif)
+{
+ unsigned int flags;
+ int err;
+
+ flags = QCQ_F_INTR;
+ err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
+ IONIC_ADMINQ_LENGTH,
+ sizeof(struct admin_cmd),
+ sizeof(struct admin_comp),
+ 0, lif->kern_pid, &lif->adminqcq);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static void ionic_qcqs_free(struct lif *lif)
+{
+ if (lif->adminqcq) {
+ ionic_qcq_free(lif, lif->adminqcq);
+ lif->adminqcq = NULL;
+ }
+}
+
static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
{
struct device *dev = ionic->dev;
@@ -65,6 +276,8 @@ static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
snprintf(lif->name, sizeof(lif->name), "lif%u", index);
+ spin_lock_init(&lif->adminq_lock);
+
/* allocate lif info */
lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
lif->info = dma_alloc_coherent(dev, lif->info_sz,
@@ -75,10 +288,19 @@ static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
goto err_out_free_netdev;
}
+ /* allocate queues */
+ err = ionic_qcqs_alloc(lif);
+ if (err)
+ goto err_out_free_lif_info;
+
list_add_tail(&lif->list, &ionic->lifs);
return lif;
+err_out_free_lif_info:
+ dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
+ lif->info = NULL;
+ lif->info_pa = 0;
err_out_free_netdev:
free_netdev(lif->netdev);
lif = NULL;
@@ -113,6 +335,8 @@ static void ionic_lif_free(struct lif *lif)
{
struct device *dev = lif->ionic->dev;
+ /* free queues */
+ ionic_qcqs_free(lif);
ionic_lif_reset(lif);
/* free lif info */
@@ -144,6 +368,30 @@ void ionic_lifs_free(struct ionic *ionic)
}
}
+static void ionic_lif_qcq_deinit(struct lif *lif, struct qcq *qcq)
+{
+ struct ionic_dev *idev = &lif->ionic->idev;
+ struct device *dev = lif->ionic->dev;
+
+ if (!qcq)
+ return;
+
+ ionic_debugfs_del_qcq(qcq);
+
+ if (!(qcq->flags & QCQ_F_INITED))
+ return;
+
+ if (qcq->flags & QCQ_F_INTR) {
+ ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
+ IONIC_INTR_MASK_SET);
+ synchronize_irq(qcq->intr.vector);
+ devm_free_irq(dev, qcq->intr.vector, &qcq->napi);
+ netif_napi_del(&qcq->napi);
+ }
+
+ qcq->flags &= ~QCQ_F_INITED;
+}
+
static void ionic_lif_deinit(struct lif *lif)
{
if (!test_bit(LIF_INITED, lif->state))
@@ -151,6 +399,9 @@ static void ionic_lif_deinit(struct lif *lif)
clear_bit(LIF_INITED, lif->state);
+ napi_disable(&lif->adminqcq->napi);
+ ionic_lif_qcq_deinit(lif, lif->adminqcq);
+
ionic_lif_reset(lif);
}
@@ -165,6 +416,74 @@ void ionic_lifs_deinit(struct ionic *ionic)
}
}
+static int ionic_request_irq(struct lif *lif, struct qcq *qcq)
+{
+ struct device *dev = lif->ionic->dev;
+ struct intr *intr = &qcq->intr;
+ struct queue *q = &qcq->q;
+ const char *name;
+
+ if (lif->registered)
+ name = lif->netdev->name;
+ else
+ name = dev_name(dev);
+
+ snprintf(intr->name, sizeof(intr->name),
+ "%s-%s-%s", DRV_NAME, name, q->name);
+
+ return devm_request_irq(dev, intr->vector, ionic_isr,
+ 0, intr->name, &qcq->napi);
+}
+
+static int ionic_lif_adminq_init(struct lif *lif)
+{
+ struct device *dev = lif->ionic->dev;
+ struct ionic_dev *idev = &lif->ionic->idev;
+ struct qcq *qcq = lif->adminqcq;
+ struct queue *q = &qcq->q;
+ struct q_init_comp comp;
+ int err;
+
+ mutex_lock(&lif->ionic->dev_cmd_lock);
+ ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index);
+ err = ionic_dev_cmd_wait(lif->ionic, devcmd_timeout);
+ ionic_dev_cmd_comp(idev, (union dev_cmd_comp *)&comp);
+ mutex_unlock(&lif->ionic->dev_cmd_lock);
+ if (err) {
+ netdev_err(lif->netdev, "adminq init failed %d\n", err);
+ return err;
+ }
+
+ q->hw_type = comp.hw_type;
+ q->hw_index = le32_to_cpu(comp.hw_index);
+ q->dbval = IONIC_DBELL_QID(q->hw_index);
+
+ dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type);
+ dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index);
+
+ netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi,
+ NAPI_POLL_WEIGHT);
+
+ err = ionic_request_irq(lif, qcq);
+ if (err) {
+ netdev_warn(lif->netdev, "adminq irq request failed %d\n", err);
+ netif_napi_del(&qcq->napi);
+ return err;
+ }
+
+ napi_enable(&qcq->napi);
+
+ if (qcq->flags & QCQ_F_INTR)
+ ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
+ IONIC_INTR_MASK_CLEAR);
+
+ qcq->flags |= QCQ_F_INITED;
+
+ ionic_debugfs_add_qcq(lif, qcq);
+
+ return 0;
+}
+
static int ionic_lif_init(struct lif *lif)
{
struct ionic_dev *idev = &lif->ionic->idev;
@@ -211,10 +530,19 @@ static int ionic_lif_init(struct lif *lif)
goto err_out_free_dbid;
}
+ err = ionic_lif_adminq_init(lif);
+ if (err)
+ goto err_out_adminq_deinit;
+
set_bit(LIF_INITED, lif->state);
return 0;
+err_out_adminq_deinit:
+ ionic_lif_qcq_deinit(lif, lif->adminqcq);
+ ionic_lif_reset(lif);
+ ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage);
+ lif->kern_dbpage = NULL;
err_out_free_dbid:
kfree(lif->dbid_inuse);
lif->dbid_inuse = NULL;
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index 98d0699234e9..28ab92b43a64 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -6,6 +6,57 @@
#include <linux/pci.h>
+#define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */
+
+#define GET_NAPI_CNTR_IDX(work_done) (work_done)
+#define MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1)
+#define GET_SG_CNTR_IDX(num_sg_elems) (num_sg_elems)
+#define MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1)
+
+struct tx_stats {
+ u64 pkts;
+ u64 bytes;
+};
+
+struct rx_stats {
+ u64 pkts;
+ u64 bytes;
+};
+
+#define QCQ_F_INITED BIT(0)
+#define QCQ_F_SG BIT(1)
+#define QCQ_F_INTR BIT(2)
+
+struct napi_stats {
+ u64 poll_count;
+ u64 work_done_cntr[MAX_NUM_NAPI_CNTR];
+};
+
+struct q_stats {
+ union {
+ struct tx_stats tx;
+ struct rx_stats rx;
+ };
+};
+
+struct qcq {
+ void *base;
+ dma_addr_t base_pa;
+ unsigned int total_size;
+ struct queue q;
+ struct cq cq;
+ struct intr intr;
+ struct napi_struct napi;
+ struct napi_stats napi_stats;
+ struct q_stats *stats;
+ unsigned int flags;
+ struct dentry *dentry;
+};
+
+#define q_to_qcq(q) container_of(q, struct qcq, q)
+#define napi_to_qcq(napi) container_of(napi, struct qcq, napi)
+#define napi_to_cq(napi) (&napi_to_qcq(napi)->cq)
+
enum lif_state_flags {
LIF_INITED,
@@ -25,6 +76,8 @@ struct lif {
unsigned int hw_index;
unsigned int kern_pid;
u64 __iomem *kern_dbpage;
+ spinlock_t adminq_lock; /* lock for AdminQ operations */
+ struct qcq *adminqcq;
unsigned int neqs;
unsigned int nxqs;
@@ -71,4 +124,23 @@ int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
union lif_identity *lif_ident);
int ionic_lifs_size(struct ionic *ionic);
+static inline void debug_stats_napi_poll(struct qcq *qcq,
+ unsigned int work_done)
+{
+ u32 napi_cntr_idx;
+
+ qcq->napi_stats.poll_count++;
+
+ napi_cntr_idx = GET_NAPI_CNTR_IDX(work_done);
+ if (napi_cntr_idx > (MAX_NUM_NAPI_CNTR - 1))
+ napi_cntr_idx = MAX_NUM_NAPI_CNTR - 1;
+
+ qcq->napi_stats.work_done_cntr[napi_cntr_idx]++;
+}
+
+#define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++)
+#define DEBUG_STATS_INTR_REARM(intr) ((intr)->rearm_count++)
+#define DEBUG_STATS_NAPI_POLL(qcq, work_done) \
+ debug_stats_napi_poll(qcq, work_done)
+
#endif /* _IONIC_LIF_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_main.c b/drivers/net/ethernet/pensando/ionic/ionic_main.c
index b732e7345550..aa73ea81a4b2 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_main.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_main.c
@@ -169,6 +169,32 @@ static const char *ionic_opcode_to_str(enum cmd_opcode opcode)
}
}
+int ionic_napi(struct napi_struct *napi, int budget, ionic_cq_cb cb,
+ ionic_cq_done_cb done_cb, void *done_arg)
+{
+ struct qcq *qcq = napi_to_qcq(napi);
+ struct cq *cq = &qcq->cq;
+ u32 work_done, flags = 0;
+
+ work_done = ionic_cq_service(cq, budget, cb, done_cb, done_arg);
+
+ if (work_done < budget && napi_complete_done(napi, work_done)) {
+ flags |= IONIC_INTR_CRED_UNMASK;
+ DEBUG_STATS_INTR_REARM(cq->bound_intr);
+ }
+
+ if (work_done || flags) {
+ flags |= IONIC_INTR_CRED_RESET_COALESCE;
+ ionic_intr_credits(cq->lif->ionic->idev.intr_ctrl,
+ cq->bound_intr->index,
+ work_done, flags);
+ }
+
+ DEBUG_STATS_NAPI_POLL(qcq, work_done);
+
+ return work_done;
+}
+
int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_seconds)
{
struct ionic_dev *idev = &ionic->idev;
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 06/19] ionic: Add basic adminq support
2019-07-22 21:40 ` [PATCH v4 net-next 06/19] ionic: Add basic adminq support Shannon Nelson
@ 2019-07-23 21:27 ` David Miller
2019-07-23 22:50 ` Shannon Nelson
0 siblings, 1 reply; 69+ messages in thread
From: David Miller @ 2019-07-23 21:27 UTC (permalink / raw)
To: snelson; +Cc: netdev
From: Shannon Nelson <snelson@pensando.io>
Date: Mon, 22 Jul 2019 14:40:10 -0700
> +struct queue {
...
> +struct cq {
...
> +struct napi_stats {
...
> +struct q_stats {
...
> +struct qcq {
Using names like these and "dev_queue" are just asking for conflicts with the
global datastructure namespace both now and in the future.
Please put ionic_ or similar as a prefix to these data structure names.
Thank you.
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 06/19] ionic: Add basic adminq support
2019-07-23 21:27 ` David Miller
@ 2019-07-23 22:50 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-23 22:50 UTC (permalink / raw)
To: David Miller; +Cc: netdev
On 7/23/19 2:27 PM, David Miller wrote:
> From: Shannon Nelson <snelson@pensando.io>
> Date: Mon, 22 Jul 2019 14:40:10 -0700
>
>> +struct queue {
> ...
>> +struct cq {
> ...
>> +struct napi_stats {
> ...
>> +struct q_stats {
> ...
>> +struct qcq {
> Using names like these and "dev_queue" are just asking for conflicts with the
> global datastructure namespace both now and in the future.
>
> Please put ionic_ or similar as a prefix to these data structure names.
>
> Thank you.
Sure
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 07/19] ionic: Add adminq action
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (5 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 06/19] ionic: Add basic adminq support Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-22 21:40 ` [PATCH v4 net-next 08/19] ionic: Add notifyq support Shannon Nelson
` (11 subsequent siblings)
18 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Add AdminQ specific message requests and completion handling.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/ionic.h | 7 ++
.../net/ethernet/pensando/ionic/ionic_main.c | 106 ++++++++++++++++++
2 files changed, 113 insertions(+)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
index c8c93e9efb39..87ab13aee89e 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -43,9 +43,16 @@ struct ionic {
DECLARE_BITMAP(intrs, INTR_CTRL_REGS_MAX);
};
+struct ionic_admin_ctx {
+ struct completion work;
+ union adminq_cmd cmd;
+ union adminq_comp comp;
+};
+
int ionic_napi(struct napi_struct *napi, int budget, ionic_cq_cb cb,
ionic_cq_done_cb done_cb, void *done_arg);
+int ionic_adminq_post_wait(struct lif *lif, struct ionic_admin_ctx *ctx);
int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_wait);
int ionic_set_dma_mask(struct ionic *ionic);
int ionic_setup(struct ionic *ionic);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_main.c b/drivers/net/ethernet/pensando/ionic/ionic_main.c
index aa73ea81a4b2..3b44e1752258 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_main.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_main.c
@@ -169,6 +169,112 @@ static const char *ionic_opcode_to_str(enum cmd_opcode opcode)
}
}
+static void ionic_adminq_flush(struct lif *lif)
+{
+ struct queue *adminq = &lif->adminqcq->q;
+
+ spin_lock(&lif->adminq_lock);
+
+ while (adminq->tail != adminq->head) {
+ memset(adminq->tail->desc, 0, sizeof(union adminq_cmd));
+ adminq->tail->cb = NULL;
+ adminq->tail->cb_arg = NULL;
+ adminq->tail = adminq->tail->next;
+ }
+ spin_unlock(&lif->adminq_lock);
+}
+
+static int ionic_adminq_check_err(struct lif *lif, struct ionic_admin_ctx *ctx,
+ bool timeout)
+{
+ struct net_device *netdev = lif->netdev;
+ const char *opcode_str;
+ const char *status_str;
+ int err = 0;
+
+ if (ctx->comp.comp.status || timeout) {
+ opcode_str = ionic_opcode_to_str(ctx->cmd.cmd.opcode);
+ status_str = ionic_error_to_str(ctx->comp.comp.status);
+ err = timeout ? -ETIMEDOUT :
+ ionic_error_to_errno(ctx->comp.comp.status);
+
+ netdev_err(netdev, "%s (%d) failed: %s (%d)\n",
+ opcode_str, ctx->cmd.cmd.opcode,
+ timeout ? "TIMEOUT" : status_str, err);
+
+ if (timeout)
+ ionic_adminq_flush(lif);
+ }
+
+ return err;
+}
+
+static void ionic_adminq_cb(struct queue *q, struct desc_info *desc_info,
+ struct cq_info *cq_info, void *cb_arg)
+{
+ struct ionic_admin_ctx *ctx = cb_arg;
+ struct admin_comp *comp = cq_info->cq_desc;
+ struct device *dev = &q->lif->netdev->dev;
+
+ if (!ctx)
+ return;
+
+ memcpy(&ctx->comp, comp, sizeof(*comp));
+
+ dev_dbg(dev, "comp admin queue command:\n");
+ dynamic_hex_dump("comp ", DUMP_PREFIX_OFFSET, 16, 1,
+ &ctx->comp, sizeof(ctx->comp), true);
+
+ complete_all(&ctx->work);
+}
+
+static int ionic_adminq_post(struct lif *lif, struct ionic_admin_ctx *ctx)
+{
+ struct queue *adminq = &lif->adminqcq->q;
+ int err = 0;
+
+ WARN_ON(in_interrupt());
+
+ spin_lock(&lif->adminq_lock);
+ if (!ionic_q_has_space(adminq, 1)) {
+ err = -ENOSPC;
+ goto err_out;
+ }
+
+ memcpy(adminq->head->desc, &ctx->cmd, sizeof(ctx->cmd));
+
+ dev_dbg(&lif->netdev->dev, "post admin queue command:\n");
+ dynamic_hex_dump("cmd ", DUMP_PREFIX_OFFSET, 16, 1,
+ &ctx->cmd, sizeof(ctx->cmd), true);
+
+ ionic_q_post(adminq, true, ionic_adminq_cb, ctx);
+
+err_out:
+ spin_unlock(&lif->adminq_lock);
+
+ return err;
+}
+
+int ionic_adminq_post_wait(struct lif *lif, struct ionic_admin_ctx *ctx)
+{
+ struct net_device *netdev = lif->netdev;
+ unsigned long remaining;
+ const char *name;
+ int err;
+
+ err = ionic_adminq_post(lif, ctx);
+ if (err) {
+ name = ionic_opcode_to_str(ctx->cmd.cmd.opcode);
+ netdev_err(netdev, "Posting of %s (%d) failed: %d\n",
+ name, ctx->cmd.cmd.opcode, err);
+ return err;
+ }
+
+ remaining = wait_for_completion_timeout(&ctx->work,
+ HZ * (ulong)devcmd_timeout);
+ return ionic_adminq_check_err(lif, ctx, (remaining == 0));
+}
+
int ionic_napi(struct napi_struct *napi, int budget, ionic_cq_cb cb,
ionic_cq_done_cb done_cb, void *done_arg)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* [PATCH v4 net-next 08/19] ionic: Add notifyq support
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (6 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 07/19] ionic: Add adminq action Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-24 23:21 ` Saeed Mahameed
2019-07-22 21:40 ` [PATCH v4 net-next 09/19] ionic: Add the basic NDO callbacks for netdev support Shannon Nelson
` (10 subsequent siblings)
18 siblings, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
The AdminQ is fine for sending messages and requests to the NIC,
but we also need to have events published from the NIC to the
driver. The NotifyQ handles this for us, using the same interrupt
as AdminQ.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
.../ethernet/pensando/ionic/ionic_debugfs.c | 16 ++
.../net/ethernet/pensando/ionic/ionic_lif.c | 181 +++++++++++++++++-
.../net/ethernet/pensando/ionic/ionic_lif.h | 4 +
3 files changed, 200 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
index 9af15c69b2a6..1d05b23de303 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
@@ -126,6 +126,7 @@ int ionic_debugfs_add_qcq(struct lif *lif, struct qcq *qcq)
struct debugfs_blob_wrapper *desc_blob;
struct device *dev = lif->ionic->dev;
struct intr *intr = &qcq->intr;
+ struct dentry *stats_dentry;
struct queue *q = &qcq->q;
struct cq *cq = &qcq->cq;
@@ -219,6 +220,21 @@ int ionic_debugfs_add_qcq(struct lif *lif, struct qcq *qcq)
intr_ctrl_regset);
}
+ if (qcq->flags & QCQ_F_NOTIFYQ) {
+ stats_dentry = debugfs_create_dir("notifyblock", qcq_dentry);
+ if (IS_ERR_OR_NULL(stats_dentry))
+ return PTR_ERR(stats_dentry);
+
+ debugfs_create_u64("eid", 0400, stats_dentry,
+ (u64 *)&lif->info->status.eid);
+ debugfs_create_u16("link_status", 0400, stats_dentry,
+ (u16 *)&lif->info->status.link_status);
+ debugfs_create_u32("link_speed", 0400, stats_dentry,
+ (u32 *)&lif->info->status.link_speed);
+ debugfs_create_u16("link_down_count", 0400, stats_dentry,
+ (u16 *)&lif->info->status.link_down_count);
+ }
+
return 0;
}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index 19c046502a26..01f9665611d4 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -12,6 +12,8 @@
#include "ionic_lif.h"
#include "ionic_debugfs.h"
+static int ionic_notifyq_clean(struct lif *lif, int budget);
+
static bool ionic_adminq_service(struct cq *cq, struct cq_info *cq_info)
{
struct admin_comp *comp = cq_info->cq_desc;
@@ -26,7 +28,90 @@ static bool ionic_adminq_service(struct cq *cq, struct cq_info *cq_info)
static int ionic_adminq_napi(struct napi_struct *napi, int budget)
{
- return ionic_napi(napi, budget, ionic_adminq_service, NULL, NULL);
+ struct lif *lif = napi_to_cq(napi)->lif;
+ int n_work = 0;
+ int a_work = 0;
+
+ if (likely(lif->notifyqcq && lif->notifyqcq->flags & QCQ_F_INITED))
+ n_work = ionic_notifyq_clean(lif, budget);
+ a_work = ionic_napi(napi, budget, ionic_adminq_service, NULL, NULL);
+
+ return max(n_work, a_work);
+}
+
+static bool ionic_notifyq_service(struct cq *cq, struct cq_info *cq_info)
+{
+ union notifyq_comp *comp = cq_info->cq_desc;
+ struct net_device *netdev;
+ struct queue *q;
+ struct lif *lif;
+ u64 eid;
+
+ q = cq->bound_q;
+ lif = q->info[0].cb_arg;
+ netdev = lif->netdev;
+ eid = le64_to_cpu(comp->event.eid);
+
+ /* Have we run out of new completions to process? */
+ if (eid <= lif->last_eid)
+ return false;
+
+ lif->last_eid = eid;
+
+ dev_dbg(lif->ionic->dev, "notifyq event:\n");
+ dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1,
+ comp, sizeof(*comp), true);
+
+ switch (le16_to_cpu(comp->event.ecode)) {
+ case EVENT_OPCODE_LINK_CHANGE:
+ netdev_info(netdev, "Notifyq EVENT_OPCODE_LINK_CHANGE eid=%lld\n",
+ eid);
+ netdev_info(netdev,
+ " link_status=%d link_speed=%d\n",
+ le16_to_cpu(comp->link_change.link_status),
+ le32_to_cpu(comp->link_change.link_speed));
+ break;
+ case EVENT_OPCODE_RESET:
+ netdev_info(netdev, "Notifyq EVENT_OPCODE_RESET eid=%lld\n",
+ eid);
+ netdev_info(netdev, " reset_code=%d state=%d\n",
+ comp->reset.reset_code,
+ comp->reset.state);
+ break;
+ case EVENT_OPCODE_LOG:
+ netdev_info(netdev, "Notifyq EVENT_OPCODE_LOG eid=%lld\n", eid);
+ print_hex_dump(KERN_INFO, "notifyq ", DUMP_PREFIX_OFFSET, 16, 1,
+ comp->log.data, sizeof(comp->log.data), true);
+ break;
+ default:
+ netdev_warn(netdev, "Notifyq unknown event ecode=%d eid=%lld\n",
+ comp->event.ecode, eid);
+ break;
+ }
+
+ return true;
+}
+
+static int ionic_notifyq_clean(struct lif *lif, int budget)
+{
+ struct ionic_dev *idev = &lif->ionic->idev;
+ struct cq *cq = &lif->notifyqcq->cq;
+ u32 work_done;
+
+ work_done = ionic_cq_service(cq, budget, ionic_notifyq_service,
+ NULL, NULL);
+ if (work_done)
+ ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index,
+ work_done, IONIC_INTR_CRED_RESET_COALESCE);
+
+ /* If we ran out of budget, there are more events
+ * to process and napi will reschedule us soon
+ */
+ if (work_done == budget)
+ goto return_to_napi;
+
+return_to_napi:
+ return work_done;
}
static irqreturn_t ionic_isr(int irq, void *data)
@@ -62,6 +147,17 @@ static void ionic_intr_free(struct lif *lif, int index)
clear_bit(index, lif->ionic->intrs);
}
+static void ionic_link_qcq_interrupts(struct qcq *src_qcq, struct qcq *n_qcq)
+{
+ if (WARN_ON(n_qcq->flags & QCQ_F_INTR)) {
+ ionic_intr_free(n_qcq->cq.lif, n_qcq->intr.index);
+ n_qcq->flags &= ~QCQ_F_INTR;
+ }
+
+ n_qcq->intr.vector = src_qcq->intr.vector;
+ n_qcq->intr.index = src_qcq->intr.index;
+}
+
static int ionic_qcq_alloc(struct lif *lif, unsigned int type,
unsigned int index,
const char *name, unsigned int flags,
@@ -236,11 +332,36 @@ static int ionic_qcqs_alloc(struct lif *lif)
if (err)
return err;
+ if (lif->ionic->nnqs_per_lif) {
+ flags = QCQ_F_NOTIFYQ;
+ err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq",
+ flags, IONIC_NOTIFYQ_LENGTH,
+ sizeof(struct notifyq_cmd),
+ sizeof(union notifyq_comp),
+ 0, lif->kern_pid, &lif->notifyqcq);
+ if (err)
+ goto err_out_free_adminqcq;
+
+ /* Let the notifyq ride on the adminq interrupt */
+ ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq);
+ }
+
return 0;
+
+err_out_free_adminqcq:
+ ionic_qcq_free(lif, lif->adminqcq);
+ lif->adminqcq = NULL;
+
+ return err;
}
static void ionic_qcqs_free(struct lif *lif)
{
+ if (lif->notifyqcq) {
+ ionic_qcq_free(lif, lif->notifyqcq);
+ lif->notifyqcq = NULL;
+ }
+
if (lif->adminqcq) {
ionic_qcq_free(lif, lif->adminqcq);
lif->adminqcq = NULL;
@@ -400,6 +521,7 @@ static void ionic_lif_deinit(struct lif *lif)
clear_bit(LIF_INITED, lif->state);
napi_disable(&lif->adminqcq->napi);
+ ionic_lif_qcq_deinit(lif, lif->notifyqcq);
ionic_lif_qcq_deinit(lif, lif->adminqcq);
ionic_lif_reset(lif);
@@ -484,6 +606,55 @@ static int ionic_lif_adminq_init(struct lif *lif)
return 0;
}
+static int ionic_lif_notifyq_init(struct lif *lif)
+{
+ struct device *dev = lif->ionic->dev;
+ struct qcq *qcq = lif->notifyqcq;
+ struct queue *q = &qcq->q;
+ int err;
+
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.q_init = {
+ .opcode = CMD_OPCODE_Q_INIT,
+ .lif_index = cpu_to_le16(lif->index),
+ .type = q->type,
+ .index = cpu_to_le32(q->index),
+ .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
+ IONIC_QINIT_F_ENA),
+ .intr_index = cpu_to_le16(lif->adminqcq->intr.index),
+ .pid = cpu_to_le16(q->pid),
+ .ring_size = ilog2(q->num_descs),
+ .ring_base = cpu_to_le64(q->base_pa),
+ }
+ };
+
+ dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid);
+ dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index);
+ dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
+ dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
+
+ err = ionic_adminq_post_wait(lif, &ctx);
+ if (err)
+ return err;
+
+ q->hw_type = ctx.comp.q_init.hw_type;
+ q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
+ q->dbval = IONIC_DBELL_QID(q->hw_index);
+
+ dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type);
+ dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index);
+
+ /* preset the callback info */
+ q->info[0].cb_arg = lif;
+
+ qcq->flags |= QCQ_F_INITED;
+
+ ionic_debugfs_add_qcq(lif, qcq);
+
+ return 0;
+}
+
static int ionic_lif_init(struct lif *lif)
{
struct ionic_dev *idev = &lif->ionic->idev;
@@ -534,10 +705,18 @@ static int ionic_lif_init(struct lif *lif)
if (err)
goto err_out_adminq_deinit;
+ if (lif->ionic->nnqs_per_lif) {
+ err = ionic_lif_notifyq_init(lif);
+ if (err)
+ goto err_out_notifyq_deinit;
+ }
+
set_bit(LIF_INITED, lif->state);
return 0;
+err_out_notifyq_deinit:
+ ionic_lif_qcq_deinit(lif, lif->notifyqcq);
err_out_adminq_deinit:
ionic_lif_qcq_deinit(lif, lif->adminqcq);
ionic_lif_reset(lif);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index 28ab92b43a64..80eec0778f40 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -7,6 +7,7 @@
#include <linux/pci.h>
#define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */
+#define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */
#define GET_NAPI_CNTR_IDX(work_done) (work_done)
#define MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1)
@@ -26,6 +27,7 @@ struct rx_stats {
#define QCQ_F_INITED BIT(0)
#define QCQ_F_SG BIT(1)
#define QCQ_F_INTR BIT(2)
+#define QCQ_F_NOTIFYQ BIT(5)
struct napi_stats {
u64 poll_count;
@@ -78,6 +80,8 @@ struct lif {
u64 __iomem *kern_dbpage;
spinlock_t adminq_lock; /* lock for AdminQ operations */
struct qcq *adminqcq;
+ struct qcq *notifyqcq;
+ u64 last_eid;
unsigned int neqs;
unsigned int nxqs;
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 08/19] ionic: Add notifyq support
2019-07-22 21:40 ` [PATCH v4 net-next 08/19] ionic: Add notifyq support Shannon Nelson
@ 2019-07-24 23:21 ` Saeed Mahameed
2019-07-30 18:35 ` Shannon Nelson
0 siblings, 1 reply; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-24 23:21 UTC (permalink / raw)
To: snelson, netdev, davem
On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> The AdminQ is fine for sending messages and requests to the NIC,
> but we also need to have events published from the NIC to the
> driver. The NotifyQ handles this for us, using the same interrupt
> as AdminQ.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
> ---
> .../ethernet/pensando/ionic/ionic_debugfs.c | 16 ++
> .../net/ethernet/pensando/ionic/ionic_lif.c | 181
> +++++++++++++++++-
> .../net/ethernet/pensando/ionic/ionic_lif.h | 4 +
> 3 files changed, 200 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
> b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
> index 9af15c69b2a6..1d05b23de303 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
> @@ -126,6 +126,7 @@ int ionic_debugfs_add_qcq(struct lif *lif, struct
> qcq *qcq)
> struct debugfs_blob_wrapper *desc_blob;
> struct device *dev = lif->ionic->dev;
> struct intr *intr = &qcq->intr;
> + struct dentry *stats_dentry;
> struct queue *q = &qcq->q;
> struct cq *cq = &qcq->cq;
>
> @@ -219,6 +220,21 @@ int ionic_debugfs_add_qcq(struct lif *lif,
> struct qcq *qcq)
> intr_ctrl_regset);
> }
>
> + if (qcq->flags & QCQ_F_NOTIFYQ) {
> + stats_dentry = debugfs_create_dir("notifyblock",
> qcq_dentry);
> + if (IS_ERR_OR_NULL(stats_dentry))
> + return PTR_ERR(stats_dentry);
> +
> + debugfs_create_u64("eid", 0400, stats_dentry,
> + (u64 *)&lif->info->status.eid);
> + debugfs_create_u16("link_status", 0400, stats_dentry,
> + (u16 *)&lif->info-
> >status.link_status);
> + debugfs_create_u32("link_speed", 0400, stats_dentry,
> + (u32 *)&lif->info-
> >status.link_speed);
> + debugfs_create_u16("link_down_count", 0400,
> stats_dentry,
> + (u16 *)&lif->info-
> >status.link_down_count);
> + }
> +
you never write to these lif->info->status.xyz ..
and link state and speed are/should be available in "ethtool <ifname>"
so this looks redundant to me. you can also use ethtool -S to report
linkdown count.
> return 0;
> }
>
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> index 19c046502a26..01f9665611d4 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> @@ -12,6 +12,8 @@
> #include "ionic_lif.h"
> #include "ionic_debugfs.h"
>
> +static int ionic_notifyq_clean(struct lif *lif, int budget);
> +
> static bool ionic_adminq_service(struct cq *cq, struct cq_info
> *cq_info)
> {
> struct admin_comp *comp = cq_info->cq_desc;
> @@ -26,7 +28,90 @@ static bool ionic_adminq_service(struct cq *cq,
> struct cq_info *cq_info)
>
> static int ionic_adminq_napi(struct napi_struct *napi, int budget)
> {
> - return ionic_napi(napi, budget, ionic_adminq_service, NULL,
> NULL);
> + struct lif *lif = napi_to_cq(napi)->lif;
> + int n_work = 0;
> + int a_work = 0;
> +
> + if (likely(lif->notifyqcq && lif->notifyqcq->flags &
> QCQ_F_INITED))
> + n_work = ionic_notifyq_clean(lif, budget);
> + a_work = ionic_napi(napi, budget, ionic_adminq_service, NULL,
> NULL);
> +
> + return max(n_work, a_work);
> +}
> +
> +static bool ionic_notifyq_service(struct cq *cq, struct cq_info
> *cq_info)
> +{
> + union notifyq_comp *comp = cq_info->cq_desc;
> + struct net_device *netdev;
> + struct queue *q;
> + struct lif *lif;
> + u64 eid;
> +
> + q = cq->bound_q;
> + lif = q->info[0].cb_arg;
> + netdev = lif->netdev;
> + eid = le64_to_cpu(comp->event.eid);
> +
> + /* Have we run out of new completions to process? */
> + if (eid <= lif->last_eid)
> + return false;
> +
> + lif->last_eid = eid;
> +
> + dev_dbg(lif->ionic->dev, "notifyq event:\n");
> + dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1,
> + comp, sizeof(*comp), true);
> +
> + switch (le16_to_cpu(comp->event.ecode)) {
> + case EVENT_OPCODE_LINK_CHANGE:
> + netdev_info(netdev, "Notifyq EVENT_OPCODE_LINK_CHANGE
> eid=%lld\n",
> + eid);
> + netdev_info(netdev,
> + " link_status=%d link_speed=%d\n",
> + le16_to_cpu(comp->link_change.link_status),
> + le32_to_cpu(comp->link_change.link_speed));
> + break;
> + case EVENT_OPCODE_RESET:
> + netdev_info(netdev, "Notifyq EVENT_OPCODE_RESET
> eid=%lld\n",
> + eid);
> + netdev_info(netdev, " reset_code=%d state=%d\n",
> + comp->reset.reset_code,
> + comp->reset.state);
> + break;
> + case EVENT_OPCODE_LOG:
> + netdev_info(netdev, "Notifyq EVENT_OPCODE_LOG
> eid=%lld\n", eid);
> + print_hex_dump(KERN_INFO, "notifyq ",
> DUMP_PREFIX_OFFSET, 16, 1,
> + comp->log.data, sizeof(comp->log.data),
> true);
So your device can generate log buffer dump into the kernel log ..
I am not sure how acceptable this is, maybe trace buffer is more
appropriate for this.
> + break;
> + default:
> + netdev_warn(netdev, "Notifyq unknown event ecode=%d
> eid=%lld\n",
> + comp->event.ecode, eid);
> + break;
> + }
> +
> + return true;
> +}
> +
> +static int ionic_notifyq_clean(struct lif *lif, int budget)
> +{
> + struct ionic_dev *idev = &lif->ionic->idev;
> + struct cq *cq = &lif->notifyqcq->cq;
> + u32 work_done;
> +
> + work_done = ionic_cq_service(cq, budget, ionic_notifyq_service,
> + NULL, NULL);
> + if (work_done)
> + ionic_intr_credits(idev->intr_ctrl, cq->bound_intr-
> >index,
> + work_done,
> IONIC_INTR_CRED_RESET_COALESCE);
> +
> + /* If we ran out of budget, there are more events
> + * to process and napi will reschedule us soon
> + */
> + if (work_done == budget)
> + goto return_to_napi;
> +
> +return_to_napi:
> + return work_done;
> }
>
> static irqreturn_t ionic_isr(int irq, void *data)
> @@ -62,6 +147,17 @@ static void ionic_intr_free(struct lif *lif, int
> index)
> clear_bit(index, lif->ionic->intrs);
> }
>
> +static void ionic_link_qcq_interrupts(struct qcq *src_qcq, struct
> qcq *n_qcq)
> +{
> + if (WARN_ON(n_qcq->flags & QCQ_F_INTR)) {
> + ionic_intr_free(n_qcq->cq.lif, n_qcq->intr.index);
> + n_qcq->flags &= ~QCQ_F_INTR;
> + }
> +
> + n_qcq->intr.vector = src_qcq->intr.vector;
> + n_qcq->intr.index = src_qcq->intr.index;
> +}
> +
> static int ionic_qcq_alloc(struct lif *lif, unsigned int type,
> unsigned int index,
> const char *name, unsigned int flags,
> @@ -236,11 +332,36 @@ static int ionic_qcqs_alloc(struct lif *lif)
> if (err)
> return err;
>
> + if (lif->ionic->nnqs_per_lif) {
> + flags = QCQ_F_NOTIFYQ;
> + err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0,
> "notifyq",
> + flags, IONIC_NOTIFYQ_LENGTH,
> + sizeof(struct notifyq_cmd),
> + sizeof(union notifyq_comp),
> + 0, lif->kern_pid, &lif-
> >notifyqcq);
> + if (err)
> + goto err_out_free_adminqcq;
> +
> + /* Let the notifyq ride on the adminq interrupt */
> + ionic_link_qcq_interrupts(lif->adminqcq, lif-
> >notifyqcq);
> + }
> +
> return 0;
> +
> +err_out_free_adminqcq:
> + ionic_qcq_free(lif, lif->adminqcq);
> + lif->adminqcq = NULL;
> +
> + return err;
> }
>
> static void ionic_qcqs_free(struct lif *lif)
> {
> + if (lif->notifyqcq) {
> + ionic_qcq_free(lif, lif->notifyqcq);
> + lif->notifyqcq = NULL;
> + }
> +
> if (lif->adminqcq) {
> ionic_qcq_free(lif, lif->adminqcq);
> lif->adminqcq = NULL;
> @@ -400,6 +521,7 @@ static void ionic_lif_deinit(struct lif *lif)
> clear_bit(LIF_INITED, lif->state);
>
> napi_disable(&lif->adminqcq->napi);
> + ionic_lif_qcq_deinit(lif, lif->notifyqcq);
> ionic_lif_qcq_deinit(lif, lif->adminqcq);
>
> ionic_lif_reset(lif);
> @@ -484,6 +606,55 @@ static int ionic_lif_adminq_init(struct lif
> *lif)
> return 0;
> }
>
> +static int ionic_lif_notifyq_init(struct lif *lif)
> +{
> + struct device *dev = lif->ionic->dev;
> + struct qcq *qcq = lif->notifyqcq;
> + struct queue *q = &qcq->q;
> + int err;
> +
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.q_init = {
> + .opcode = CMD_OPCODE_Q_INIT,
> + .lif_index = cpu_to_le16(lif->index),
> + .type = q->type,
> + .index = cpu_to_le32(q->index),
> + .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
> + IONIC_QINIT_F_ENA),
> + .intr_index = cpu_to_le16(lif->adminqcq-
> >intr.index),
> + .pid = cpu_to_le16(q->pid),
> + .ring_size = ilog2(q->num_descs),
> + .ring_base = cpu_to_le64(q->base_pa),
> + }
> + };
> +
> + dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid);
> + dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index);
> + dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n",
> ctx.cmd.q_init.ring_base);
> + dev_dbg(dev, "notifyq_init.ring_size %d\n",
> ctx.cmd.q_init.ring_size);
> +
> + err = ionic_adminq_post_wait(lif, &ctx);
> + if (err)
> + return err;
> +
> + q->hw_type = ctx.comp.q_init.hw_type;
> + q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
> + q->dbval = IONIC_DBELL_QID(q->hw_index);
> +
> + dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type);
> + dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index);
> +
> + /* preset the callback info */
> + q->info[0].cb_arg = lif;
> +
> + qcq->flags |= QCQ_F_INITED;
> +
> + ionic_debugfs_add_qcq(lif, qcq);
> +
> + return 0;
> +}
> +
> static int ionic_lif_init(struct lif *lif)
> {
> struct ionic_dev *idev = &lif->ionic->idev;
> @@ -534,10 +705,18 @@ static int ionic_lif_init(struct lif *lif)
> if (err)
> goto err_out_adminq_deinit;
>
> + if (lif->ionic->nnqs_per_lif) {
> + err = ionic_lif_notifyq_init(lif);
> + if (err)
> + goto err_out_notifyq_deinit;
> + }
> +
> set_bit(LIF_INITED, lif->state);
>
> return 0;
>
> +err_out_notifyq_deinit:
> + ionic_lif_qcq_deinit(lif, lif->notifyqcq);
> err_out_adminq_deinit:
> ionic_lif_qcq_deinit(lif, lif->adminqcq);
> ionic_lif_reset(lif);
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> index 28ab92b43a64..80eec0778f40 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> @@ -7,6 +7,7 @@
> #include <linux/pci.h>
>
> #define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */
> +#define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */
>
> #define GET_NAPI_CNTR_IDX(work_done) (work_done)
> #define MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1)
> @@ -26,6 +27,7 @@ struct rx_stats {
> #define QCQ_F_INITED BIT(0)
> #define QCQ_F_SG BIT(1)
> #define QCQ_F_INTR BIT(2)
> +#define QCQ_F_NOTIFYQ BIT(5)
>
> struct napi_stats {
> u64 poll_count;
> @@ -78,6 +80,8 @@ struct lif {
> u64 __iomem *kern_dbpage;
> spinlock_t adminq_lock; /* lock for AdminQ operations
> */
> struct qcq *adminqcq;
> + struct qcq *notifyqcq;
> + u64 last_eid;
> unsigned int neqs;
> unsigned int nxqs;
>
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 08/19] ionic: Add notifyq support
2019-07-24 23:21 ` Saeed Mahameed
@ 2019-07-30 18:35 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-30 18:35 UTC (permalink / raw)
To: Saeed Mahameed, netdev, davem
On 7/24/19 4:21 PM, Saeed Mahameed wrote:
> On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
>> The AdminQ is fine for sending messages and requests to the NIC,
>> but we also need to have events published from the NIC to the
>> driver. The NotifyQ handles this for us, using the same interrupt
>> as AdminQ.
>>
>> Signed-off-by: Shannon Nelson<snelson@pensando.io>
>> ---
>> .../ethernet/pensando/ionic/ionic_debugfs.c | 16 ++
>> .../net/ethernet/pensando/ionic/ionic_lif.c | 181
>> +++++++++++++++++-
>> .../net/ethernet/pensando/ionic/ionic_lif.h | 4 +
>> 3 files changed, 200 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
>> b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
>> index 9af15c69b2a6..1d05b23de303 100644
>> --- a/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
>> +++ b/drivers/net/ethernet/pensando/ionic/ionic_debugfs.c
>> @@ -126,6 +126,7 @@ int ionic_debugfs_add_qcq(struct lif *lif, struct
>> qcq *qcq)
>> struct debugfs_blob_wrapper *desc_blob;
>> struct device *dev = lif->ionic->dev;
>> struct intr *intr = &qcq->intr;
>> + struct dentry *stats_dentry;
>> struct queue *q = &qcq->q;
>> struct cq *cq = &qcq->cq;
>>
>> @@ -219,6 +220,21 @@ int ionic_debugfs_add_qcq(struct lif *lif,
>> struct qcq *qcq)
>> intr_ctrl_regset);
>> }
>>
>> + if (qcq->flags & QCQ_F_NOTIFYQ) {
>> + stats_dentry = debugfs_create_dir("notifyblock",
>> qcq_dentry);
>> + if (IS_ERR_OR_NULL(stats_dentry))
>> + return PTR_ERR(stats_dentry);
>> +
>> + debugfs_create_u64("eid", 0400, stats_dentry,
>> + (u64 *)&lif->info->status.eid);
>> + debugfs_create_u16("link_status", 0400, stats_dentry,
>> + (u16 *)&lif->info-
>>> status.link_status);
>> + debugfs_create_u32("link_speed", 0400, stats_dentry,
>> + (u32 *)&lif->info-
>>> status.link_speed);
>> + debugfs_create_u16("link_down_count", 0400,
>> stats_dentry,
>> + (u16 *)&lif->info-
>>> status.link_down_count);
>> + }
>> +
> you never write to these lif->info->status.xyz ..
This is data coming out of DMA memory from the nic, the driver only
reads it.
> and link state and speed are/should be available in "ethtool <ifname>"
> so this looks redundant to me. you can also use ethtool -S to report
> linkdown count.
The notifyblock is a chunk of data that usually stays together, but
isn't really something for ethtool -S, I'd prefer to leave this here.
[...]
>> + case EVENT_OPCODE_LOG:
>> + netdev_info(netdev, "Notifyq EVENT_OPCODE_LOG
>> eid=%lld\n", eid);
>> + print_hex_dump(KERN_INFO, "notifyq ",
>> DUMP_PREFIX_OFFSET, 16, 1,
>> + comp->log.data, sizeof(comp->log.data),
>> true);
> So your device can generate log buffer dump into the kernel log ..
> I am not sure how acceptable this is, maybe trace buffer is more
> appropriate for this.
It turns out that this early design feature has gone unused, so I'll
drop it out of here for now.
Thanks,
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 09/19] ionic: Add the basic NDO callbacks for netdev support
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (7 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 08/19] ionic: Add notifyq support Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-24 23:45 ` Saeed Mahameed
2019-07-22 21:40 ` [PATCH v4 net-next 10/19] ionic: Add management of rx filters Shannon Nelson
` (9 subsequent siblings)
18 siblings, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Set up the initial NDO structure and callbacks for netdev
to use, and register the netdev. This will allow us to do
a few basic operations on the device, but no traffic yet.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/ionic.h | 1 +
.../ethernet/pensando/ionic/ionic_bus_pci.c | 9 +
.../net/ethernet/pensando/ionic/ionic_dev.h | 2 +
.../net/ethernet/pensando/ionic/ionic_lif.c | 348 ++++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_lif.h | 5 +
5 files changed, 365 insertions(+)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
index 87ab13aee89e..d7eee79b2a10 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -34,6 +34,7 @@ struct ionic {
unsigned int num_bars;
struct identity ident;
struct list_head lifs;
+ struct lif *master_lif;
unsigned int nnqs_per_lif;
unsigned int neqs_per_lif;
unsigned int ntxqs_per_lif;
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
index 59d1ae7ce532..98c12b770c7f 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -206,8 +206,16 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
goto err_out_free_lifs;
}
+ err = ionic_lifs_register(ionic);
+ if (err) {
+ dev_err(dev, "Cannot register LIFs: %d, aborting\n", err);
+ goto err_out_deinit_lifs;
+ }
+
return 0;
+err_out_deinit_lifs:
+ ionic_lifs_deinit(ionic);
err_out_free_lifs:
ionic_lifs_free(ionic);
err_out_free_irqs:
@@ -239,6 +247,7 @@ static void ionic_remove(struct pci_dev *pdev)
struct ionic *ionic = pci_get_drvdata(pdev);
if (ionic) {
+ ionic_lifs_unregister(ionic);
ionic_lifs_deinit(ionic);
ionic_lifs_free(ionic);
ionic_bus_free_irq_vectors(ionic);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
index 8bd1501dd639..523927566925 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_dev.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
@@ -10,6 +10,8 @@
#include "ionic_if.h"
#include "ionic_regs.h"
+#define IONIC_MIN_MTU ETH_MIN_MTU
+#define IONIC_MAX_MTU 9194
#define IONIC_LIFS_MAX 1024
struct ionic_dev_bar {
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index 01f9665611d4..005b1d908fa1 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -12,8 +12,74 @@
#include "ionic_lif.h"
#include "ionic_debugfs.h"
+static int ionic_set_nic_features(struct lif *lif, netdev_features_t features);
static int ionic_notifyq_clean(struct lif *lif, int budget);
+int ionic_open(struct net_device *netdev)
+{
+ struct lif *lif = netdev_priv(netdev);
+
+ netif_carrier_off(netdev);
+
+ set_bit(LIF_UP, lif->state);
+
+ if (netif_carrier_ok(netdev))
+ netif_tx_wake_all_queues(netdev);
+
+ return 0;
+}
+
+static int ionic_lif_stop(struct lif *lif)
+{
+ struct net_device *ndev = lif->netdev;
+ int err = 0;
+
+ if (!test_bit(LIF_UP, lif->state)) {
+ dev_dbg(lif->ionic->dev, "%s: %s state=DOWN\n",
+ __func__, lif->name);
+ return 0;
+ }
+ dev_dbg(lif->ionic->dev, "%s: %s state=UP\n", __func__, lif->name);
+ clear_bit(LIF_UP, lif->state);
+
+ /* carrier off before disabling queues to avoid watchdog timeout */
+ netif_carrier_off(ndev);
+ netif_tx_stop_all_queues(ndev);
+ netif_tx_disable(ndev);
+ synchronize_rcu();
+
+ return err;
+}
+
+int ionic_stop(struct net_device *netdev)
+{
+ struct lif *lif = netdev_priv(netdev);
+
+ return ionic_lif_stop(lif);
+}
+
+int ionic_reset_queues(struct lif *lif)
+{
+ bool running;
+ int err = 0;
+
+ /* Put off the next watchdog timeout */
+ netif_trans_update(lif->netdev);
+
+ while (test_and_set_bit(LIF_QUEUE_RESET, lif->state))
+ usleep_range(100, 200);
+
+ running = netif_running(lif->netdev);
+ if (running)
+ err = ionic_stop(lif->netdev);
+ if (!err && running)
+ ionic_open(lif->netdev);
+
+ clear_bit(LIF_QUEUE_RESET, lif->state);
+
+ return err;
+}
+
static bool ionic_adminq_service(struct cq *cq, struct cq_info *cq_info)
{
struct admin_comp *comp = cq_info->cq_desc;
@@ -114,6 +180,81 @@ static int ionic_notifyq_clean(struct lif *lif, int budget)
return work_done;
}
+static int ionic_set_features(struct net_device *netdev,
+ netdev_features_t features)
+{
+ struct lif *lif = netdev_priv(netdev);
+ int err;
+
+ netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n",
+ __func__, (u64)lif->netdev->features, (u64)features);
+
+ err = ionic_set_nic_features(lif, features);
+
+ return err;
+}
+
+static int ionic_set_mac_address(struct net_device *netdev, void *sa)
+{
+ netdev_info(netdev, "%s: stubbed\n", __func__);
+ return 0;
+}
+
+static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.lif_setattr = {
+ .opcode = CMD_OPCODE_LIF_SETATTR,
+ .index = cpu_to_le16(lif->index),
+ .attr = IONIC_LIF_ATTR_MTU,
+ .mtu = cpu_to_le32(new_mtu),
+ },
+ };
+ int err;
+
+ err = ionic_adminq_post_wait(lif, &ctx);
+ if (err)
+ return err;
+
+ netdev->mtu = new_mtu;
+ err = ionic_reset_queues(lif);
+
+ return err;
+}
+
+static void ionic_tx_timeout(struct net_device *netdev)
+{
+ netdev_info(netdev, "%s: stubbed\n", __func__);
+}
+
+static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
+ u16 vid)
+{
+ netdev_info(netdev, "%s: stubbed\n", __func__);
+ return 0;
+}
+
+static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
+ u16 vid)
+{
+ netdev_info(netdev, "%s: stubbed\n", __func__);
+ return 0;
+}
+
+static const struct net_device_ops ionic_netdev_ops = {
+ .ndo_open = ionic_open,
+ .ndo_stop = ionic_stop,
+ .ndo_set_features = ionic_set_features,
+ .ndo_set_mac_address = ionic_set_mac_address,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_tx_timeout = ionic_tx_timeout,
+ .ndo_change_mtu = ionic_change_mtu,
+ .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid,
+ .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid,
+};
+
static irqreturn_t ionic_isr(int irq, void *data)
{
struct napi_struct *napi = data;
@@ -388,6 +529,12 @@ static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
lif = netdev_priv(netdev);
lif->netdev = netdev;
+ ionic->master_lif = lif;
+ netdev->netdev_ops = &ionic_netdev_ops;
+
+ netdev->watchdog_timeo = 2 * HZ;
+ netdev->min_mtu = IONIC_MIN_MTU;
+ netdev->max_mtu = IONIC_MAX_MTU;
lif->neqs = ionic->neqs_per_lif;
lif->nxqs = ionic->ntxqs_per_lif;
@@ -655,6 +802,177 @@ static int ionic_lif_notifyq_init(struct lif *lif)
return 0;
}
+static __le64 ionic_netdev_features_to_nic(netdev_features_t features)
+{
+ u64 wanted = 0;
+
+ if (features & NETIF_F_HW_VLAN_CTAG_TX)
+ wanted |= ETH_HW_VLAN_TX_TAG;
+ if (features & NETIF_F_HW_VLAN_CTAG_RX)
+ wanted |= ETH_HW_VLAN_RX_STRIP;
+ if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
+ wanted |= ETH_HW_VLAN_RX_FILTER;
+ if (features & NETIF_F_RXHASH)
+ wanted |= ETH_HW_RX_HASH;
+ if (features & NETIF_F_RXCSUM)
+ wanted |= ETH_HW_RX_CSUM;
+ if (features & NETIF_F_SG)
+ wanted |= ETH_HW_TX_SG;
+ if (features & NETIF_F_HW_CSUM)
+ wanted |= ETH_HW_TX_CSUM;
+ if (features & NETIF_F_TSO)
+ wanted |= ETH_HW_TSO;
+ if (features & NETIF_F_TSO6)
+ wanted |= ETH_HW_TSO_IPV6;
+ if (features & NETIF_F_TSO_ECN)
+ wanted |= ETH_HW_TSO_ECN;
+ if (features & NETIF_F_GSO_GRE)
+ wanted |= ETH_HW_TSO_GRE;
+ if (features & NETIF_F_GSO_GRE_CSUM)
+ wanted |= ETH_HW_TSO_GRE_CSUM;
+ if (features & NETIF_F_GSO_IPXIP4)
+ wanted |= ETH_HW_TSO_IPXIP4;
+ if (features & NETIF_F_GSO_IPXIP6)
+ wanted |= ETH_HW_TSO_IPXIP6;
+ if (features & NETIF_F_GSO_UDP_TUNNEL)
+ wanted |= ETH_HW_TSO_UDP;
+ if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM)
+ wanted |= ETH_HW_TSO_UDP_CSUM;
+
+ return cpu_to_le64(wanted);
+}
+
+static int ionic_set_nic_features(struct lif *lif, netdev_features_t features)
+{
+ struct device *dev = lif->ionic->dev;
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.lif_setattr = {
+ .opcode = CMD_OPCODE_LIF_SETATTR,
+ .index = cpu_to_le16(lif->index),
+ .attr = IONIC_LIF_ATTR_FEATURES,
+ },
+ };
+ u64 vlan_flags = ETH_HW_VLAN_TX_TAG |
+ ETH_HW_VLAN_RX_STRIP |
+ ETH_HW_VLAN_RX_FILTER;
+ int err;
+
+ ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features);
+ err = ionic_adminq_post_wait(lif, &ctx);
+ if (err)
+ return err;
+
+ lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features &
+ ctx.comp.lif_setattr.features);
+
+ if ((vlan_flags & features) &&
+ !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features)))
+ dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n");
+
+ if (lif->hw_features & ETH_HW_VLAN_TX_TAG)
+ dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n");
+ if (lif->hw_features & ETH_HW_VLAN_RX_STRIP)
+ dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n");
+ if (lif->hw_features & ETH_HW_VLAN_RX_FILTER)
+ dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n");
+ if (lif->hw_features & ETH_HW_RX_HASH)
+ dev_dbg(dev, "feature ETH_HW_RX_HASH\n");
+ if (lif->hw_features & ETH_HW_TX_SG)
+ dev_dbg(dev, "feature ETH_HW_TX_SG\n");
+ if (lif->hw_features & ETH_HW_TX_CSUM)
+ dev_dbg(dev, "feature ETH_HW_TX_CSUM\n");
+ if (lif->hw_features & ETH_HW_RX_CSUM)
+ dev_dbg(dev, "feature ETH_HW_RX_CSUM\n");
+ if (lif->hw_features & ETH_HW_TSO)
+ dev_dbg(dev, "feature ETH_HW_TSO\n");
+ if (lif->hw_features & ETH_HW_TSO_IPV6)
+ dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n");
+ if (lif->hw_features & ETH_HW_TSO_ECN)
+ dev_dbg(dev, "feature ETH_HW_TSO_ECN\n");
+ if (lif->hw_features & ETH_HW_TSO_GRE)
+ dev_dbg(dev, "feature ETH_HW_TSO_GRE\n");
+ if (lif->hw_features & ETH_HW_TSO_GRE_CSUM)
+ dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n");
+ if (lif->hw_features & ETH_HW_TSO_IPXIP4)
+ dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n");
+ if (lif->hw_features & ETH_HW_TSO_IPXIP6)
+ dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n");
+ if (lif->hw_features & ETH_HW_TSO_UDP)
+ dev_dbg(dev, "feature ETH_HW_TSO_UDP\n");
+ if (lif->hw_features & ETH_HW_TSO_UDP_CSUM)
+ dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n");
+
+ return 0;
+}
+
+static int ionic_init_nic_features(struct lif *lif)
+{
+ struct net_device *netdev = lif->netdev;
+ netdev_features_t features;
+ int err;
+
+ /* set up what we expect to support by default */
+ features = NETIF_F_HW_VLAN_CTAG_TX |
+ NETIF_F_HW_VLAN_CTAG_RX |
+ NETIF_F_HW_VLAN_CTAG_FILTER |
+ NETIF_F_RXHASH |
+ NETIF_F_SG |
+ NETIF_F_HW_CSUM |
+ NETIF_F_RXCSUM |
+ NETIF_F_TSO |
+ NETIF_F_TSO6 |
+ NETIF_F_TSO_ECN;
+
+ err = ionic_set_nic_features(lif, features);
+ if (err)
+ return err;
+
+ /* tell the netdev what we actually can support */
+ netdev->features |= NETIF_F_HIGHDMA;
+
+ if (lif->hw_features & ETH_HW_VLAN_TX_TAG)
+ netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
+ if (lif->hw_features & ETH_HW_VLAN_RX_STRIP)
+ netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
+ if (lif->hw_features & ETH_HW_VLAN_RX_FILTER)
+ netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
+ if (lif->hw_features & ETH_HW_RX_HASH)
+ netdev->hw_features |= NETIF_F_RXHASH;
+ if (lif->hw_features & ETH_HW_TX_SG)
+ netdev->hw_features |= NETIF_F_SG;
+
+ if (lif->hw_features & ETH_HW_TX_CSUM)
+ netdev->hw_enc_features |= NETIF_F_HW_CSUM;
+ if (lif->hw_features & ETH_HW_RX_CSUM)
+ netdev->hw_enc_features |= NETIF_F_RXCSUM;
+ if (lif->hw_features & ETH_HW_TSO)
+ netdev->hw_enc_features |= NETIF_F_TSO;
+ if (lif->hw_features & ETH_HW_TSO_IPV6)
+ netdev->hw_enc_features |= NETIF_F_TSO6;
+ if (lif->hw_features & ETH_HW_TSO_ECN)
+ netdev->hw_enc_features |= NETIF_F_TSO_ECN;
+ if (lif->hw_features & ETH_HW_TSO_GRE)
+ netdev->hw_enc_features |= NETIF_F_GSO_GRE;
+ if (lif->hw_features & ETH_HW_TSO_GRE_CSUM)
+ netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM;
+ if (lif->hw_features & ETH_HW_TSO_IPXIP4)
+ netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4;
+ if (lif->hw_features & ETH_HW_TSO_IPXIP6)
+ netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6;
+ if (lif->hw_features & ETH_HW_TSO_UDP)
+ netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
+ if (lif->hw_features & ETH_HW_TSO_UDP_CSUM)
+ netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
+
+ netdev->hw_features |= netdev->hw_enc_features;
+ netdev->features |= netdev->hw_features;
+
+ netdev->priv_flags |= IFF_UNICAST_FLT;
+
+ return 0;
+}
+
static int ionic_lif_init(struct lif *lif)
{
struct ionic_dev *idev = &lif->ionic->idev;
@@ -711,6 +1029,10 @@ static int ionic_lif_init(struct lif *lif)
goto err_out_notifyq_deinit;
}
+ err = ionic_init_nic_features(lif);
+ if (err)
+ goto err_out_notifyq_deinit;
+
set_bit(LIF_INITED, lif->state);
return 0;
@@ -745,6 +1067,32 @@ int ionic_lifs_init(struct ionic *ionic)
return 0;
}
+int ionic_lifs_register(struct ionic *ionic)
+{
+ int err;
+
+ /* only register LIF0 for now */
+ err = register_netdev(ionic->master_lif->netdev);
+ if (err) {
+ dev_err(ionic->dev, "Cannot register net device, aborting\n");
+ return err;
+ }
+
+ ionic->master_lif->registered = true;
+
+ return 0;
+}
+
+void ionic_lifs_unregister(struct ionic *ionic)
+{
+ /* There is only one lif ever registered in the
+ * current model, so don't bother searching the
+ * ionic->lif for candidates to unregister
+ */
+ if (ionic->master_lif->netdev->reg_state == NETREG_REGISTERED)
+ unregister_netdev(ionic->master_lif->netdev);
+}
+
int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
union lif_identity *lid)
{
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index 80eec0778f40..ef3f7340a277 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -61,6 +61,8 @@ struct qcq {
enum lif_state_flags {
LIF_INITED,
+ LIF_UP,
+ LIF_QUEUE_RESET,
/* leave this as last */
LIF_STATE_SIZE
@@ -84,6 +86,7 @@ struct lif {
u64 last_eid;
unsigned int neqs;
unsigned int nxqs;
+ u64 hw_features;
struct lif_info *info;
dma_addr_t info_pa;
@@ -124,6 +127,8 @@ int ionic_lifs_alloc(struct ionic *ionic);
void ionic_lifs_free(struct ionic *ionic);
void ionic_lifs_deinit(struct ionic *ionic);
int ionic_lifs_init(struct ionic *ionic);
+int ionic_lifs_register(struct ionic *ionic);
+void ionic_lifs_unregister(struct ionic *ionic);
int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
union lif_identity *lif_ident);
int ionic_lifs_size(struct ionic *ionic);
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 09/19] ionic: Add the basic NDO callbacks for netdev support
2019-07-22 21:40 ` [PATCH v4 net-next 09/19] ionic: Add the basic NDO callbacks for netdev support Shannon Nelson
@ 2019-07-24 23:45 ` Saeed Mahameed
2019-07-30 18:35 ` Shannon Nelson
0 siblings, 1 reply; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-24 23:45 UTC (permalink / raw)
To: snelson, netdev, davem
On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> Set up the initial NDO structure and callbacks for netdev
> to use, and register the netdev. This will allow us to do
> a few basic operations on the device, but no traffic yet.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
> ---
> drivers/net/ethernet/pensando/ionic/ionic.h | 1 +
> .../ethernet/pensando/ionic/ionic_bus_pci.c | 9 +
> .../net/ethernet/pensando/ionic/ionic_dev.h | 2 +
> .../net/ethernet/pensando/ionic/ionic_lif.c | 348
> ++++++++++++++++++
> .../net/ethernet/pensando/ionic/ionic_lif.h | 5 +
> 5 files changed, 365 insertions(+)
>
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h
> b/drivers/net/ethernet/pensando/ionic/ionic.h
> index 87ab13aee89e..d7eee79b2a10 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic.h
> @@ -34,6 +34,7 @@ struct ionic {
> unsigned int num_bars;
> struct identity ident;
> struct list_head lifs;
> + struct lif *master_lif;
> unsigned int nnqs_per_lif;
> unsigned int neqs_per_lif;
> unsigned int ntxqs_per_lif;
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
> b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
> index 59d1ae7ce532..98c12b770c7f 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
> @@ -206,8 +206,16 @@ static int ionic_probe(struct pci_dev *pdev,
> const struct pci_device_id *ent)
> goto err_out_free_lifs;
> }
>
> + err = ionic_lifs_register(ionic);
> + if (err) {
> + dev_err(dev, "Cannot register LIFs: %d, aborting\n",
> err);
> + goto err_out_deinit_lifs;
> + }
> +
> return 0;
>
> +err_out_deinit_lifs:
> + ionic_lifs_deinit(ionic);
> err_out_free_lifs:
> ionic_lifs_free(ionic);
> err_out_free_irqs:
> @@ -239,6 +247,7 @@ static void ionic_remove(struct pci_dev *pdev)
> struct ionic *ionic = pci_get_drvdata(pdev);
>
> if (ionic) {
> + ionic_lifs_unregister(ionic);
> ionic_lifs_deinit(ionic);
> ionic_lifs_free(ionic);
> ionic_bus_free_irq_vectors(ionic);
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h
> b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
> index 8bd1501dd639..523927566925 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_dev.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
> @@ -10,6 +10,8 @@
> #include "ionic_if.h"
> #include "ionic_regs.h"
>
> +#define IONIC_MIN_MTU ETH_MIN_MTU
> +#define IONIC_MAX_MTU 9194
> #define IONIC_LIFS_MAX 1024
>
> struct ionic_dev_bar {
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> index 01f9665611d4..005b1d908fa1 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> @@ -12,8 +12,74 @@
> #include "ionic_lif.h"
> #include "ionic_debugfs.h"
>
> +static int ionic_set_nic_features(struct lif *lif, netdev_features_t
> features);
> static int ionic_notifyq_clean(struct lif *lif, int budget);
>
> +int ionic_open(struct net_device *netdev)
> +{
> + struct lif *lif = netdev_priv(netdev);
> +
> + netif_carrier_off(netdev);
> +
> + set_bit(LIF_UP, lif->state);
> +
> + if (netif_carrier_ok(netdev))
always false ? you just invoked netif_carrier_off two lines ago..
> + netif_tx_wake_all_queues(netdev);
> +
> + return 0;
> +}
> +
> +static int ionic_lif_stop(struct lif *lif)
> +{
> + struct net_device *ndev = lif->netdev;
> + int err = 0;
> +
> + if (!test_bit(LIF_UP, lif->state)) {
> + dev_dbg(lif->ionic->dev, "%s: %s state=DOWN\n",
> + __func__, lif->name);
> + return 0;
> + }
> + dev_dbg(lif->ionic->dev, "%s: %s state=UP\n", __func__, lif-
> >name);
> + clear_bit(LIF_UP, lif->state);
> +
> + /* carrier off before disabling queues to avoid watchdog
> timeout */
> + netif_carrier_off(ndev);
> + netif_tx_stop_all_queues(ndev);
> + netif_tx_disable(ndev);
> + synchronize_rcu();
why synchronize_rcu ?
> +
> + return err;
> +}
> +
> +int ionic_stop(struct net_device *netdev)
> +{
> + struct lif *lif = netdev_priv(netdev);
> +
> + return ionic_lif_stop(lif);
> +}
> +
> +int ionic_reset_queues(struct lif *lif)
> +{
> + bool running;
> + int err = 0;
> +
> + /* Put off the next watchdog timeout */
> + netif_trans_update(lif->netdev);
this doesn't seem right to me also this won't help you if the next
while loop takes too long.. also netif_trans_update is marked to be
only used for legacy drivers.
> +
> + while (test_and_set_bit(LIF_QUEUE_RESET, lif->state))
> + usleep_range(100, 200);
> +
> + running = netif_running(lif->netdev);
> + if (running)
> + err = ionic_stop(lif->netdev);
> + if (!err && running)
> + ionic_open(lif->netdev);
> +
> + clear_bit(LIF_QUEUE_RESET, lif->state);
> +
> + return err;
> +}
> +
> static bool ionic_adminq_service(struct cq *cq, struct cq_info
> *cq_info)
> {
> struct admin_comp *comp = cq_info->cq_desc;
> @@ -114,6 +180,81 @@ static int ionic_notifyq_clean(struct lif *lif,
> int budget)
> return work_done;
> }
>
> +static int ionic_set_features(struct net_device *netdev,
> + netdev_features_t features)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + int err;
> +
> + netdev_dbg(netdev, "%s: lif->features=0x%08llx
> new_features=0x%08llx\n",
> + __func__, (u64)lif->netdev->features,
> (u64)features);
> +
> + err = ionic_set_nic_features(lif, features);
> +
> + return err;
> +}
> +
> +static int ionic_set_mac_address(struct net_device *netdev, void
> *sa)
> +{
> + netdev_info(netdev, "%s: stubbed\n", __func__);
> + return 0;
> +}
> +
> +static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.lif_setattr = {
> + .opcode = CMD_OPCODE_LIF_SETATTR,
> + .index = cpu_to_le16(lif->index),
> + .attr = IONIC_LIF_ATTR_MTU,
> + .mtu = cpu_to_le32(new_mtu),
> + },
> + };
> + int err;
> +
> + err = ionic_adminq_post_wait(lif, &ctx);
> + if (err)
> + return err;
> +
> + netdev->mtu = new_mtu;
> + err = ionic_reset_queues(lif);
> +
> + return err;
> +}
> +
> +static void ionic_tx_timeout(struct net_device *netdev)
> +{
> + netdev_info(netdev, "%s: stubbed\n", __func__);
> +}
> +
> +static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16
> proto,
> + u16 vid)
> +{
> + netdev_info(netdev, "%s: stubbed\n", __func__);
> + return 0;
> +}
> +
> +static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16
> proto,
> + u16 vid)
> +{
> + netdev_info(netdev, "%s: stubbed\n", __func__);
> + return 0;
> +}
> +
> +static const struct net_device_ops ionic_netdev_ops = {
> + .ndo_open = ionic_open,
> + .ndo_stop = ionic_stop,
> + .ndo_set_features = ionic_set_features,
> + .ndo_set_mac_address = ionic_set_mac_address,
> + .ndo_validate_addr = eth_validate_addr,
> + .ndo_tx_timeout = ionic_tx_timeout,
> + .ndo_change_mtu = ionic_change_mtu,
> + .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid,
> + .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid,
> +};
> +
> static irqreturn_t ionic_isr(int irq, void *data)
> {
> struct napi_struct *napi = data;
> @@ -388,6 +529,12 @@ static struct lif *ionic_lif_alloc(struct ionic
> *ionic, unsigned int index)
>
> lif = netdev_priv(netdev);
> lif->netdev = netdev;
> + ionic->master_lif = lif;
> + netdev->netdev_ops = &ionic_netdev_ops;
> +
> + netdev->watchdog_timeo = 2 * HZ;
> + netdev->min_mtu = IONIC_MIN_MTU;
> + netdev->max_mtu = IONIC_MAX_MTU;
>
> lif->neqs = ionic->neqs_per_lif;
> lif->nxqs = ionic->ntxqs_per_lif;
> @@ -655,6 +802,177 @@ static int ionic_lif_notifyq_init(struct lif
> *lif)
> return 0;
> }
>
> +static __le64 ionic_netdev_features_to_nic(netdev_features_t
> features)
> +{
> + u64 wanted = 0;
> +
> + if (features & NETIF_F_HW_VLAN_CTAG_TX)
> + wanted |= ETH_HW_VLAN_TX_TAG;
> + if (features & NETIF_F_HW_VLAN_CTAG_RX)
> + wanted |= ETH_HW_VLAN_RX_STRIP;
> + if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
> + wanted |= ETH_HW_VLAN_RX_FILTER;
> + if (features & NETIF_F_RXHASH)
> + wanted |= ETH_HW_RX_HASH;
> + if (features & NETIF_F_RXCSUM)
> + wanted |= ETH_HW_RX_CSUM;
> + if (features & NETIF_F_SG)
> + wanted |= ETH_HW_TX_SG;
> + if (features & NETIF_F_HW_CSUM)
> + wanted |= ETH_HW_TX_CSUM;
> + if (features & NETIF_F_TSO)
> + wanted |= ETH_HW_TSO;
> + if (features & NETIF_F_TSO6)
> + wanted |= ETH_HW_TSO_IPV6;
> + if (features & NETIF_F_TSO_ECN)
> + wanted |= ETH_HW_TSO_ECN;
> + if (features & NETIF_F_GSO_GRE)
> + wanted |= ETH_HW_TSO_GRE;
> + if (features & NETIF_F_GSO_GRE_CSUM)
> + wanted |= ETH_HW_TSO_GRE_CSUM;
> + if (features & NETIF_F_GSO_IPXIP4)
> + wanted |= ETH_HW_TSO_IPXIP4;
> + if (features & NETIF_F_GSO_IPXIP6)
> + wanted |= ETH_HW_TSO_IPXIP6;
> + if (features & NETIF_F_GSO_UDP_TUNNEL)
> + wanted |= ETH_HW_TSO_UDP;
> + if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM)
> + wanted |= ETH_HW_TSO_UDP_CSUM;
> +
> + return cpu_to_le64(wanted);
> +}
> +
> +static int ionic_set_nic_features(struct lif *lif, netdev_features_t
> features)
> +{
> + struct device *dev = lif->ionic->dev;
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.lif_setattr = {
> + .opcode = CMD_OPCODE_LIF_SETATTR,
> + .index = cpu_to_le16(lif->index),
> + .attr = IONIC_LIF_ATTR_FEATURES,
> + },
> + };
> + u64 vlan_flags = ETH_HW_VLAN_TX_TAG |
> + ETH_HW_VLAN_RX_STRIP |
> + ETH_HW_VLAN_RX_FILTER;
> + int err;
> +
> + ctx.cmd.lif_setattr.features =
> ionic_netdev_features_to_nic(features);
> + err = ionic_adminq_post_wait(lif, &ctx);
> + if (err)
> + return err;
> +
> + lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features &
> + ctx.comp.lif_setattr.features);
> +
> + if ((vlan_flags & features) &&
> + !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features)))
> + dev_info_once(lif->ionic->dev, "NIC is not supporting
> vlan offload, likely in SmartNIC mode\n");
> +
> + if (lif->hw_features & ETH_HW_VLAN_TX_TAG)
> + dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n");
> + if (lif->hw_features & ETH_HW_VLAN_RX_STRIP)
> + dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n");
> + if (lif->hw_features & ETH_HW_VLAN_RX_FILTER)
> + dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n");
> + if (lif->hw_features & ETH_HW_RX_HASH)
> + dev_dbg(dev, "feature ETH_HW_RX_HASH\n");
> + if (lif->hw_features & ETH_HW_TX_SG)
> + dev_dbg(dev, "feature ETH_HW_TX_SG\n");
> + if (lif->hw_features & ETH_HW_TX_CSUM)
> + dev_dbg(dev, "feature ETH_HW_TX_CSUM\n");
> + if (lif->hw_features & ETH_HW_RX_CSUM)
> + dev_dbg(dev, "feature ETH_HW_RX_CSUM\n");
> + if (lif->hw_features & ETH_HW_TSO)
> + dev_dbg(dev, "feature ETH_HW_TSO\n");
> + if (lif->hw_features & ETH_HW_TSO_IPV6)
> + dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n");
> + if (lif->hw_features & ETH_HW_TSO_ECN)
> + dev_dbg(dev, "feature ETH_HW_TSO_ECN\n");
> + if (lif->hw_features & ETH_HW_TSO_GRE)
> + dev_dbg(dev, "feature ETH_HW_TSO_GRE\n");
> + if (lif->hw_features & ETH_HW_TSO_GRE_CSUM)
> + dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n");
> + if (lif->hw_features & ETH_HW_TSO_IPXIP4)
> + dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n");
> + if (lif->hw_features & ETH_HW_TSO_IPXIP6)
> + dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n");
> + if (lif->hw_features & ETH_HW_TSO_UDP)
> + dev_dbg(dev, "feature ETH_HW_TSO_UDP\n");
> + if (lif->hw_features & ETH_HW_TSO_UDP_CSUM)
> + dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n");
> +
> + return 0;
> +}
> +
> +static int ionic_init_nic_features(struct lif *lif)
> +{
> + struct net_device *netdev = lif->netdev;
> + netdev_features_t features;
> + int err;
> +
> + /* set up what we expect to support by default */
> + features = NETIF_F_HW_VLAN_CTAG_TX |
> + NETIF_F_HW_VLAN_CTAG_RX |
> + NETIF_F_HW_VLAN_CTAG_FILTER |
> + NETIF_F_RXHASH |
> + NETIF_F_SG |
> + NETIF_F_HW_CSUM |
> + NETIF_F_RXCSUM |
> + NETIF_F_TSO |
> + NETIF_F_TSO6 |
> + NETIF_F_TSO_ECN;
> +
> + err = ionic_set_nic_features(lif, features);
> + if (err)
> + return err;
> +
> + /* tell the netdev what we actually can support */
> + netdev->features |= NETIF_F_HIGHDMA;
> +
> + if (lif->hw_features & ETH_HW_VLAN_TX_TAG)
> + netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
> + if (lif->hw_features & ETH_HW_VLAN_RX_STRIP)
> + netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
> + if (lif->hw_features & ETH_HW_VLAN_RX_FILTER)
> + netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
> + if (lif->hw_features & ETH_HW_RX_HASH)
> + netdev->hw_features |= NETIF_F_RXHASH;
> + if (lif->hw_features & ETH_HW_TX_SG)
> + netdev->hw_features |= NETIF_F_SG;
> +
> + if (lif->hw_features & ETH_HW_TX_CSUM)
> + netdev->hw_enc_features |= NETIF_F_HW_CSUM;
> + if (lif->hw_features & ETH_HW_RX_CSUM)
> + netdev->hw_enc_features |= NETIF_F_RXCSUM;
> + if (lif->hw_features & ETH_HW_TSO)
> + netdev->hw_enc_features |= NETIF_F_TSO;
> + if (lif->hw_features & ETH_HW_TSO_IPV6)
> + netdev->hw_enc_features |= NETIF_F_TSO6;
> + if (lif->hw_features & ETH_HW_TSO_ECN)
> + netdev->hw_enc_features |= NETIF_F_TSO_ECN;
> + if (lif->hw_features & ETH_HW_TSO_GRE)
> + netdev->hw_enc_features |= NETIF_F_GSO_GRE;
> + if (lif->hw_features & ETH_HW_TSO_GRE_CSUM)
> + netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM;
> + if (lif->hw_features & ETH_HW_TSO_IPXIP4)
> + netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4;
> + if (lif->hw_features & ETH_HW_TSO_IPXIP6)
> + netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6;
> + if (lif->hw_features & ETH_HW_TSO_UDP)
> + netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
> + if (lif->hw_features & ETH_HW_TSO_UDP_CSUM)
> + netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
> +
> + netdev->hw_features |= netdev->hw_enc_features;
> + netdev->features |= netdev->hw_features;
> +
> + netdev->priv_flags |= IFF_UNICAST_FLT;
> +
> + return 0;
> +}
> +
> static int ionic_lif_init(struct lif *lif)
> {
> struct ionic_dev *idev = &lif->ionic->idev;
> @@ -711,6 +1029,10 @@ static int ionic_lif_init(struct lif *lif)
> goto err_out_notifyq_deinit;
> }
>
> + err = ionic_init_nic_features(lif);
> + if (err)
> + goto err_out_notifyq_deinit;
> +
> set_bit(LIF_INITED, lif->state);
>
> return 0;
> @@ -745,6 +1067,32 @@ int ionic_lifs_init(struct ionic *ionic)
> return 0;
> }
>
> +int ionic_lifs_register(struct ionic *ionic)
> +{
> + int err;
> +
> + /* only register LIF0 for now */
> + err = register_netdev(ionic->master_lif->netdev);
> + if (err) {
> + dev_err(ionic->dev, "Cannot register net device,
> aborting\n");
> + return err;
> + }
> +
> + ionic->master_lif->registered = true;
> +
> + return 0;
> +}
> +
> +void ionic_lifs_unregister(struct ionic *ionic)
> +{
> + /* There is only one lif ever registered in the
> + * current model, so don't bother searching the
> + * ionic->lif for candidates to unregister
> + */
> + if (ionic->master_lif->netdev->reg_state == NETREG_REGISTERED)
> + unregister_netdev(ionic->master_lif->netdev);
> +}
> +
> int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
> union lif_identity *lid)
> {
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> index 80eec0778f40..ef3f7340a277 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> @@ -61,6 +61,8 @@ struct qcq {
>
> enum lif_state_flags {
> LIF_INITED,
> + LIF_UP,
> + LIF_QUEUE_RESET,
>
> /* leave this as last */
> LIF_STATE_SIZE
> @@ -84,6 +86,7 @@ struct lif {
> u64 last_eid;
> unsigned int neqs;
> unsigned int nxqs;
> + u64 hw_features;
>
> struct lif_info *info;
> dma_addr_t info_pa;
> @@ -124,6 +127,8 @@ int ionic_lifs_alloc(struct ionic *ionic);
> void ionic_lifs_free(struct ionic *ionic);
> void ionic_lifs_deinit(struct ionic *ionic);
> int ionic_lifs_init(struct ionic *ionic);
> +int ionic_lifs_register(struct ionic *ionic);
> +void ionic_lifs_unregister(struct ionic *ionic);
> int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
> union lif_identity *lif_ident);
> int ionic_lifs_size(struct ionic *ionic);
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 09/19] ionic: Add the basic NDO callbacks for netdev support
2019-07-24 23:45 ` Saeed Mahameed
@ 2019-07-30 18:35 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-30 18:35 UTC (permalink / raw)
To: Saeed Mahameed, netdev, davem
On 7/24/19 4:45 PM, Saeed Mahameed wrote:
> On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
>> Set up the initial NDO structure and callbacks for netdev
>> to use, and register the netdev. This will allow us to do
>> a few basic operations on the device, but no traffic yet.
>>
>> Signed-off-by: Shannon Nelson<snelson@pensando.io>
>> ---
>> drivers/net/ethernet/pensando/ionic/ionic.h | 1 +
>> .../ethernet/pensando/ionic/ionic_bus_pci.c | 9 +
>> .../net/ethernet/pensando/ionic/ionic_dev.h | 2 +
>> .../net/ethernet/pensando/ionic/ionic_lif.c | 348
>> ++++++++++++++++++
>> .../net/ethernet/pensando/ionic/ionic_lif.h | 5 +
>> 5 files changed, 365 insertions(+)
>>
[...]
>>
>> +static int ionic_set_nic_features(struct lif *lif, netdev_features_t
>> features);
>> static int ionic_notifyq_clean(struct lif *lif, int budget);
>>
>> +int ionic_open(struct net_device *netdev)
>> +{
>> + struct lif *lif = netdev_priv(netdev);
>> +
>> + netif_carrier_off(netdev);
>> +
>> + set_bit(LIF_UP, lif->state);
>> +
>> + if (netif_carrier_ok(netdev))
> always false ? you just invoked netif_carrier_off two lines ago..
Hmmm... an artifact of splitting up an existing driver. This makes more
sense when there's a link status check in between these, which comes in
about 3 patches later. Unless this really causes someone significant
heartburn, I'm going to leave this as is for now.
>> + netif_tx_wake_all_queues(netdev);
>> +
>> + return 0;
>> +}
>> +
>> +static int ionic_lif_stop(struct lif *lif)
>> +{
>> + struct net_device *ndev = lif->netdev;
>> + int err = 0;
>> +
>> + if (!test_bit(LIF_UP, lif->state)) {
>> + dev_dbg(lif->ionic->dev, "%s: %s state=DOWN\n",
>> + __func__, lif->name);
>> + return 0;
>> + }
>> + dev_dbg(lif->ionic->dev, "%s: %s state=UP\n", __func__, lif-
>>> name);
>> + clear_bit(LIF_UP, lif->state);
>> +
>> + /* carrier off before disabling queues to avoid watchdog
>> timeout */
>> + netif_carrier_off(ndev);
>> + netif_tx_stop_all_queues(ndev);
>> + netif_tx_disable(ndev);
>> + synchronize_rcu();
> why synchronize_rcu ?
Looks like a little leakage from a feature in the internal driver, I'll
remove it.
>> +
>> + return err;
>> +}
>> +
>> +int ionic_stop(struct net_device *netdev)
>> +{
>> + struct lif *lif = netdev_priv(netdev);
>> +
>> + return ionic_lif_stop(lif);
>> +}
>> +
>> +int ionic_reset_queues(struct lif *lif)
>> +{
>> + bool running;
>> + int err = 0;
>> +
>> + /* Put off the next watchdog timeout */
>> + netif_trans_update(lif->netdev);
> this doesn't seem right to me also this won't help you if the next
> while loop takes too long.. also netif_trans_update is marked to be
> only used for legacy drivers.
If the loop takes too long, then I don't mind if the watchdog goes off.
Yes, its primary use is now handled by netdev_start_xmit(), but it is
still a handy gizmo to give a little more cushion until the carrier is
set off in ionic_lif_stop().
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 10/19] ionic: Add management of rx filters
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (8 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 09/19] ionic: Add the basic NDO callbacks for netdev support Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-24 23:52 ` Saeed Mahameed
2019-07-22 21:40 ` [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support Shannon Nelson
` (8 subsequent siblings)
18 siblings, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Set up the infrastructure for managing Rx filters. We can't ask the
hardware for what filters it has, so we keep a local list of filters
that we've pushed into the HW.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/Makefile | 4 +-
.../net/ethernet/pensando/ionic/ionic_lif.c | 6 +
.../net/ethernet/pensando/ionic/ionic_lif.h | 2 +
.../ethernet/pensando/ionic/ionic_rx_filter.c | 143 ++++++++++++++++++
.../ethernet/pensando/ionic/ionic_rx_filter.h | 35 +++++
5 files changed, 188 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_rx_filter.c
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_rx_filter.h
diff --git a/drivers/net/ethernet/pensando/ionic/Makefile b/drivers/net/ethernet/pensando/ionic/Makefile
index 04d519d00be6..7d9cdc5f02a1 100644
--- a/drivers/net/ethernet/pensando/ionic/Makefile
+++ b/drivers/net/ethernet/pensando/ionic/Makefile
@@ -3,5 +3,5 @@
obj-$(CONFIG_IONIC) := ionic.o
-ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_debugfs.o \
- ionic_lif.o
+ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o \
+ ionic_lif.o ionic_rx_filter.o ionic_debugfs.o
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index 005b1d908fa1..72ac0fd56b69 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -667,6 +667,8 @@ static void ionic_lif_deinit(struct lif *lif)
clear_bit(LIF_INITED, lif->state);
+ ionic_rx_filters_deinit(lif);
+
napi_disable(&lif->adminqcq->napi);
ionic_lif_qcq_deinit(lif, lif->notifyqcq);
ionic_lif_qcq_deinit(lif, lif->adminqcq);
@@ -1033,6 +1035,10 @@ static int ionic_lif_init(struct lif *lif)
if (err)
goto err_out_notifyq_deinit;
+ err = ionic_rx_filters_init(lif);
+ if (err)
+ goto err_out_notifyq_deinit;
+
set_bit(LIF_INITED, lif->state);
return 0;
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index ef3f7340a277..9f112aa69033 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -5,6 +5,7 @@
#define _IONIC_LIF_H_
#include <linux/pci.h>
+#include "ionic_rx_filter.h"
#define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */
#define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */
@@ -92,6 +93,7 @@ struct lif {
dma_addr_t info_pa;
u32 info_sz;
+ struct rx_filters rx_filters;
unsigned long *dbid_inuse;
unsigned int dbid_count;
struct dentry *dentry;
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_rx_filter.c b/drivers/net/ethernet/pensando/ionic/ionic_rx_filter.c
new file mode 100644
index 000000000000..e0b67fd90b11
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_rx_filter.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+
+#include "ionic.h"
+#include "ionic_lif.h"
+#include "ionic_rx_filter.h"
+
+void ionic_rx_filter_free(struct lif *lif, struct rx_filter *f)
+{
+ struct device *dev = lif->ionic->dev;
+
+ hlist_del(&f->by_id);
+ hlist_del(&f->by_hash);
+ devm_kfree(dev, f);
+}
+
+int ionic_rx_filter_del(struct lif *lif, struct rx_filter *f)
+{
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.rx_filter_del = {
+ .opcode = CMD_OPCODE_RX_FILTER_DEL,
+ .filter_id = cpu_to_le32(f->filter_id),
+ },
+ };
+
+ return ionic_adminq_post_wait(lif, &ctx);
+}
+
+int ionic_rx_filters_init(struct lif *lif)
+{
+ unsigned int i;
+
+ spin_lock_init(&lif->rx_filters.lock);
+
+ for (i = 0; i < RX_FILTER_HLISTS; i++) {
+ INIT_HLIST_HEAD(&lif->rx_filters.by_hash[i]);
+ INIT_HLIST_HEAD(&lif->rx_filters.by_id[i]);
+ }
+
+ return 0;
+}
+
+void ionic_rx_filters_deinit(struct lif *lif)
+{
+ struct hlist_head *head;
+ struct hlist_node *tmp;
+ struct rx_filter *f;
+ unsigned int i;
+
+ for (i = 0; i < RX_FILTER_HLISTS; i++) {
+ head = &lif->rx_filters.by_id[i];
+ hlist_for_each_entry_safe(f, tmp, head, by_id)
+ ionic_rx_filter_free(lif, f);
+ }
+}
+
+int ionic_rx_filter_save(struct lif *lif, u32 flow_id, u16 rxq_index,
+ u32 hash, struct ionic_admin_ctx *ctx)
+{
+ struct device *dev = lif->ionic->dev;
+ struct rx_filter_add_cmd *ac;
+ struct hlist_head *head;
+ struct rx_filter *f;
+ unsigned int key;
+
+ ac = &ctx->cmd.rx_filter_add;
+
+ switch (le16_to_cpu(ac->match)) {
+ case RX_FILTER_MATCH_VLAN:
+ key = le16_to_cpu(ac->vlan.vlan);
+ break;
+ case RX_FILTER_MATCH_MAC:
+ key = *(u32 *)ac->mac.addr;
+ break;
+ case RX_FILTER_MATCH_MAC_VLAN:
+ key = le16_to_cpu(ac->mac_vlan.vlan);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ f = devm_kzalloc(dev, sizeof(*f), GFP_KERNEL);
+ if (!f)
+ return -ENOMEM;
+
+ f->flow_id = flow_id;
+ f->filter_id = le32_to_cpu(ctx->comp.rx_filter_add.filter_id);
+ f->rxq_index = rxq_index;
+ memcpy(&f->cmd, ac, sizeof(f->cmd));
+
+ INIT_HLIST_NODE(&f->by_hash);
+ INIT_HLIST_NODE(&f->by_id);
+
+ spin_lock_bh(&lif->rx_filters.lock);
+
+ key = hash_32(key, RX_FILTER_HASH_BITS);
+ head = &lif->rx_filters.by_hash[key];
+ hlist_add_head(&f->by_hash, head);
+
+ key = f->filter_id & RX_FILTER_HLISTS_MASK;
+ head = &lif->rx_filters.by_id[key];
+ hlist_add_head(&f->by_id, head);
+
+ spin_unlock_bh(&lif->rx_filters.lock);
+
+ return 0;
+}
+
+struct rx_filter *ionic_rx_filter_by_vlan(struct lif *lif, u16 vid)
+{
+ unsigned int key = hash_32(vid, RX_FILTER_HASH_BITS);
+ struct hlist_head *head = &lif->rx_filters.by_hash[key];
+ struct rx_filter *f;
+
+ hlist_for_each_entry(f, head, by_hash) {
+ if (le16_to_cpu(f->cmd.match) != RX_FILTER_MATCH_VLAN)
+ continue;
+ if (le16_to_cpu(f->cmd.vlan.vlan) == vid)
+ return f;
+ }
+
+ return NULL;
+}
+
+struct rx_filter *ionic_rx_filter_by_addr(struct lif *lif, const u8 *addr)
+{
+ unsigned int key = hash_32(*(u32 *)addr, RX_FILTER_HASH_BITS);
+ struct hlist_head *head = &lif->rx_filters.by_hash[key];
+ struct rx_filter *f;
+
+ hlist_for_each_entry(f, head, by_hash) {
+ if (le16_to_cpu(f->cmd.match) != RX_FILTER_MATCH_MAC)
+ continue;
+ if (memcmp(addr, f->cmd.mac.addr, ETH_ALEN) == 0)
+ return f;
+ }
+
+ return NULL;
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_rx_filter.h b/drivers/net/ethernet/pensando/ionic/ionic_rx_filter.h
new file mode 100644
index 000000000000..67ae279a4cb6
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_rx_filter.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#ifndef _IONIC_RX_FILTER_H_
+#define _IONIC_RX_FILTER_H_
+
+#define RXQ_INDEX_ANY (0xFFFF)
+struct rx_filter {
+ u32 flow_id;
+ u32 filter_id;
+ u16 rxq_index;
+ struct rx_filter_add_cmd cmd;
+ struct hlist_node by_hash;
+ struct hlist_node by_id;
+};
+
+#define RX_FILTER_HASH_BITS 10
+#define RX_FILTER_HLISTS BIT(RX_FILTER_HASH_BITS)
+#define RX_FILTER_HLISTS_MASK (RX_FILTER_HLISTS - 1)
+struct rx_filters {
+ spinlock_t lock; /* filter list lock */
+ struct hlist_head by_hash[RX_FILTER_HLISTS]; /* by skb hash */
+ struct hlist_head by_id[RX_FILTER_HLISTS]; /* by filter_id */
+};
+
+void ionic_rx_filter_free(struct lif *lif, struct rx_filter *f);
+int ionic_rx_filter_del(struct lif *lif, struct rx_filter *f);
+int ionic_rx_filters_init(struct lif *lif);
+void ionic_rx_filters_deinit(struct lif *lif);
+int ionic_rx_filter_save(struct lif *lif, u32 flow_id, u16 rxq_index,
+ u32 hash, struct ionic_admin_ctx *ctx);
+struct rx_filter *ionic_rx_filter_by_vlan(struct lif *lif, u16 vid);
+struct rx_filter *ionic_rx_filter_by_addr(struct lif *lif, const u8 *addr);
+
+#endif /* _IONIC_RX_FILTER_H_ */
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 10/19] ionic: Add management of rx filters
2019-07-22 21:40 ` [PATCH v4 net-next 10/19] ionic: Add management of rx filters Shannon Nelson
@ 2019-07-24 23:52 ` Saeed Mahameed
0 siblings, 0 replies; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-24 23:52 UTC (permalink / raw)
To: snelson, netdev, davem
On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> Set up the infrastructure for managing Rx filters. We can't ask the
> hardware for what filters it has, so we keep a local list of filters
> that we've pushed into the HW.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
> ---
> drivers/net/ethernet/pensando/ionic/Makefile | 4 +-
> .../net/ethernet/pensando/ionic/ionic_lif.c | 6 +
> .../net/ethernet/pensando/ionic/ionic_lif.h | 2 +
> .../ethernet/pensando/ionic/ionic_rx_filter.c | 143
> ++++++++++++++++++
> .../ethernet/pensando/ionic/ionic_rx_filter.h | 35 +++++
> 5 files changed, 188 insertions(+), 2 deletions(-)
> create mode 100644
> drivers/net/ethernet/pensando/ionic/ionic_rx_filter.c
> create mode 100644
> drivers/net/ethernet/pensando/ionic/ionic_rx_filter.h
>
>
[...]
> +#define RXQ_INDEX_ANY (0xFFFF)
> +struct rx_filter {
> + u32 flow_id;
> + u32 filter_id;
> + u16 rxq_index;
> + struct rx_filter_add_cmd cmd;
> + struct hlist_node by_hash;
> + struct hlist_node by_id;
> +};
> +
> +#define RX_FILTER_HASH_BITS 10
> +#define RX_FILTER_HLISTS BIT(RX_FILTER_HASH_BITS)
> +#define RX_FILTER_HLISTS_MASK (RX_FILTER_HLISTS - 1)
> +struct rx_filters {
> + spinlock_t lock; /* filter list lock
> */
> + struct hlist_head by_hash[RX_FILTER_HLISTS]; /* by skb
> hash */
> + struct hlist_head by_id[RX_FILTER_HLISTS]; /* by
> filter_id */
> +};
> +
>
Following Dave's comment on this, you use too generic struct and macro
/define names, i strongly recommend to add a unique prefix to this
driver.
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (9 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 10/19] ionic: Add management of rx filters Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-23 21:33 ` David Miller
2019-07-23 23:20 ` Saeed Mahameed
2019-07-22 21:40 ` [PATCH v4 net-next 12/19] ionic: Add async link status check and basic stats Shannon Nelson
` (7 subsequent siblings)
18 siblings, 2 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Add the Rx filtering and rx_mode NDO callbacks. Also add
the deferred work thread handling needed to manage the filter
requests otuside of the netif_addr_lock spinlock.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
.../net/ethernet/pensando/ionic/ionic_lif.c | 389 +++++++++++++++++-
.../net/ethernet/pensando/ionic/ionic_lif.h | 29 ++
2 files changed, 412 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index 72ac0fd56b69..efcda1337f91 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -12,9 +12,55 @@
#include "ionic_lif.h"
#include "ionic_debugfs.h"
+static void ionic_lif_rx_mode(struct lif *lif, unsigned int rx_mode);
+static int ionic_lif_addr_add(struct lif *lif, const u8 *addr);
+static int ionic_lif_addr_del(struct lif *lif, const u8 *addr);
+
static int ionic_set_nic_features(struct lif *lif, netdev_features_t features);
static int ionic_notifyq_clean(struct lif *lif, int budget);
+static void ionic_lif_deferred_work(struct work_struct *work)
+{
+ struct lif *lif = container_of(work, struct lif, deferred.work);
+ struct ionic_deferred *def = &lif->deferred;
+ struct ionic_deferred_work *w = NULL;
+
+ spin_lock_bh(&def->lock);
+ if (!list_empty(&def->list)) {
+ w = list_first_entry(&def->list,
+ struct ionic_deferred_work, list);
+ list_del(&w->list);
+ }
+ spin_unlock_bh(&def->lock);
+
+ if (w) {
+ switch (w->type) {
+ case DW_TYPE_RX_MODE:
+ ionic_lif_rx_mode(lif, w->rx_mode);
+ break;
+ case DW_TYPE_RX_ADDR_ADD:
+ ionic_lif_addr_add(lif, w->addr);
+ break;
+ case DW_TYPE_RX_ADDR_DEL:
+ ionic_lif_addr_del(lif, w->addr);
+ break;
+ default:
+ break;
+ }
+ kfree(w);
+ schedule_work(&def->work);
+ }
+}
+
+static void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
+ struct ionic_deferred_work *work)
+{
+ spin_lock_bh(&def->lock);
+ list_add_tail(&work->list, &def->list);
+ spin_unlock_bh(&def->lock);
+ schedule_work(&def->work);
+}
+
int ionic_open(struct net_device *netdev)
{
struct lif *lif = netdev_priv(netdev);
@@ -180,6 +226,235 @@ static int ionic_notifyq_clean(struct lif *lif, int budget)
return work_done;
}
+static int ionic_lif_addr_add(struct lif *lif, const u8 *addr)
+{
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.rx_filter_add = {
+ .opcode = CMD_OPCODE_RX_FILTER_ADD,
+ .lif_index = cpu_to_le16(lif->index),
+ .match = cpu_to_le16(RX_FILTER_MATCH_MAC),
+ },
+ };
+ struct rx_filter *f;
+ int err;
+
+ /* don't bother if we already have it */
+ spin_lock_bh(&lif->rx_filters.lock);
+ f = ionic_rx_filter_by_addr(lif, addr);
+ spin_unlock_bh(&lif->rx_filters.lock);
+ if (f)
+ return 0;
+
+ netdev_dbg(lif->netdev, "rx_filter add ADDR %pM (id %d)\n", addr,
+ ctx.comp.rx_filter_add.filter_id);
+
+ memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN);
+ err = ionic_adminq_post_wait(lif, &ctx);
+ if (err)
+ return err;
+
+ return ionic_rx_filter_save(lif, 0, RXQ_INDEX_ANY, 0, &ctx);
+}
+
+static int ionic_lif_addr_del(struct lif *lif, const u8 *addr)
+{
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.rx_filter_del = {
+ .opcode = CMD_OPCODE_RX_FILTER_DEL,
+ .lif_index = cpu_to_le16(lif->index),
+ },
+ };
+ struct rx_filter *f;
+ int err;
+
+ spin_lock_bh(&lif->rx_filters.lock);
+ f = ionic_rx_filter_by_addr(lif, addr);
+ if (!f) {
+ spin_unlock_bh(&lif->rx_filters.lock);
+ return -ENOENT;
+ }
+
+ ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
+ ionic_rx_filter_free(lif, f);
+ spin_unlock_bh(&lif->rx_filters.lock);
+
+ err = ionic_adminq_post_wait(lif, &ctx);
+ if (err)
+ return err;
+
+ netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n", addr,
+ ctx.cmd.rx_filter_del.filter_id);
+
+ return 0;
+}
+
+static int ionic_lif_addr(struct lif *lif, const u8 *addr, bool add)
+{
+ struct ionic *ionic = lif->ionic;
+ struct ionic_deferred_work *work;
+ unsigned int nmfilters;
+ unsigned int nufilters;
+
+ if (add) {
+ /* Do we have space for this filter? We test the counters
+ * here before checking the need for deferral so that we
+ * can return an overflow error to the stack.
+ */
+ nmfilters = le32_to_cpu(ionic->ident.lif.eth.max_mcast_filters);
+ nufilters = le32_to_cpu(ionic->ident.lif.eth.max_ucast_filters);
+
+ if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters))
+ lif->nmcast++;
+ else if (!is_multicast_ether_addr(addr) &&
+ lif->nucast < nufilters)
+ lif->nucast++;
+ else
+ return -ENOSPC;
+ } else {
+ if (is_multicast_ether_addr(addr) && lif->nmcast)
+ lif->nmcast--;
+ else if (!is_multicast_ether_addr(addr) && lif->nucast)
+ lif->nucast--;
+ }
+
+ if (in_interrupt()) {
+ work = kzalloc(sizeof(*work), GFP_ATOMIC);
+ if (!work) {
+ netdev_err(lif->netdev, "%s OOM\n", __func__);
+ return -ENOMEM;
+ }
+ work->type = add ? DW_TYPE_RX_ADDR_ADD : DW_TYPE_RX_ADDR_DEL;
+ memcpy(work->addr, addr, ETH_ALEN);
+ netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n",
+ add ? "add" : "del", addr);
+ ionic_lif_deferred_enqueue(&lif->deferred, work);
+ } else {
+ netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
+ add ? "add" : "del", addr);
+ if (add)
+ return ionic_lif_addr_add(lif, addr);
+ else
+ return ionic_lif_addr_del(lif, addr);
+ }
+
+ return 0;
+}
+
+static int ionic_addr_add(struct net_device *netdev, const u8 *addr)
+{
+ return ionic_lif_addr(netdev_priv(netdev), addr, true);
+}
+
+static int ionic_addr_del(struct net_device *netdev, const u8 *addr)
+{
+ return ionic_lif_addr(netdev_priv(netdev), addr, false);
+}
+
+static void ionic_lif_rx_mode(struct lif *lif, unsigned int rx_mode)
+{
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.rx_mode_set = {
+ .opcode = CMD_OPCODE_RX_MODE_SET,
+ .lif_index = cpu_to_le16(lif->index),
+ .rx_mode = cpu_to_le16(rx_mode),
+ },
+ };
+ char buf[128];
+ int err;
+ int i;
+#define REMAIN(__x) (sizeof(buf) - (__x))
+
+ i = snprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",
+ lif->rx_mode, rx_mode);
+ if (rx_mode & RX_MODE_F_UNICAST)
+ i += snprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST");
+ if (rx_mode & RX_MODE_F_MULTICAST)
+ i += snprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST");
+ if (rx_mode & RX_MODE_F_BROADCAST)
+ i += snprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST");
+ if (rx_mode & RX_MODE_F_PROMISC)
+ i += snprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC");
+ if (rx_mode & RX_MODE_F_ALLMULTI)
+ i += snprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI");
+ netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf);
+
+ err = ionic_adminq_post_wait(lif, &ctx);
+ if (err)
+ netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n",
+ rx_mode, err);
+ else
+ lif->rx_mode = rx_mode;
+}
+
+static void _ionic_lif_rx_mode(struct lif *lif, unsigned int rx_mode)
+{
+ struct ionic_deferred_work *work;
+
+ if (in_interrupt()) {
+ work = kzalloc(sizeof(*work), GFP_ATOMIC);
+ if (!work) {
+ netdev_err(lif->netdev, "%s OOM\n", __func__);
+ return;
+ }
+ work->type = DW_TYPE_RX_MODE;
+ work->rx_mode = rx_mode;
+ netdev_dbg(lif->netdev, "deferred: rx_mode\n");
+ ionic_lif_deferred_enqueue(&lif->deferred, work);
+ } else {
+ ionic_lif_rx_mode(lif, rx_mode);
+ }
+}
+
+static void ionic_set_rx_mode(struct net_device *netdev)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct identity *ident = &lif->ionic->ident;
+ unsigned int nfilters;
+ unsigned int rx_mode;
+
+ rx_mode = RX_MODE_F_UNICAST;
+ rx_mode |= (netdev->flags & IFF_MULTICAST) ? RX_MODE_F_MULTICAST : 0;
+ rx_mode |= (netdev->flags & IFF_BROADCAST) ? RX_MODE_F_BROADCAST : 0;
+ rx_mode |= (netdev->flags & IFF_PROMISC) ? RX_MODE_F_PROMISC : 0;
+ rx_mode |= (netdev->flags & IFF_ALLMULTI) ? RX_MODE_F_ALLMULTI : 0;
+
+ /* sync unicast addresses
+ * next check to see if we're in an overflow state
+ * if so, we track that we overflowed and enable NIC PROMISC
+ * else if the overflow is set and not needed
+ * we remove our overflow flag and check the netdev flags
+ * to see if we can disable NIC PROMISC
+ */
+ __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
+ nfilters = le32_to_cpu(ident->lif.eth.max_ucast_filters);
+ if (netdev_uc_count(netdev) + 1 > nfilters) {
+ rx_mode |= RX_MODE_F_PROMISC;
+ lif->uc_overflow = true;
+ } else if (lif->uc_overflow) {
+ lif->uc_overflow = false;
+ if (!(netdev->flags & IFF_PROMISC))
+ rx_mode &= ~RX_MODE_F_PROMISC;
+ }
+
+ /* same for multicast */
+ __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
+ nfilters = le32_to_cpu(ident->lif.eth.max_mcast_filters);
+ if (netdev_mc_count(netdev) > nfilters) {
+ rx_mode |= RX_MODE_F_ALLMULTI;
+ lif->mc_overflow = true;
+ } else if (lif->mc_overflow) {
+ lif->mc_overflow = false;
+ if (!(netdev->flags & IFF_ALLMULTI))
+ rx_mode &= ~RX_MODE_F_ALLMULTI;
+ }
+
+ if (lif->rx_mode != rx_mode)
+ _ionic_lif_rx_mode(lif, rx_mode);
+}
+
static int ionic_set_features(struct net_device *netdev,
netdev_features_t features)
{
@@ -196,8 +471,26 @@ static int ionic_set_features(struct net_device *netdev,
static int ionic_set_mac_address(struct net_device *netdev, void *sa)
{
- netdev_info(netdev, "%s: stubbed\n", __func__);
- return 0;
+ struct sockaddr *addr = sa;
+ u8 *mac;
+
+ mac = (u8 *)addr->sa_data;
+ if (ether_addr_equal(netdev->dev_addr, mac))
+ return 0;
+
+ if (!is_valid_ether_addr(mac))
+ return -EADDRNOTAVAIL;
+
+ if (!is_zero_ether_addr(netdev->dev_addr)) {
+ netdev_info(netdev, "deleting mac addr %pM\n",
+ netdev->dev_addr);
+ ionic_addr_del(netdev, netdev->dev_addr);
+ }
+
+ memcpy(netdev->dev_addr, mac, netdev->addr_len);
+ netdev_info(netdev, "updating mac addr %pM\n", mac);
+
+ return ionic_addr_add(netdev, mac);
}
static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
@@ -232,20 +525,63 @@ static void ionic_tx_timeout(struct net_device *netdev)
static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
u16 vid)
{
- netdev_info(netdev, "%s: stubbed\n", __func__);
- return 0;
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.rx_filter_add = {
+ .opcode = CMD_OPCODE_RX_FILTER_ADD,
+ .lif_index = cpu_to_le16(lif->index),
+ .match = cpu_to_le16(RX_FILTER_MATCH_VLAN),
+ .vlan.vlan = cpu_to_le16(vid),
+ },
+ };
+ int err;
+
+ err = ionic_adminq_post_wait(lif, &ctx);
+ if (err)
+ return err;
+
+ netdev_dbg(netdev, "rx_filter add VLAN %d (id %d)\n", vid,
+ ctx.comp.rx_filter_add.filter_id);
+
+ return ionic_rx_filter_save(lif, 0, RXQ_INDEX_ANY, 0, &ctx);
}
static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
u16 vid)
{
- netdev_info(netdev, "%s: stubbed\n", __func__);
- return 0;
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.rx_filter_del = {
+ .opcode = CMD_OPCODE_RX_FILTER_DEL,
+ .lif_index = cpu_to_le16(lif->index),
+ },
+ };
+ struct rx_filter *f;
+
+ spin_lock_bh(&lif->rx_filters.lock);
+
+ f = ionic_rx_filter_by_vlan(lif, vid);
+ if (!f) {
+ spin_unlock_bh(&lif->rx_filters.lock);
+ return -ENOENT;
+ }
+
+ netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", vid,
+ le32_to_cpu(ctx.cmd.rx_filter_del.filter_id));
+
+ ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
+ ionic_rx_filter_free(lif, f);
+ spin_unlock_bh(&lif->rx_filters.lock);
+
+ return ionic_adminq_post_wait(lif, &ctx);
}
static const struct net_device_ops ionic_netdev_ops = {
.ndo_open = ionic_open,
.ndo_stop = ionic_stop,
+ .ndo_set_rx_mode = ionic_set_rx_mode,
.ndo_set_features = ionic_set_features,
.ndo_set_mac_address = ionic_set_mac_address,
.ndo_validate_addr = eth_validate_addr,
@@ -546,6 +882,10 @@ static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
spin_lock_init(&lif->adminq_lock);
+ spin_lock_init(&lif->deferred.lock);
+ INIT_LIST_HEAD(&lif->deferred.list);
+ INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work);
+
/* allocate lif info */
lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
lif->info = dma_alloc_coherent(dev, lif->info_sz,
@@ -607,6 +947,8 @@ static void ionic_lif_free(struct lif *lif)
ionic_qcqs_free(lif);
ionic_lif_reset(lif);
+ cancel_work_sync(&lif->deferred.work);
+
/* free lif info */
dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
lif->info = NULL;
@@ -975,6 +1317,37 @@ static int ionic_init_nic_features(struct lif *lif)
return 0;
}
+static int ionic_station_set(struct lif *lif)
+{
+ struct net_device *netdev = lif->netdev;
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.lif_getattr = {
+ .opcode = CMD_OPCODE_LIF_GETATTR,
+ .index = cpu_to_le16(lif->index),
+ .attr = IONIC_LIF_ATTR_MAC,
+ },
+ };
+ int err;
+
+ err = ionic_adminq_post_wait(lif, &ctx);
+ if (err)
+ return err;
+
+ if (!is_zero_ether_addr(netdev->dev_addr)) {
+ netdev_dbg(lif->netdev, "deleting station MAC addr %pM\n",
+ netdev->dev_addr);
+ ionic_lif_addr(lif, netdev->dev_addr, false);
+ }
+ memcpy(netdev->dev_addr, ctx.comp.lif_getattr.mac,
+ netdev->addr_len);
+ netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",
+ netdev->dev_addr);
+ ionic_lif_addr(lif, netdev->dev_addr, true);
+
+ return 0;
+}
+
static int ionic_lif_init(struct lif *lif)
{
struct ionic_dev *idev = &lif->ionic->idev;
@@ -1039,6 +1412,10 @@ static int ionic_lif_init(struct lif *lif)
if (err)
goto err_out_notifyq_deinit;
+ err = ionic_station_set(lif);
+ if (err)
+ goto err_out_notifyq_deinit;
+
set_bit(LIF_INITED, lif->state);
return 0;
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index 9f112aa69033..20b4fa573f77 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -60,6 +60,29 @@ struct qcq {
#define napi_to_qcq(napi) container_of(napi, struct qcq, napi)
#define napi_to_cq(napi) (&napi_to_qcq(napi)->cq)
+enum ionic_deferred_work_type {
+ DW_TYPE_RX_MODE,
+ DW_TYPE_RX_ADDR_ADD,
+ DW_TYPE_RX_ADDR_DEL,
+ DW_TYPE_LINK_STATUS,
+ DW_TYPE_LIF_RESET,
+};
+
+struct ionic_deferred_work {
+ struct list_head list;
+ enum ionic_deferred_work_type type;
+ union {
+ unsigned int rx_mode;
+ u8 addr[ETH_ALEN];
+ };
+};
+
+struct ionic_deferred {
+ spinlock_t lock; /* lock for deferred work list */
+ struct list_head list;
+ struct work_struct work;
+};
+
enum lif_state_flags {
LIF_INITED,
LIF_UP,
@@ -87,13 +110,19 @@ struct lif {
u64 last_eid;
unsigned int neqs;
unsigned int nxqs;
+ unsigned int rx_mode;
u64 hw_features;
+ bool mc_overflow;
+ unsigned int nmcast;
+ bool uc_overflow;
+ unsigned int nucast;
struct lif_info *info;
dma_addr_t info_pa;
u32 info_sz;
struct rx_filters rx_filters;
+ struct ionic_deferred deferred;
unsigned long *dbid_inuse;
unsigned int dbid_count;
struct dentry *dentry;
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-22 21:40 ` [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support Shannon Nelson
@ 2019-07-23 21:33 ` David Miller
2019-07-23 22:50 ` Shannon Nelson
2019-07-23 22:51 ` Saeed Mahameed
2019-07-23 23:20 ` Saeed Mahameed
1 sibling, 2 replies; 69+ messages in thread
From: David Miller @ 2019-07-23 21:33 UTC (permalink / raw)
To: snelson; +Cc: netdev
From: Shannon Nelson <snelson@pensando.io>
Date: Mon, 22 Jul 2019 14:40:15 -0700
> + if (in_interrupt()) {
> + work = kzalloc(sizeof(*work), GFP_ATOMIC);
> + if (!work) {
> + netdev_err(lif->netdev, "%s OOM\n", __func__);
> + return -ENOMEM;
> + }
> + work->type = add ? DW_TYPE_RX_ADDR_ADD : DW_TYPE_RX_ADDR_DEL;
> + memcpy(work->addr, addr, ETH_ALEN);
> + netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n",
> + add ? "add" : "del", addr);
> + ionic_lif_deferred_enqueue(&lif->deferred, work);
> + } else {
> + netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
> + add ? "add" : "del", addr);
> + if (add)
> + return ionic_lif_addr_add(lif, addr);
> + else
> + return ionic_lif_addr_del(lif, addr);
> + }
I don't know about this.
Generally interface address changes are expected to be synchronous.
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-23 21:33 ` David Miller
@ 2019-07-23 22:50 ` Shannon Nelson
2019-07-23 23:06 ` David Miller
2019-07-23 22:51 ` Saeed Mahameed
1 sibling, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-23 22:50 UTC (permalink / raw)
To: David Miller; +Cc: netdev
On 7/23/19 2:33 PM, David Miller wrote:
> From: Shannon Nelson <snelson@pensando.io>
> Date: Mon, 22 Jul 2019 14:40:15 -0700
>
>> + if (in_interrupt()) {
>> + work = kzalloc(sizeof(*work), GFP_ATOMIC);
>> + if (!work) {
>> + netdev_err(lif->netdev, "%s OOM\n", __func__);
>> + return -ENOMEM;
>> + }
>> + work->type = add ? DW_TYPE_RX_ADDR_ADD : DW_TYPE_RX_ADDR_DEL;
>> + memcpy(work->addr, addr, ETH_ALEN);
>> + netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n",
>> + add ? "add" : "del", addr);
>> + ionic_lif_deferred_enqueue(&lif->deferred, work);
>> + } else {
>> + netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
>> + add ? "add" : "del", addr);
>> + if (add)
>> + return ionic_lif_addr_add(lif, addr);
>> + else
>> + return ionic_lif_addr_del(lif, addr);
>> + }
> I don't know about this.
>
> Generally interface address changes are expected to be synchronous.
Yeah, this bothers me a bit as well, but the address change calls come
in under spin_lock_bh(), and I'm reluctant to make an AdminQ call under
the _bh that could block for a few seconds.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-23 22:50 ` Shannon Nelson
@ 2019-07-23 23:06 ` David Miller
2019-07-23 23:54 ` Saeed Mahameed
2019-07-24 0:19 ` Shannon Nelson
0 siblings, 2 replies; 69+ messages in thread
From: David Miller @ 2019-07-23 23:06 UTC (permalink / raw)
To: snelson; +Cc: netdev
From: Shannon Nelson <snelson@pensando.io>
Date: Tue, 23 Jul 2019 15:50:43 -0700
> On 7/23/19 2:33 PM, David Miller wrote:
>> Generally interface address changes are expected to be synchronous.
> Yeah, this bothers me a bit as well, but the address change calls come
> in under spin_lock_bh(), and I'm reluctant to make an AdminQ call
> under the _bh that could block for a few seconds.
So it's not about memory allocation but rather the fact that the device
might take a while to complete?
Can you start the operation synchronously yet complete it async?
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-23 23:06 ` David Miller
@ 2019-07-23 23:54 ` Saeed Mahameed
2019-07-24 0:19 ` Shannon Nelson
2019-07-24 0:19 ` Shannon Nelson
1 sibling, 1 reply; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-23 23:54 UTC (permalink / raw)
To: snelson, davem; +Cc: netdev
On Tue, 2019-07-23 at 16:06 -0700, David Miller wrote:
> From: Shannon Nelson <snelson@pensando.io>
> Date: Tue, 23 Jul 2019 15:50:43 -0700
>
> > On 7/23/19 2:33 PM, David Miller wrote:
> > > Generally interface address changes are expected to be
> > > synchronous.
> > Yeah, this bothers me a bit as well, but the address change calls
> > come
> > in under spin_lock_bh(), and I'm reluctant to make an AdminQ call
> > under the _bh that could block for a few seconds.
>
> So it's not about memory allocation but rather the fact that the
> device
> might take a while to complete?
>
> Can you start the operation synchronously yet complete it async?
The driver is doing busy polling on command completion, doing only busy
polling on completion status in the deferred work will not be much
different than what they have now..
async completion will only make since if the hardware supports
interrupt based (MSI-x) command completion.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-23 23:54 ` Saeed Mahameed
@ 2019-07-24 0:19 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-24 0:19 UTC (permalink / raw)
To: Saeed Mahameed, davem; +Cc: netdev
On 7/23/19 4:54 PM, Saeed Mahameed wrote:
> On Tue, 2019-07-23 at 16:06 -0700, David Miller wrote:
>> From: Shannon Nelson <snelson@pensando.io>
>> Date: Tue, 23 Jul 2019 15:50:43 -0700
>>
>>> On 7/23/19 2:33 PM, David Miller wrote:
>>>> Generally interface address changes are expected to be
>>>> synchronous.
>>> Yeah, this bothers me a bit as well, but the address change calls
>>> come
>>> in under spin_lock_bh(), and I'm reluctant to make an AdminQ call
>>> under the _bh that could block for a few seconds.
>> So it's not about memory allocation but rather the fact that the
>> device
>> might take a while to complete?
>>
>> Can you start the operation synchronously yet complete it async?
> The driver is doing busy polling on command completion, doing only busy
> polling on completion status in the deferred work will not be much
> different than what they have now..
>
> async completion will only make since if the hardware supports
> interrupt based (MSI-x) command completion.
Actually, there are two different command paths - one for basic
low-level setup, and one for more advanced work:
- dev_cmd does indeed do polling on PCI register space, and we try to
keep this to a minimum
- adminq does a wait_for_completion_timeout() which gets completed in an
MSI-x handler
The rx_mode related work goes through adminq.
Yes, it could be made async, but would the extra logic needed buy us
that much? We already know this model works in other drivers. We
wouldn't get the address into the hardware any quicker, and we still
wouldn't get any errors from the request back to the original call.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-23 23:06 ` David Miller
2019-07-23 23:54 ` Saeed Mahameed
@ 2019-07-24 0:19 ` Shannon Nelson
1 sibling, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-24 0:19 UTC (permalink / raw)
To: David Miller; +Cc: netdev
On 7/23/19 4:06 PM, David Miller wrote:
> From: Shannon Nelson <snelson@pensando.io>
> Date: Tue, 23 Jul 2019 15:50:43 -0700
>
>> On 7/23/19 2:33 PM, David Miller wrote:
>>> Generally interface address changes are expected to be synchronous.
>> Yeah, this bothers me a bit as well, but the address change calls come
>> in under spin_lock_bh(), and I'm reluctant to make an AdminQ call
>> under the _bh that could block for a few seconds.
> So it's not about memory allocation but rather the fact that the device
> might take a while to complete?
Memory allocation may or may not be involved, but yes, mainly we're
doing another spin_lock on a firmware command that waits for an ACK or
ERROR answer, and in extreme cases could possibly timeout on a dead
firmware. I know that i40e and ice do much the same thing, and I
believe mlx5 as well, for the same reasons. I suspect others do as well.
> Can you start the operation synchronously yet complete it async?
This could be possible, but would likely require a bunch more messy
logic to track async AdminQ requests, that otherwise is unnecessary.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-23 21:33 ` David Miller
2019-07-23 22:50 ` Shannon Nelson
@ 2019-07-23 22:51 ` Saeed Mahameed
1 sibling, 0 replies; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-23 22:51 UTC (permalink / raw)
To: snelson, davem; +Cc: netdev
On Tue, 2019-07-23 at 14:33 -0700, David Miller wrote:
> From: Shannon Nelson <snelson@pensando.io>
> Date: Mon, 22 Jul 2019 14:40:15 -0700
>
> > + if (in_interrupt()) {
> > + work = kzalloc(sizeof(*work), GFP_ATOMIC);
> > + if (!work) {
> > + netdev_err(lif->netdev, "%s OOM\n", __func__);
> > + return -ENOMEM;
> > + }
> > + work->type = add ? DW_TYPE_RX_ADDR_ADD :
> > DW_TYPE_RX_ADDR_DEL;
> > + memcpy(work->addr, addr, ETH_ALEN);
> > + netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n",
> > + add ? "add" : "del", addr);
> > + ionic_lif_deferred_enqueue(&lif->deferred, work);
> > + } else {
> > + netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
> > + add ? "add" : "del", addr);
> > + if (add)
> > + return ionic_lif_addr_add(lif, addr);
> > + else
> > + return ionic_lif_addr_del(lif, addr);
> > + }
>
> I don't know about this.
>
> Generally interface address changes are expected to be synchronous.
Well, drivers can't sleep on set_rx_mode ndo, dev_set_rx_mode is
holding netif_addr_lock_bh.
Some drivers need to wait for firmware/device completion to program the
new address and they have to do this asynchronously to avoid atomic
context. I assume this driver is having the same issue due to
"ionic_adminq_post_wait()" ..
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-22 21:40 ` [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support Shannon Nelson
2019-07-23 21:33 ` David Miller
@ 2019-07-23 23:20 ` Saeed Mahameed
2019-07-24 0:07 ` Shannon Nelson
1 sibling, 1 reply; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-23 23:20 UTC (permalink / raw)
To: snelson, netdev, davem
On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> Add the Rx filtering and rx_mode NDO callbacks. Also add
> the deferred work thread handling needed to manage the filter
> requests otuside of the netif_addr_lock spinlock.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
> ---
> .../net/ethernet/pensando/ionic/ionic_lif.c | 389
> +++++++++++++++++-
> .../net/ethernet/pensando/ionic/ionic_lif.h | 29 ++
> 2 files changed, 412 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> index 72ac0fd56b69..efcda1337f91 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> @@ -12,9 +12,55 @@
> #include "ionic_lif.h"
> #include "ionic_debugfs.h"
>
> +static void ionic_lif_rx_mode(struct lif *lif, unsigned int
> rx_mode);
> +static int ionic_lif_addr_add(struct lif *lif, const u8 *addr);
> +static int ionic_lif_addr_del(struct lif *lif, const u8 *addr);
> +
> static int ionic_set_nic_features(struct lif *lif, netdev_features_t
> features);
> static int ionic_notifyq_clean(struct lif *lif, int budget);
>
> +static void ionic_lif_deferred_work(struct work_struct *work)
> +{
> + struct lif *lif = container_of(work, struct lif,
> deferred.work);
> + struct ionic_deferred *def = &lif->deferred;
> + struct ionic_deferred_work *w = NULL;
> +
> + spin_lock_bh(&def->lock);
> + if (!list_empty(&def->list)) {
> + w = list_first_entry(&def->list,
> + struct ionic_deferred_work, list);
> + list_del(&w->list);
> + }
> + spin_unlock_bh(&def->lock);
> +
> + if (w) {
> + switch (w->type) {
> + case DW_TYPE_RX_MODE:
> + ionic_lif_rx_mode(lif, w->rx_mode);
> + break;
> + case DW_TYPE_RX_ADDR_ADD:
> + ionic_lif_addr_add(lif, w->addr);
> + break;
> + case DW_TYPE_RX_ADDR_DEL:
> + ionic_lif_addr_del(lif, w->addr);
> + break;
> + default:
> + break;
> + }
> + kfree(w);
> + schedule_work(&def->work);
> + }
> +}
> +
> +static void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
> + struct ionic_deferred_work
> *work)
> +{
> + spin_lock_bh(&def->lock);
> + list_add_tail(&work->list, &def->list);
> + spin_unlock_bh(&def->lock);
> + schedule_work(&def->work);
> +}
> +
> int ionic_open(struct net_device *netdev)
> {
> struct lif *lif = netdev_priv(netdev);
> @@ -180,6 +226,235 @@ static int ionic_notifyq_clean(struct lif *lif,
> int budget)
> return work_done;
> }
>
> +static int ionic_lif_addr_add(struct lif *lif, const u8 *addr)
> +{
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.rx_filter_add = {
> + .opcode = CMD_OPCODE_RX_FILTER_ADD,
> + .lif_index = cpu_to_le16(lif->index),
> + .match = cpu_to_le16(RX_FILTER_MATCH_MAC),
> + },
> + };
> + struct rx_filter *f;
> + int err;
> +
> + /* don't bother if we already have it */
> + spin_lock_bh(&lif->rx_filters.lock);
> + f = ionic_rx_filter_by_addr(lif, addr);
> + spin_unlock_bh(&lif->rx_filters.lock);
> + if (f)
> + return 0;
> +
> + netdev_dbg(lif->netdev, "rx_filter add ADDR %pM (id %d)\n",
> addr,
> + ctx.comp.rx_filter_add.filter_id);
> +
> + memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN);
> + err = ionic_adminq_post_wait(lif, &ctx);
> + if (err)
> + return err;
> +
> + return ionic_rx_filter_save(lif, 0, RXQ_INDEX_ANY, 0, &ctx);
> +}
> +
> +static int ionic_lif_addr_del(struct lif *lif, const u8 *addr)
> +{
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.rx_filter_del = {
> + .opcode = CMD_OPCODE_RX_FILTER_DEL,
> + .lif_index = cpu_to_le16(lif->index),
> + },
> + };
> + struct rx_filter *f;
> + int err;
> +
> + spin_lock_bh(&lif->rx_filters.lock);
> + f = ionic_rx_filter_by_addr(lif, addr);
> + if (!f) {
> + spin_unlock_bh(&lif->rx_filters.lock);
> + return -ENOENT;
> + }
> +
> + ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
> + ionic_rx_filter_free(lif, f);
> + spin_unlock_bh(&lif->rx_filters.lock);
> +
> + err = ionic_adminq_post_wait(lif, &ctx);
> + if (err)
> + return err;
> +
> + netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n",
> addr,
> + ctx.cmd.rx_filter_del.filter_id);
> +
> + return 0;
> +}
> +
> +static int ionic_lif_addr(struct lif *lif, const u8 *addr, bool add)
> +{
> + struct ionic *ionic = lif->ionic;
> + struct ionic_deferred_work *work;
> + unsigned int nmfilters;
> + unsigned int nufilters;
> +
> + if (add) {
> + /* Do we have space for this filter? We test the
> counters
> + * here before checking the need for deferral so that
> we
> + * can return an overflow error to the stack.
> + */
> + nmfilters = le32_to_cpu(ionic-
> >ident.lif.eth.max_mcast_filters);
> + nufilters = le32_to_cpu(ionic-
> >ident.lif.eth.max_ucast_filters);
> +
> + if ((is_multicast_ether_addr(addr) && lif->nmcast <
> nmfilters))
> + lif->nmcast++;
> + else if (!is_multicast_ether_addr(addr) &&
> + lif->nucast < nufilters)
> + lif->nucast++;
> + else
> + return -ENOSPC;
> + } else {
> + if (is_multicast_ether_addr(addr) && lif->nmcast)
> + lif->nmcast--;
> + else if (!is_multicast_ether_addr(addr) && lif->nucast)
> + lif->nucast--;
> + }
> +
> + if (in_interrupt()) {
> + work = kzalloc(sizeof(*work), GFP_ATOMIC);
> + if (!work) {
> + netdev_err(lif->netdev, "%s OOM\n", __func__);
> + return -ENOMEM;
> + }
> + work->type = add ? DW_TYPE_RX_ADDR_ADD :
> DW_TYPE_RX_ADDR_DEL;
> + memcpy(work->addr, addr, ETH_ALEN);
> + netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n",
> + add ? "add" : "del", addr);
> + ionic_lif_deferred_enqueue(&lif->deferred, work);
> + } else {
> + netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
> + add ? "add" : "del", addr);
> + if (add)
> + return ionic_lif_addr_add(lif, addr);
> + else
> + return ionic_lif_addr_del(lif, addr);
> + }
> +
> + return 0;
> +}
> +
> +static int ionic_addr_add(struct net_device *netdev, const u8 *addr)
> +{
> + return ionic_lif_addr(netdev_priv(netdev), addr, true);
> +}
> +
> +static int ionic_addr_del(struct net_device *netdev, const u8 *addr)
> +{
> + return ionic_lif_addr(netdev_priv(netdev), addr, false);
> +}
> +
> +static void ionic_lif_rx_mode(struct lif *lif, unsigned int rx_mode)
> +{
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.rx_mode_set = {
> + .opcode = CMD_OPCODE_RX_MODE_SET,
> + .lif_index = cpu_to_le16(lif->index),
> + .rx_mode = cpu_to_le16(rx_mode),
> + },
> + };
> + char buf[128];
> + int err;
> + int i;
> +#define REMAIN(__x) (sizeof(buf) - (__x))
> +
> + i = snprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",
> + lif->rx_mode, rx_mode);
> + if (rx_mode & RX_MODE_F_UNICAST)
> + i += snprintf(&buf[i], REMAIN(i), "
> RX_MODE_F_UNICAST");
> + if (rx_mode & RX_MODE_F_MULTICAST)
> + i += snprintf(&buf[i], REMAIN(i), "
> RX_MODE_F_MULTICAST");
> + if (rx_mode & RX_MODE_F_BROADCAST)
> + i += snprintf(&buf[i], REMAIN(i), "
> RX_MODE_F_BROADCAST");
> + if (rx_mode & RX_MODE_F_PROMISC)
> + i += snprintf(&buf[i], REMAIN(i), "
> RX_MODE_F_PROMISC");
> + if (rx_mode & RX_MODE_F_ALLMULTI)
> + i += snprintf(&buf[i], REMAIN(i), "
> RX_MODE_F_ALLMULTI");
> + netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf);
> +
> + err = ionic_adminq_post_wait(lif, &ctx);
> + if (err)
> + netdev_warn(lif->netdev, "set rx_mode 0x%04x failed:
> %d\n",
> + rx_mode, err);
> + else
> + lif->rx_mode = rx_mode;
> +}
> +
> +static void _ionic_lif_rx_mode(struct lif *lif, unsigned int
> rx_mode)
> +{
> + struct ionic_deferred_work *work;
> +
> + if (in_interrupt()) {
> + work = kzalloc(sizeof(*work), GFP_ATOMIC);
> + if (!work) {
> + netdev_err(lif->netdev, "%s OOM\n", __func__);
> + return;
> + }
> + work->type = DW_TYPE_RX_MODE;
> + work->rx_mode = rx_mode;
> + netdev_dbg(lif->netdev, "deferred: rx_mode\n");
> + ionic_lif_deferred_enqueue(&lif->deferred, work);
> + } else {
> + ionic_lif_rx_mode(lif, rx_mode);
> + }
> +}
> +
> +static void ionic_set_rx_mode(struct net_device *netdev)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct identity *ident = &lif->ionic->ident;
> + unsigned int nfilters;
> + unsigned int rx_mode;
> +
> + rx_mode = RX_MODE_F_UNICAST;
> + rx_mode |= (netdev->flags & IFF_MULTICAST) ?
> RX_MODE_F_MULTICAST : 0;
> + rx_mode |= (netdev->flags & IFF_BROADCAST) ?
> RX_MODE_F_BROADCAST : 0;
> + rx_mode |= (netdev->flags & IFF_PROMISC) ? RX_MODE_F_PROMISC :
> 0;
> + rx_mode |= (netdev->flags & IFF_ALLMULTI) ? RX_MODE_F_ALLMULTI
> : 0;
> +
> + /* sync unicast addresses
> + * next check to see if we're in an overflow state
> + * if so, we track that we overflowed and enable NIC PROMISC
> + * else if the overflow is set and not needed
> + * we remove our overflow flag and check the netdev flags
> + * to see if we can disable NIC PROMISC
> + */
> + __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
> + nfilters = le32_to_cpu(ident->lif.eth.max_ucast_filters);
> + if (netdev_uc_count(netdev) + 1 > nfilters) {
> + rx_mode |= RX_MODE_F_PROMISC;
> + lif->uc_overflow = true;
> + } else if (lif->uc_overflow) {
> + lif->uc_overflow = false;
> + if (!(netdev->flags & IFF_PROMISC))
> + rx_mode &= ~RX_MODE_F_PROMISC;
> + }
> +
> + /* same for multicast */
> + __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
> + nfilters = le32_to_cpu(ident->lif.eth.max_mcast_filters);
> + if (netdev_mc_count(netdev) > nfilters) {
> + rx_mode |= RX_MODE_F_ALLMULTI;
> + lif->mc_overflow = true;
> + } else if (lif->mc_overflow) {
> + lif->mc_overflow = false;
> + if (!(netdev->flags & IFF_ALLMULTI))
> + rx_mode &= ~RX_MODE_F_ALLMULTI;
> + }
> +
> + if (lif->rx_mode != rx_mode)
> + _ionic_lif_rx_mode(lif, rx_mode);
> +}
> +
> static int ionic_set_features(struct net_device *netdev,
> netdev_features_t features)
> {
> @@ -196,8 +471,26 @@ static int ionic_set_features(struct net_device
> *netdev,
>
> static int ionic_set_mac_address(struct net_device *netdev, void
> *sa)
> {
> - netdev_info(netdev, "%s: stubbed\n", __func__);
> - return 0;
> + struct sockaddr *addr = sa;
> + u8 *mac;
> +
> + mac = (u8 *)addr->sa_data;
> + if (ether_addr_equal(netdev->dev_addr, mac))
> + return 0;
> +
> + if (!is_valid_ether_addr(mac))
> + return -EADDRNOTAVAIL;
> +
> + if (!is_zero_ether_addr(netdev->dev_addr)) {
> + netdev_info(netdev, "deleting mac addr %pM\n",
> + netdev->dev_addr);
> + ionic_addr_del(netdev, netdev->dev_addr);
> + }
> +
> + memcpy(netdev->dev_addr, mac, netdev->addr_len);
> + netdev_info(netdev, "updating mac addr %pM\n", mac);
> +
> + return ionic_addr_add(netdev, mac);
> }
>
> static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
> @@ -232,20 +525,63 @@ static void ionic_tx_timeout(struct net_device
> *netdev)
> static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16
> proto,
> u16 vid)
> {
> - netdev_info(netdev, "%s: stubbed\n", __func__);
> - return 0;
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.rx_filter_add = {
> + .opcode = CMD_OPCODE_RX_FILTER_ADD,
> + .lif_index = cpu_to_le16(lif->index),
> + .match = cpu_to_le16(RX_FILTER_MATCH_VLAN),
> + .vlan.vlan = cpu_to_le16(vid),
> + },
> + };
> + int err;
> +
> + err = ionic_adminq_post_wait(lif, &ctx);
> + if (err)
> + return err;
> +
> + netdev_dbg(netdev, "rx_filter add VLAN %d (id %d)\n", vid,
> + ctx.comp.rx_filter_add.filter_id);
> +
> + return ionic_rx_filter_save(lif, 0, RXQ_INDEX_ANY, 0, &ctx);
> }
>
> static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16
> proto,
> u16 vid)
> {
> - netdev_info(netdev, "%s: stubbed\n", __func__);
> - return 0;
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.rx_filter_del = {
> + .opcode = CMD_OPCODE_RX_FILTER_DEL,
> + .lif_index = cpu_to_le16(lif->index),
> + },
> + };
> + struct rx_filter *f;
> +
> + spin_lock_bh(&lif->rx_filters.lock);
> +
> + f = ionic_rx_filter_by_vlan(lif, vid);
> + if (!f) {
> + spin_unlock_bh(&lif->rx_filters.lock);
> + return -ENOENT;
> + }
> +
> + netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", vid,
> + le32_to_cpu(ctx.cmd.rx_filter_del.filter_id));
> +
> + ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
> + ionic_rx_filter_free(lif, f);
> + spin_unlock_bh(&lif->rx_filters.lock);
> +
> + return ionic_adminq_post_wait(lif, &ctx);
> }
>
> static const struct net_device_ops ionic_netdev_ops = {
> .ndo_open = ionic_open,
> .ndo_stop = ionic_stop,
> + .ndo_set_rx_mode = ionic_set_rx_mode,
> .ndo_set_features = ionic_set_features,
> .ndo_set_mac_address = ionic_set_mac_address,
> .ndo_validate_addr = eth_validate_addr,
> @@ -546,6 +882,10 @@ static struct lif *ionic_lif_alloc(struct ionic
> *ionic, unsigned int index)
>
> spin_lock_init(&lif->adminq_lock);
>
> + spin_lock_init(&lif->deferred.lock);
> + INIT_LIST_HEAD(&lif->deferred.list);
> + INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work);
> +
> /* allocate lif info */
> lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE);
> lif->info = dma_alloc_coherent(dev, lif->info_sz,
> @@ -607,6 +947,8 @@ static void ionic_lif_free(struct lif *lif)
> ionic_qcqs_free(lif);
> ionic_lif_reset(lif);
>
I don't think you want deferred.work running while reset is executing..
cancel_work_sync should happen as early as you close the netdevice.
I assume ionic_lif_reset will flush all configurations and you don't
need to cleanup anything manually? or any data structure stored in
driver ?
> + cancel_work_sync(&lif->deferred.work);
> +
> /* free lif info */
> dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
> lif->info = NULL;
> @@ -975,6 +1317,37 @@ static int ionic_init_nic_features(struct lif
> *lif)
> return 0;
> }
>
> +static int ionic_station_set(struct lif *lif)
> +{
> + struct net_device *netdev = lif->netdev;
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.lif_getattr = {
> + .opcode = CMD_OPCODE_LIF_GETATTR,
> + .index = cpu_to_le16(lif->index),
> + .attr = IONIC_LIF_ATTR_MAC,
> + },
> + };
> + int err;
> +
> + err = ionic_adminq_post_wait(lif, &ctx);
> + if (err)
> + return err;
> +
> + if (!is_zero_ether_addr(netdev->dev_addr)) {
> + netdev_dbg(lif->netdev, "deleting station MAC addr
> %pM\n",
> + netdev->dev_addr);
> + ionic_lif_addr(lif, netdev->dev_addr, false);
> + }
> + memcpy(netdev->dev_addr, ctx.comp.lif_getattr.mac,
> + netdev->addr_len);
> + netdev_dbg(lif->netdev, "adding station MAC addr %pM\n",
> + netdev->dev_addr);
> + ionic_lif_addr(lif, netdev->dev_addr, true);
> +
> + return 0;
> +}
> +
> static int ionic_lif_init(struct lif *lif)
> {
> struct ionic_dev *idev = &lif->ionic->idev;
> @@ -1039,6 +1412,10 @@ static int ionic_lif_init(struct lif *lif)
> if (err)
> goto err_out_notifyq_deinit;
>
> + err = ionic_station_set(lif);
> + if (err)
> + goto err_out_notifyq_deinit;
> +
> set_bit(LIF_INITED, lif->state);
>
> return 0;
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> index 9f112aa69033..20b4fa573f77 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> @@ -60,6 +60,29 @@ struct qcq {
> #define napi_to_qcq(napi) container_of(napi, struct qcq, napi)
> #define napi_to_cq(napi) (&napi_to_qcq(napi)->cq)
>
> +enum ionic_deferred_work_type {
> + DW_TYPE_RX_MODE,
> + DW_TYPE_RX_ADDR_ADD,
> + DW_TYPE_RX_ADDR_DEL,
> + DW_TYPE_LINK_STATUS,
> + DW_TYPE_LIF_RESET,
> +};
> +
> +struct ionic_deferred_work {
> + struct list_head list;
> + enum ionic_deferred_work_type type;
> + union {
> + unsigned int rx_mode;
> + u8 addr[ETH_ALEN];
> + };
> +};
> +
> +struct ionic_deferred {
> + spinlock_t lock; /* lock for deferred work list */
> + struct list_head list;
> + struct work_struct work;
> +};
> +
> enum lif_state_flags {
> LIF_INITED,
> LIF_UP,
> @@ -87,13 +110,19 @@ struct lif {
> u64 last_eid;
> unsigned int neqs;
> unsigned int nxqs;
> + unsigned int rx_mode;
> u64 hw_features;
> + bool mc_overflow;
> + unsigned int nmcast;
> + bool uc_overflow;
> + unsigned int nucast;
>
> struct lif_info *info;
> dma_addr_t info_pa;
> u32 info_sz;
>
> struct rx_filters rx_filters;
> + struct ionic_deferred deferred;
> unsigned long *dbid_inuse;
> unsigned int dbid_count;
> struct dentry *dentry;
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-23 23:20 ` Saeed Mahameed
@ 2019-07-24 0:07 ` Shannon Nelson
2019-07-24 21:10 ` Saeed Mahameed
0 siblings, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-24 0:07 UTC (permalink / raw)
To: Saeed Mahameed, netdev, davem
On 7/23/19 4:20 PM, Saeed Mahameed wrote:
> On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
>>
>> @@ -607,6 +947,8 @@ static void ionic_lif_free(struct lif *lif)
>> ionic_qcqs_free(lif);
>> ionic_lif_reset(lif);
>>
> I don't think you want deferred.work running while reset is executing..
> cancel_work_sync should happen as early as you close the netdevice.
Given the current implementation, it doesn't actually hurt anything, but
yes it makes sense to move it up in the sequence.
> I assume ionic_lif_reset will flush all configurations and you don't
> need to cleanup anything manually? or any data structure stored in
> driver ?
Most of the driver data structure cleaning has happened in
ionic_lif_deinit() before getting here.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support
2019-07-24 0:07 ` Shannon Nelson
@ 2019-07-24 21:10 ` Saeed Mahameed
0 siblings, 0 replies; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-24 21:10 UTC (permalink / raw)
To: snelson, netdev, davem
On Tue, 2019-07-23 at 17:07 -0700, Shannon Nelson wrote:
> On 7/23/19 4:20 PM, Saeed Mahameed wrote:
> > On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> > > @@ -607,6 +947,8 @@ static void ionic_lif_free(struct lif *lif)
> > > ionic_qcqs_free(lif);
> > > ionic_lif_reset(lif);
> > >
> > I don't think you want deferred.work running while reset is
> > executing..
> > cancel_work_sync should happen as early as you close the netdevice.
>
> Given the current implementation, it doesn't actually hurt anything,
> but
> yes it makes sense to move it up in the sequence.
>
> > I assume ionic_lif_reset will flush all configurations and you
> > don't
> > need to cleanup anything manually? or any data structure stored in
> > driver ?
>
> Most of the driver data structure cleaning has happened in
> ionic_lif_deinit() before getting here.
This means that yo do have a problem keeping the deferred.work running
after ionic_lif_deinit
>
> sln
>
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 12/19] ionic: Add async link status check and basic stats
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (10 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 11/19] ionic: Add Rx filter and rx_mode ndo support Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-25 0:04 ` Saeed Mahameed
2019-07-22 21:40 ` [PATCH v4 net-next 13/19] ionic: Add initial ethtool support Shannon Nelson
` (6 subsequent siblings)
18 siblings, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Add code to handle the link status event, and wire up the
basic netdev hardware stats.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
.../net/ethernet/pensando/ionic/ionic_lif.c | 116 ++++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_lif.h | 1 +
2 files changed, 117 insertions(+)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index efcda1337f91..f52af9cb6264 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -15,6 +15,7 @@
static void ionic_lif_rx_mode(struct lif *lif, unsigned int rx_mode);
static int ionic_lif_addr_add(struct lif *lif, const u8 *addr);
static int ionic_lif_addr_del(struct lif *lif, const u8 *addr);
+static void ionic_link_status_check(struct lif *lif);
static int ionic_set_nic_features(struct lif *lif, netdev_features_t features);
static int ionic_notifyq_clean(struct lif *lif, int budget);
@@ -44,6 +45,9 @@ static void ionic_lif_deferred_work(struct work_struct *work)
case DW_TYPE_RX_ADDR_DEL:
ionic_lif_addr_del(lif, w->addr);
break;
+ case DW_TYPE_LINK_STATUS:
+ ionic_link_status_check(lif);
+ break;
default:
break;
}
@@ -69,6 +73,7 @@ int ionic_open(struct net_device *netdev)
set_bit(LIF_UP, lif->state);
+ ionic_link_status_check(lif);
if (netif_carrier_ok(netdev))
netif_tx_wake_all_queues(netdev);
@@ -151,6 +156,39 @@ static int ionic_adminq_napi(struct napi_struct *napi, int budget)
return max(n_work, a_work);
}
+static void ionic_link_status_check(struct lif *lif)
+{
+ struct net_device *netdev = lif->netdev;
+ u16 link_status;
+ bool link_up;
+
+ clear_bit(LIF_LINK_CHECK_NEEDED, lif->state);
+
+ link_status = le16_to_cpu(lif->info->status.link_status);
+ link_up = link_status == PORT_OPER_STATUS_UP;
+
+ /* filter out the no-change cases */
+ if (link_up == netif_carrier_ok(netdev))
+ return;
+
+ if (link_up) {
+ netdev_info(netdev, "Link up - %d Gbps\n",
+ le32_to_cpu(lif->info->status.link_speed) / 1000);
+
+ if (test_bit(LIF_UP, lif->state)) {
+ netif_tx_wake_all_queues(lif->netdev);
+ netif_carrier_on(netdev);
+ }
+ } else {
+ netdev_info(netdev, "Link down\n");
+
+ /* carrier off first to avoid watchdog timeout */
+ netif_carrier_off(netdev);
+ if (test_bit(LIF_UP, lif->state))
+ netif_tx_stop_all_queues(netdev);
+ }
+}
+
static bool ionic_notifyq_service(struct cq *cq, struct cq_info *cq_info)
{
union notifyq_comp *comp = cq_info->cq_desc;
@@ -182,6 +220,9 @@ static bool ionic_notifyq_service(struct cq *cq, struct cq_info *cq_info)
" link_status=%d link_speed=%d\n",
le16_to_cpu(comp->link_change.link_status),
le32_to_cpu(comp->link_change.link_speed));
+
+ set_bit(LIF_LINK_CHECK_NEEDED, lif->state);
+
break;
case EVENT_OPCODE_RESET:
netdev_info(netdev, "Notifyq EVENT_OPCODE_RESET eid=%lld\n",
@@ -222,10 +263,81 @@ static int ionic_notifyq_clean(struct lif *lif, int budget)
if (work_done == budget)
goto return_to_napi;
+ /* After outstanding events are processed we can check on
+ * the link status and any outstanding interrupt credits.
+ *
+ * We wait until here to check on the link status in case
+ * there was a long list of link events from a flap episode.
+ */
+ if (test_bit(LIF_LINK_CHECK_NEEDED, lif->state)) {
+ struct ionic_deferred_work *work;
+
+ work = kzalloc(sizeof(*work), GFP_ATOMIC);
+ if (!work) {
+ netdev_err(lif->netdev, "%s OOM\n", __func__);
+ } else {
+ work->type = DW_TYPE_LINK_STATUS;
+ ionic_lif_deferred_enqueue(&lif->deferred, work);
+ }
+ }
+
return_to_napi:
return work_done;
}
+static void ionic_get_stats64(struct net_device *netdev,
+ struct rtnl_link_stats64 *ns)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct lif_stats *ls;
+
+ memset(ns, 0, sizeof(*ns));
+ ls = &lif->info->stats;
+
+ ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) +
+ le64_to_cpu(ls->rx_mcast_packets) +
+ le64_to_cpu(ls->rx_bcast_packets);
+
+ ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) +
+ le64_to_cpu(ls->tx_mcast_packets) +
+ le64_to_cpu(ls->tx_bcast_packets);
+
+ ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) +
+ le64_to_cpu(ls->rx_mcast_bytes) +
+ le64_to_cpu(ls->rx_bcast_bytes);
+
+ ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) +
+ le64_to_cpu(ls->tx_mcast_bytes) +
+ le64_to_cpu(ls->tx_bcast_bytes);
+
+ ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) +
+ le64_to_cpu(ls->rx_mcast_drop_packets) +
+ le64_to_cpu(ls->rx_bcast_drop_packets);
+
+ ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) +
+ le64_to_cpu(ls->tx_mcast_drop_packets) +
+ le64_to_cpu(ls->tx_bcast_drop_packets);
+
+ ns->multicast = le64_to_cpu(ls->rx_mcast_packets);
+
+ ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty);
+
+ ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) +
+ le64_to_cpu(ls->rx_queue_disabled) +
+ le64_to_cpu(ls->rx_desc_fetch_error) +
+ le64_to_cpu(ls->rx_desc_data_error);
+
+ ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) +
+ le64_to_cpu(ls->tx_queue_disabled) +
+ le64_to_cpu(ls->tx_desc_fetch_error) +
+ le64_to_cpu(ls->tx_desc_data_error);
+
+ ns->rx_errors = ns->rx_over_errors +
+ ns->rx_missed_errors;
+
+ ns->tx_errors = ns->tx_aborted_errors;
+}
+
static int ionic_lif_addr_add(struct lif *lif, const u8 *addr)
{
struct ionic_admin_ctx ctx = {
@@ -581,6 +693,7 @@ static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
static const struct net_device_ops ionic_netdev_ops = {
.ndo_open = ionic_open,
.ndo_stop = ionic_stop,
+ .ndo_get_stats64 = ionic_get_stats64,
.ndo_set_rx_mode = ionic_set_rx_mode,
.ndo_set_features = ionic_set_features,
.ndo_set_mac_address = ionic_set_mac_address,
@@ -1418,6 +1531,8 @@ static int ionic_lif_init(struct lif *lif)
set_bit(LIF_INITED, lif->state);
+ ionic_link_status_check(lif);
+
return 0;
err_out_notifyq_deinit:
@@ -1461,6 +1576,7 @@ int ionic_lifs_register(struct ionic *ionic)
return err;
}
+ ionic_link_status_check(ionic->master_lif);
ionic->master_lif->registered = true;
return 0;
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index 20b4fa573f77..9930b9390c8a 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -86,6 +86,7 @@ struct ionic_deferred {
enum lif_state_flags {
LIF_INITED,
LIF_UP,
+ LIF_LINK_CHECK_NEEDED,
LIF_QUEUE_RESET,
/* leave this as last */
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 12/19] ionic: Add async link status check and basic stats
2019-07-22 21:40 ` [PATCH v4 net-next 12/19] ionic: Add async link status check and basic stats Shannon Nelson
@ 2019-07-25 0:04 ` Saeed Mahameed
2019-07-30 18:35 ` Shannon Nelson
0 siblings, 1 reply; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-25 0:04 UTC (permalink / raw)
To: snelson, netdev, davem
On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> Add code to handle the link status event, and wire up the
> basic netdev hardware stats.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
> ---
> .../net/ethernet/pensando/ionic/ionic_lif.c | 116
> ++++++++++++++++++
> .../net/ethernet/pensando/ionic/ionic_lif.h | 1 +
> 2 files changed, 117 insertions(+)
>
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> index efcda1337f91..f52af9cb6264 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> @@ -15,6 +15,7 @@
> static void ionic_lif_rx_mode(struct lif *lif, unsigned int
> rx_mode);
> static int ionic_lif_addr_add(struct lif *lif, const u8 *addr);
> static int ionic_lif_addr_del(struct lif *lif, const u8 *addr);
> +static void ionic_link_status_check(struct lif *lif);
>
> static int ionic_set_nic_features(struct lif *lif, netdev_features_t
> features);
> static int ionic_notifyq_clean(struct lif *lif, int budget);
> @@ -44,6 +45,9 @@ static void ionic_lif_deferred_work(struct
> work_struct *work)
> case DW_TYPE_RX_ADDR_DEL:
> ionic_lif_addr_del(lif, w->addr);
> break;
> + case DW_TYPE_LINK_STATUS:
> + ionic_link_status_check(lif);
> + break;
> default:
> break;
> }
> @@ -69,6 +73,7 @@ int ionic_open(struct net_device *netdev)
>
> set_bit(LIF_UP, lif->state);
>
> + ionic_link_status_check(lif);
> if (netif_carrier_ok(netdev))
> netif_tx_wake_all_queues(netdev);
>
> @@ -151,6 +156,39 @@ static int ionic_adminq_napi(struct napi_struct
> *napi, int budget)
> return max(n_work, a_work);
> }
>
> +static void ionic_link_status_check(struct lif *lif)
> +{
> + struct net_device *netdev = lif->netdev;
> + u16 link_status;
> + bool link_up;
> +
> + clear_bit(LIF_LINK_CHECK_NEEDED, lif->state);
> +
> + link_status = le16_to_cpu(lif->info->status.link_status);
> + link_up = link_status == PORT_OPER_STATUS_UP;
> +
> + /* filter out the no-change cases */
> + if (link_up == netif_carrier_ok(netdev))
> + return;
> +
> + if (link_up) {
> + netdev_info(netdev, "Link up - %d Gbps\n",
> + le32_to_cpu(lif->info->status.link_speed) /
> 1000);
> +
> + if (test_bit(LIF_UP, lif->state)) {
> + netif_tx_wake_all_queues(lif->netdev);
> + netif_carrier_on(netdev);
> + }
> + } else {
> + netdev_info(netdev, "Link down\n");
> +
> + /* carrier off first to avoid watchdog timeout */
> + netif_carrier_off(netdev);
> + if (test_bit(LIF_UP, lif->state))
> + netif_tx_stop_all_queues(netdev);
> + }
> +}
> +
> static bool ionic_notifyq_service(struct cq *cq, struct cq_info
> *cq_info)
> {
> union notifyq_comp *comp = cq_info->cq_desc;
> @@ -182,6 +220,9 @@ static bool ionic_notifyq_service(struct cq *cq,
> struct cq_info *cq_info)
> " link_status=%d link_speed=%d\n",
> le16_to_cpu(comp->link_change.link_status),
> le32_to_cpu(comp->link_change.link_speed));
> +
> + set_bit(LIF_LINK_CHECK_NEEDED, lif->state);
> +
> break;
> case EVENT_OPCODE_RESET:
> netdev_info(netdev, "Notifyq EVENT_OPCODE_RESET
> eid=%lld\n",
> @@ -222,10 +263,81 @@ static int ionic_notifyq_clean(struct lif *lif,
> int budget)
> if (work_done == budget)
> goto return_to_napi;
>
> + /* After outstanding events are processed we can check on
> + * the link status and any outstanding interrupt credits.
> + *
> + * We wait until here to check on the link status in case
> + * there was a long list of link events from a flap episode.
> + */
> + if (test_bit(LIF_LINK_CHECK_NEEDED, lif->state)) {
> + struct ionic_deferred_work *work;
> +
> + work = kzalloc(sizeof(*work), GFP_ATOMIC);
> + if (!work) {
> + netdev_err(lif->netdev, "%s OOM\n", __func__);
why not having a pre allocated dedicated lif->link_check_work, instead
of allocating in atomic context on every link check event ?
> + } else {
> + work->type = DW_TYPE_LINK_STATUS;
> + ionic_lif_deferred_enqueue(&lif->deferred,
> work);
> + }
> + }
> +
> return_to_napi:
> return work_done;
> }
>
> +static void ionic_get_stats64(struct net_device *netdev,
> + struct rtnl_link_stats64 *ns)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct lif_stats *ls;
> +
> + memset(ns, 0, sizeof(*ns));
> + ls = &lif->info->stats;
> +
> + ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) +
> + le64_to_cpu(ls->rx_mcast_packets) +
> + le64_to_cpu(ls->rx_bcast_packets);
> +
> + ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) +
> + le64_to_cpu(ls->tx_mcast_packets) +
> + le64_to_cpu(ls->tx_bcast_packets);
> +
> + ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) +
> + le64_to_cpu(ls->rx_mcast_bytes) +
> + le64_to_cpu(ls->rx_bcast_bytes);
> +
> + ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) +
> + le64_to_cpu(ls->tx_mcast_bytes) +
> + le64_to_cpu(ls->tx_bcast_bytes);
> +
> + ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) +
> + le64_to_cpu(ls->rx_mcast_drop_packets) +
> + le64_to_cpu(ls->rx_bcast_drop_packets);
> +
> + ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) +
> + le64_to_cpu(ls->tx_mcast_drop_packets) +
> + le64_to_cpu(ls->tx_bcast_drop_packets);
> +
> + ns->multicast = le64_to_cpu(ls->rx_mcast_packets);
> +
> + ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty);
> +
> + ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) +
> + le64_to_cpu(ls->rx_queue_disabled) +
> + le64_to_cpu(ls->rx_desc_fetch_error) +
> + le64_to_cpu(ls->rx_desc_data_error);
> +
> + ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) +
> + le64_to_cpu(ls->tx_queue_disabled) +
> + le64_to_cpu(ls->tx_desc_fetch_error) +
> + le64_to_cpu(ls->tx_desc_data_error);
> +
> + ns->rx_errors = ns->rx_over_errors +
> + ns->rx_missed_errors;
> +
> + ns->tx_errors = ns->tx_aborted_errors;
> +}
> +
> static int ionic_lif_addr_add(struct lif *lif, const u8 *addr)
> {
> struct ionic_admin_ctx ctx = {
> @@ -581,6 +693,7 @@ static int ionic_vlan_rx_kill_vid(struct
> net_device *netdev, __be16 proto,
> static const struct net_device_ops ionic_netdev_ops = {
> .ndo_open = ionic_open,
> .ndo_stop = ionic_stop,
> + .ndo_get_stats64 = ionic_get_stats64,
> .ndo_set_rx_mode = ionic_set_rx_mode,
> .ndo_set_features = ionic_set_features,
> .ndo_set_mac_address = ionic_set_mac_address,
> @@ -1418,6 +1531,8 @@ static int ionic_lif_init(struct lif *lif)
>
> set_bit(LIF_INITED, lif->state);
>
> + ionic_link_status_check(lif);
> +
> return 0;
>
> err_out_notifyq_deinit:
> @@ -1461,6 +1576,7 @@ int ionic_lifs_register(struct ionic *ionic)
> return err;
> }
>
are events (NotifyQ) enabled at this stage ? if so then you might endup
racing ionic_link_status_check with itself.
> + ionic_link_status_check(ionic->master_lif);
> ionic->master_lif->registered = true;
>
> return 0;
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> index 20b4fa573f77..9930b9390c8a 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> @@ -86,6 +86,7 @@ struct ionic_deferred {
> enum lif_state_flags {
> LIF_INITED,
> LIF_UP,
> + LIF_LINK_CHECK_NEEDED,
> LIF_QUEUE_RESET,
>
> /* leave this as last */
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 12/19] ionic: Add async link status check and basic stats
2019-07-25 0:04 ` Saeed Mahameed
@ 2019-07-30 18:35 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-30 18:35 UTC (permalink / raw)
To: Saeed Mahameed, netdev, davem
On 7/24/19 5:04 PM, Saeed Mahameed wrote:
> On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
>> Add code to handle the link status event, and wire up the
>> basic netdev hardware stats.
>>
>> Signed-off-by: Shannon Nelson<snelson@pensando.io>
>> ---
>> .../net/ethernet/pensando/ionic/ionic_lif.c | 116
>> ++++++++++++++++++
>> .../net/ethernet/pensando/ionic/ionic_lif.h | 1 +
>> 2 files changed, 117 insertions(+)
[...]
>> + /* After outstanding events are processed we can check on
>> + * the link status and any outstanding interrupt credits.
>> + *
>> + * We wait until here to check on the link status in case
>> + * there was a long list of link events from a flap episode.
>> + */
>> + if (test_bit(LIF_LINK_CHECK_NEEDED, lif->state)) {
>> + struct ionic_deferred_work *work;
>> +
>> + work = kzalloc(sizeof(*work), GFP_ATOMIC);
>> + if (!work) {
>> + netdev_err(lif->netdev, "%s OOM\n", __func__);
> why not having a pre allocated dedicated lif->link_check_work, instead
> of allocating in atomic context on every link check event ?
I don't want to worry about the possibility of additional requests
driven from other threads using the same struct.
>> + } else {
>> + work->type = DW_TYPE_LINK_STATUS;
>> + ionic_lif_deferred_enqueue(&lif->deferred,
>> work);
>> + }
>> + }
>> +
>> return_to_napi:
>> return work_done;
>> }
>>
>> +static void ionic_get_stats64(struct net_device *netdev,
>> + struct rtnl_link_stats64 *ns)
>> +{
>> + struct lif *lif = netdev_priv(netdev);
>> + struct lif_stats *ls;
>> +
>> + memset(ns, 0, sizeof(*ns));
>> + ls = &lif->info->stats;
>> +
>> + ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) +
>> + le64_to_cpu(ls->rx_mcast_packets) +
>> + le64_to_cpu(ls->rx_bcast_packets);
>> +
>> + ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) +
>> + le64_to_cpu(ls->tx_mcast_packets) +
>> + le64_to_cpu(ls->tx_bcast_packets);
>> +
>> + ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) +
>> + le64_to_cpu(ls->rx_mcast_bytes) +
>> + le64_to_cpu(ls->rx_bcast_bytes);
>> +
>> + ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) +
>> + le64_to_cpu(ls->tx_mcast_bytes) +
>> + le64_to_cpu(ls->tx_bcast_bytes);
>> +
>> + ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) +
>> + le64_to_cpu(ls->rx_mcast_drop_packets) +
>> + le64_to_cpu(ls->rx_bcast_drop_packets);
>> +
>> + ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) +
>> + le64_to_cpu(ls->tx_mcast_drop_packets) +
>> + le64_to_cpu(ls->tx_bcast_drop_packets);
>> +
>> + ns->multicast = le64_to_cpu(ls->rx_mcast_packets);
>> +
>> + ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty);
>> +
>> + ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) +
>> + le64_to_cpu(ls->rx_queue_disabled) +
>> + le64_to_cpu(ls->rx_desc_fetch_error) +
>> + le64_to_cpu(ls->rx_desc_data_error);
>> +
>> + ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) +
>> + le64_to_cpu(ls->tx_queue_disabled) +
>> + le64_to_cpu(ls->tx_desc_fetch_error) +
>> + le64_to_cpu(ls->tx_desc_data_error);
>> +
>> + ns->rx_errors = ns->rx_over_errors +
>> + ns->rx_missed_errors;
>> +
>> + ns->tx_errors = ns->tx_aborted_errors;
>> +}
>> +
>> static int ionic_lif_addr_add(struct lif *lif, const u8 *addr)
>> {
>> struct ionic_admin_ctx ctx = {
>> @@ -581,6 +693,7 @@ static int ionic_vlan_rx_kill_vid(struct
>> net_device *netdev, __be16 proto,
>> static const struct net_device_ops ionic_netdev_ops = {
>> .ndo_open = ionic_open,
>> .ndo_stop = ionic_stop,
>> + .ndo_get_stats64 = ionic_get_stats64,
>> .ndo_set_rx_mode = ionic_set_rx_mode,
>> .ndo_set_features = ionic_set_features,
>> .ndo_set_mac_address = ionic_set_mac_address,
>> @@ -1418,6 +1531,8 @@ static int ionic_lif_init(struct lif *lif)
>>
>> set_bit(LIF_INITED, lif->state);
>>
>> + ionic_link_status_check(lif);
>> +
>> return 0;
>>
>> err_out_notifyq_deinit:
>> @@ -1461,6 +1576,7 @@ int ionic_lifs_register(struct ionic *ionic)
>> return err;
>> }
>>
> are events (NotifyQ) enabled at this stage ? if so then you might endup
> racing ionic_link_status_check with itself.
I'll look at that again to see what such a race might do. I probably
should add a test here and in a couple other spots to see if the link
status check has already been requested.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 13/19] ionic: Add initial ethtool support
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (11 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 12/19] ionic: Add async link status check and basic stats Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-23 21:35 ` David Miller
` (3 more replies)
2019-07-22 21:40 ` [PATCH v4 net-next 14/19] ionic: Add Tx and Rx handling Shannon Nelson
` (5 subsequent siblings)
18 siblings, 4 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Add in the basic ethtool callbacks for device information
and control.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/Makefile | 2 +-
.../net/ethernet/pensando/ionic/ionic_dev.h | 3 +
.../ethernet/pensando/ionic/ionic_ethtool.c | 495 ++++++++++++++++++
.../ethernet/pensando/ionic/ionic_ethtool.h | 9 +
.../net/ethernet/pensando/ionic/ionic_lif.c | 2 +
.../net/ethernet/pensando/ionic/ionic_lif.h | 8 +
6 files changed, 518 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_ethtool.h
diff --git a/drivers/net/ethernet/pensando/ionic/Makefile b/drivers/net/ethernet/pensando/ionic/Makefile
index 7d9cdc5f02a1..9b19bf57a489 100644
--- a/drivers/net/ethernet/pensando/ionic/Makefile
+++ b/drivers/net/ethernet/pensando/ionic/Makefile
@@ -3,5 +3,5 @@
obj-$(CONFIG_IONIC) := ionic.o
-ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o \
+ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_ethtool.o \
ionic_lif.o ionic_rx_filter.o ionic_debugfs.o
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
index 523927566925..bacc9c557329 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_dev.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
@@ -12,6 +12,9 @@
#define IONIC_MIN_MTU ETH_MIN_MTU
#define IONIC_MAX_MTU 9194
+#define IONIC_MAX_TXRX_DESC 16384
+#define IONIC_MIN_TXRX_DESC 16
+#define IONIC_DEF_TXRX_DESC 4096
#define IONIC_LIFS_MAX 1024
struct ionic_dev_bar {
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
new file mode 100644
index 000000000000..f7899be547c3
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#include <linux/module.h>
+#include <linux/netdevice.h>
+
+#include "ionic.h"
+#include "ionic_bus.h"
+#include "ionic_lif.h"
+#include "ionic_ethtool.h"
+
+static void ionic_get_drvinfo(struct net_device *netdev,
+ struct ethtool_drvinfo *drvinfo)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic *ionic = lif->ionic;
+ struct ionic_dev *idev = &ionic->idev;
+
+ strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
+ strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
+ strlcpy(drvinfo->fw_version, idev->dev_info.fw_version,
+ sizeof(drvinfo->fw_version));
+ strlcpy(drvinfo->bus_info, ionic_bus_info(ionic),
+ sizeof(drvinfo->bus_info));
+}
+
+#define DEV_CMD_REG_VERSION 1
+#define DEV_INFO_REG_COUNT 32
+#define DEV_CMD_REG_COUNT 32
+static int ionic_get_regs_len(struct net_device *netdev)
+{
+ return (DEV_INFO_REG_COUNT + DEV_CMD_REG_COUNT) * sizeof(u32);
+}
+
+static void ionic_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
+ void *p)
+{
+ struct lif *lif = netdev_priv(netdev);
+ unsigned int size;
+
+ regs->version = DEV_CMD_REG_VERSION;
+
+ size = DEV_INFO_REG_COUNT * sizeof(u32);
+ memcpy_fromio(p, lif->ionic->idev.dev_info_regs->words, size);
+
+ size = DEV_CMD_REG_COUNT * sizeof(u32);
+ memcpy_fromio(p, lif->ionic->idev.dev_cmd_regs->words, size);
+}
+
+static int ionic_get_link_ksettings(struct net_device *netdev,
+ struct ethtool_link_ksettings *ks)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic_dev *idev = &lif->ionic->idev;
+ int copper_seen = 0;
+
+ ethtool_link_ksettings_zero_link_mode(ks, supported);
+
+ /* The port_info data is found in a DMA space that the NIC keeps
+ * up-to-date, so there's no need to request the data from the
+ * NIC, we already have it in our memory space.
+ */
+
+ switch (le16_to_cpu(idev->port_info->status.xcvr.pid)) {
+ /* Copper */
+ case XCVR_PID_QSFP_100G_CR4:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 100000baseCR4_Full);
+ copper_seen++;
+ break;
+ case XCVR_PID_QSFP_40GBASE_CR4:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 40000baseCR4_Full);
+ copper_seen++;
+ break;
+ case XCVR_PID_SFP_25GBASE_CR_S:
+ case XCVR_PID_SFP_25GBASE_CR_L:
+ case XCVR_PID_SFP_25GBASE_CR_N:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 25000baseCR_Full);
+ copper_seen++;
+ break;
+ case XCVR_PID_SFP_10GBASE_AOC:
+ case XCVR_PID_SFP_10GBASE_CU:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 10000baseCR_Full);
+ copper_seen++;
+ break;
+
+ /* Fibre */
+ case XCVR_PID_QSFP_100G_SR4:
+ case XCVR_PID_QSFP_100G_AOC:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 100000baseSR4_Full);
+ break;
+ case XCVR_PID_QSFP_100G_LR4:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 100000baseLR4_ER4_Full);
+ break;
+ case XCVR_PID_QSFP_100G_ER4:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 100000baseLR4_ER4_Full);
+ break;
+ case XCVR_PID_QSFP_40GBASE_SR4:
+ case XCVR_PID_QSFP_40GBASE_AOC:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 40000baseSR4_Full);
+ break;
+ case XCVR_PID_QSFP_40GBASE_LR4:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 40000baseLR4_Full);
+ break;
+ case XCVR_PID_SFP_25GBASE_SR:
+ case XCVR_PID_SFP_25GBASE_AOC:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 25000baseSR_Full);
+ break;
+ case XCVR_PID_SFP_10GBASE_SR:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 10000baseSR_Full);
+ break;
+ case XCVR_PID_SFP_10GBASE_LR:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 10000baseLR_Full);
+ break;
+ case XCVR_PID_SFP_10GBASE_LRM:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 10000baseLRM_Full);
+ break;
+ case XCVR_PID_SFP_10GBASE_ER:
+ ethtool_link_ksettings_add_link_mode(ks, supported,
+ 10000baseER_Full);
+ break;
+ case XCVR_PID_UNKNOWN:
+ break;
+ default:
+ dev_info(lif->ionic->dev, "unknown xcvr type pid=%d / 0x%x\n",
+ idev->port_info->status.xcvr.pid,
+ idev->port_info->status.xcvr.pid);
+ break;
+ }
+ ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
+
+ if (ionic_is_pf(lif->ionic))
+ ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
+
+ bitmap_copy(ks->link_modes.advertising, ks->link_modes.supported,
+ __ETHTOOL_LINK_MODE_MASK_NBITS);
+
+ ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
+ ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
+ ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
+
+ if (idev->port_info->config.fec_type == PORT_FEC_TYPE_FC)
+ ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_BASER);
+ else if (idev->port_info->config.fec_type == PORT_FEC_TYPE_RS)
+ ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
+ else if (idev->port_info->config.fec_type == PORT_FEC_TYPE_NONE)
+ ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_NONE);
+
+ ethtool_link_ksettings_add_link_mode(ks, supported, Pause);
+ if (idev->port_info->config.pause_type)
+ ethtool_link_ksettings_add_link_mode(ks, advertising, Pause);
+
+ if (idev->port_info->status.xcvr.phy == PHY_TYPE_COPPER ||
+ copper_seen) {
+ ks->base.port = PORT_DA;
+ } else if (idev->port_info->status.xcvr.phy == PHY_TYPE_FIBER) {
+ ks->base.port = PORT_FIBRE;
+ } else {
+ ks->base.port = PORT_OTHER;
+ }
+
+ ks->base.speed = le32_to_cpu(lif->info->status.link_speed);
+
+ if (idev->port_info->config.an_enable)
+ ks->base.autoneg = AUTONEG_ENABLE;
+
+ if (le16_to_cpu(lif->info->status.link_status))
+ ks->base.duplex = DUPLEX_FULL;
+ else
+ ks->base.duplex = DUPLEX_UNKNOWN;
+
+ return 0;
+}
+
+static int ionic_set_link_ksettings(struct net_device *netdev,
+ const struct ethtool_link_ksettings *ks)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic *ionic = lif->ionic;
+ struct ionic_dev *idev = &lif->ionic->idev;
+ u8 fec_type = PORT_FEC_TYPE_NONE;
+ u32 req_rs, req_fc;
+ int err = 0;
+
+ /* set autoneg */
+ if (ks->base.autoneg != idev->port_info->config.an_enable) {
+ mutex_lock(&ionic->dev_cmd_lock);
+ ionic_dev_cmd_port_autoneg(idev, ks->base.autoneg);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ mutex_unlock(&ionic->dev_cmd_lock);
+ if (err)
+ return err;
+ }
+
+ /* set speed */
+ if (ks->base.speed != le32_to_cpu(idev->port_info->config.speed)) {
+ mutex_lock(&ionic->dev_cmd_lock);
+ ionic_dev_cmd_port_speed(idev, ks->base.speed);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ mutex_unlock(&ionic->dev_cmd_lock);
+ if (err)
+ return err;
+ }
+
+ /* set FEC */
+ req_rs = ethtool_link_ksettings_test_link_mode(ks, advertising, FEC_RS);
+ req_fc = ethtool_link_ksettings_test_link_mode(ks, advertising, FEC_BASER);
+ if (req_rs && req_fc) {
+ netdev_info(netdev, "Only select one FEC mode at a time\n");
+ return -EINVAL;
+ } else if (req_fc &&
+ idev->port_info->config.fec_type != PORT_FEC_TYPE_FC) {
+ fec_type = PORT_FEC_TYPE_FC;
+ } else if (req_rs &&
+ idev->port_info->config.fec_type != PORT_FEC_TYPE_RS) {
+ fec_type = PORT_FEC_TYPE_RS;
+ } else if (!(req_rs | req_fc) &&
+ idev->port_info->config.fec_type != PORT_FEC_TYPE_NONE) {
+ fec_type = PORT_FEC_TYPE_NONE;
+ }
+
+ if (fec_type != idev->port_info->config.fec_type) {
+ mutex_lock(&ionic->dev_cmd_lock);
+ ionic_dev_cmd_port_fec(idev, fec_type);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ mutex_unlock(&ionic->dev_cmd_lock);
+ if (err)
+ return err;
+
+ idev->port_info->config.fec_type = fec_type;
+ }
+
+ return 0;
+}
+
+static void ionic_get_pauseparam(struct net_device *netdev,
+ struct ethtool_pauseparam *pause)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic_dev *idev = &lif->ionic->idev;
+ uint8_t pause_type = idev->port_info->config.pause_type;
+
+ pause->autoneg = 0;
+
+ if (pause_type) {
+ pause->rx_pause = pause_type & IONIC_PAUSE_F_RX ? 1 : 0;
+ pause->tx_pause = pause_type & IONIC_PAUSE_F_TX ? 1 : 0;
+ }
+}
+
+static int ionic_set_pauseparam(struct net_device *netdev,
+ struct ethtool_pauseparam *pause)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic *ionic = lif->ionic;
+ struct ionic_dev *idev = &lif->ionic->idev;
+ u32 requested_pause;
+ int err;
+
+ if (pause->autoneg == AUTONEG_ENABLE) {
+ netdev_info(netdev, "Please use 'ethtool -s ...' to change autoneg\n");
+ return -EOPNOTSUPP;
+ }
+
+ /* change both at the same time */
+ requested_pause = PORT_PAUSE_TYPE_LINK;
+ if (pause->rx_pause)
+ requested_pause |= IONIC_PAUSE_F_RX;
+ if (pause->tx_pause)
+ requested_pause |= IONIC_PAUSE_F_TX;
+
+ if (requested_pause == idev->port_info->config.pause_type)
+ return 0;
+
+ idev->port_info->config.pause_type = requested_pause;
+
+ mutex_lock(&ionic->dev_cmd_lock);
+ ionic_dev_cmd_port_pause(idev, requested_pause);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ mutex_unlock(&ionic->dev_cmd_lock);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static int ionic_get_coalesce(struct net_device *netdev,
+ struct ethtool_coalesce *coalesce)
+{
+ struct lif *lif = netdev_priv(netdev);
+
+ coalesce->tx_coalesce_usecs = lif->tx_coalesce_usecs;
+ coalesce->rx_coalesce_usecs = lif->rx_coalesce_usecs;
+
+ return 0;
+}
+
+static void ionic_get_ringparam(struct net_device *netdev,
+ struct ethtool_ringparam *ring)
+{
+ struct lif *lif = netdev_priv(netdev);
+
+ ring->tx_max_pending = IONIC_MAX_TXRX_DESC;
+ ring->tx_pending = lif->ntxq_descs;
+ ring->rx_max_pending = IONIC_MAX_TXRX_DESC;
+ ring->rx_pending = lif->nrxq_descs;
+}
+
+static int ionic_set_ringparam(struct net_device *netdev,
+ struct ethtool_ringparam *ring)
+{
+ struct lif *lif = netdev_priv(netdev);
+ bool running;
+
+ if (ring->rx_mini_pending || ring->rx_jumbo_pending) {
+ netdev_info(netdev, "Changing jumbo or mini descriptors not supported\n");
+ return -EINVAL;
+ }
+
+ if (!is_power_of_2(ring->tx_pending) ||
+ !is_power_of_2(ring->rx_pending)) {
+ netdev_info(netdev, "Descriptor count must be a power of 2\n");
+ return -EINVAL;
+ }
+
+ /* if nothing to do return success */
+ if (ring->tx_pending == lif->ntxq_descs &&
+ ring->rx_pending == lif->nrxq_descs)
+ return 0;
+
+ while (test_and_set_bit(LIF_QUEUE_RESET, lif->state))
+ usleep_range(200, 400);
+
+ running = test_bit(LIF_UP, lif->state);
+ if (running)
+ ionic_stop(netdev);
+
+ lif->ntxq_descs = ring->tx_pending;
+ lif->nrxq_descs = ring->rx_pending;
+
+ if (running)
+ ionic_open(netdev);
+ clear_bit(LIF_QUEUE_RESET, lif->state);
+
+ return 0;
+}
+
+static void ionic_get_channels(struct net_device *netdev,
+ struct ethtool_channels *ch)
+{
+ struct lif *lif = netdev_priv(netdev);
+
+ /* report maximum channels */
+ ch->max_combined = lif->ionic->ntxqs_per_lif;
+
+ /* report current channels */
+ ch->combined_count = lif->nxqs;
+}
+
+static int ionic_set_channels(struct net_device *netdev,
+ struct ethtool_channels *ch)
+{
+ struct lif *lif = netdev_priv(netdev);
+ bool running;
+
+ if (!ch->combined_count || ch->other_count ||
+ ch->rx_count || ch->tx_count)
+ return -EINVAL;
+
+ if (ch->combined_count == lif->nxqs)
+ return 0;
+
+ while (test_and_set_bit(LIF_QUEUE_RESET, lif->state))
+ usleep_range(200, 400);
+
+ running = test_bit(LIF_UP, lif->state);
+ if (running)
+ ionic_stop(netdev);
+
+ lif->nxqs = ch->combined_count;
+
+ if (running)
+ ionic_open(netdev);
+ clear_bit(LIF_QUEUE_RESET, lif->state);
+
+ return 0;
+}
+
+static int ionic_get_module_info(struct net_device *netdev,
+ struct ethtool_modinfo *modinfo)
+
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic_dev *idev = &lif->ionic->idev;
+ struct xcvr_status *xcvr;
+
+ xcvr = &idev->port_info->status.xcvr;
+
+ /* report the module data type and length */
+ switch (xcvr->sprom[0]) {
+ case 0x03: /* SFP */
+ modinfo->type = ETH_MODULE_SFF_8079;
+ modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
+ break;
+ case 0x0D: /* QSFP */
+ case 0x11: /* QSFP28 */
+ modinfo->type = ETH_MODULE_SFF_8436;
+ modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
+ break;
+ default:
+ netdev_info(netdev, "unknown xcvr type 0x%02x\n",
+ xcvr->sprom[0]);
+ break;
+ }
+
+ return 0;
+}
+
+static int ionic_get_module_eeprom(struct net_device *netdev,
+ struct ethtool_eeprom *ee,
+ u8 *data)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic_dev *idev = &lif->ionic->idev;
+ struct xcvr_status *xcvr;
+ u32 len;
+
+ /* The NIC keeps the module prom up-to-date in the DMA space
+ * so we can simply copy the module bytes into the data buffer.
+ */
+ xcvr = &idev->port_info->status.xcvr;
+ len = min_t(u32, sizeof(xcvr->sprom), ee->len);
+ memcpy(data, xcvr->sprom, len);
+
+ return 0;
+}
+
+static int ionic_nway_reset(struct net_device *netdev)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct ionic *ionic = lif->ionic;
+ int err = 0;
+
+ /* flap the link to force auto-negotiation */
+
+ mutex_lock(&ionic->dev_cmd_lock);
+
+ ionic_dev_cmd_port_state(&ionic->idev, PORT_ADMIN_STATE_DOWN);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+
+ if (!err) {
+ ionic_dev_cmd_port_state(&ionic->idev, PORT_ADMIN_STATE_UP);
+ err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
+ }
+
+ mutex_unlock(&ionic->dev_cmd_lock);
+
+ return err;
+}
+
+static const struct ethtool_ops ionic_ethtool_ops = {
+ .get_drvinfo = ionic_get_drvinfo,
+ .get_regs_len = ionic_get_regs_len,
+ .get_regs = ionic_get_regs,
+ .get_link = ethtool_op_get_link,
+ .get_link_ksettings = ionic_get_link_ksettings,
+ .get_coalesce = ionic_get_coalesce,
+ .get_ringparam = ionic_get_ringparam,
+ .set_ringparam = ionic_set_ringparam,
+ .get_channels = ionic_get_channels,
+ .set_channels = ionic_set_channels,
+ .get_module_info = ionic_get_module_info,
+ .get_module_eeprom = ionic_get_module_eeprom,
+ .get_pauseparam = ionic_get_pauseparam,
+ .set_pauseparam = ionic_set_pauseparam,
+ .set_link_ksettings = ionic_set_link_ksettings,
+ .nway_reset = ionic_nway_reset,
+};
+
+void ionic_ethtool_set_ops(struct net_device *netdev)
+{
+ netdev->ethtool_ops = &ionic_ethtool_ops;
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.h b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.h
new file mode 100644
index 000000000000..38b91b1d70ae
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#ifndef _IONIC_ETHTOOL_H_
+#define _IONIC_ETHTOOL_H_
+
+void ionic_ethtool_set_ops(struct net_device *netdev);
+
+#endif /* _IONIC_ETHTOOL_H_ */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index f52af9cb6264..2bd8ce61c4a0 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -10,6 +10,7 @@
#include "ionic.h"
#include "ionic_bus.h"
#include "ionic_lif.h"
+#include "ionic_ethtool.h"
#include "ionic_debugfs.h"
static void ionic_lif_rx_mode(struct lif *lif, unsigned int rx_mode);
@@ -980,6 +981,7 @@ static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
lif->netdev = netdev;
ionic->master_lif = lif;
netdev->netdev_ops = &ionic_netdev_ops;
+ ionic_ethtool_set_ops(netdev);
netdev->watchdog_timeo = 2 * HZ;
netdev->min_mtu = IONIC_MIN_MTU;
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index 9930b9390c8a..d8589a306aa5 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -111,6 +111,8 @@ struct lif {
u64 last_eid;
unsigned int neqs;
unsigned int nxqs;
+ unsigned int ntxq_descs;
+ unsigned int nrxq_descs;
unsigned int rx_mode;
u64 hw_features;
bool mc_overflow;
@@ -124,6 +126,8 @@ struct lif {
struct rx_filters rx_filters;
struct ionic_deferred deferred;
+ u32 tx_coalesce_usecs;
+ u32 rx_coalesce_usecs;
unsigned long *dbid_inuse;
unsigned int dbid_count;
struct dentry *dentry;
@@ -165,6 +169,10 @@ int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
union lif_identity *lif_ident);
int ionic_lifs_size(struct ionic *ionic);
+int ionic_open(struct net_device *netdev);
+int ionic_stop(struct net_device *netdev);
+int ionic_reset_queues(struct lif *lif);
+
static inline void debug_stats_napi_poll(struct qcq *qcq,
unsigned int work_done)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 13/19] ionic: Add initial ethtool support
2019-07-22 21:40 ` [PATCH v4 net-next 13/19] ionic: Add initial ethtool support Shannon Nelson
@ 2019-07-23 21:35 ` David Miller
2019-07-23 22:50 ` Shannon Nelson
2019-07-25 0:17 ` Saeed Mahameed
` (2 subsequent siblings)
3 siblings, 1 reply; 69+ messages in thread
From: David Miller @ 2019-07-23 21:35 UTC (permalink / raw)
To: snelson; +Cc: netdev
From: Shannon Nelson <snelson@pensando.io>
Date: Mon, 22 Jul 2019 14:40:17 -0700
> +static int ionic_get_link_ksettings(struct net_device *netdev,
> + struct ethtool_link_ksettings *ks)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_dev *idev = &lif->ionic->idev;
> + int copper_seen = 0;
Reverse christmas tree ordering here please.
> +static int ionic_set_link_ksettings(struct net_device *netdev,
> + const struct ethtool_link_ksettings *ks)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic *ionic = lif->ionic;
> + struct ionic_dev *idev = &lif->ionic->idev;
> + u8 fec_type = PORT_FEC_TYPE_NONE;
> + u32 req_rs, req_fc;
> + int err = 0;
Likewise.
> +static void ionic_get_pauseparam(struct net_device *netdev,
> + struct ethtool_pauseparam *pause)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_dev *idev = &lif->ionic->idev;
> + uint8_t pause_type = idev->port_info->config.pause_type;
Likewise.
> +static int ionic_set_pauseparam(struct net_device *netdev,
> + struct ethtool_pauseparam *pause)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic *ionic = lif->ionic;
> + struct ionic_dev *idev = &lif->ionic->idev;
> + u32 requested_pause;
> + int err;
Likewise.
> +static int ionic_get_module_info(struct net_device *netdev,
> + struct ethtool_modinfo *modinfo)
> +
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_dev *idev = &lif->ionic->idev;
> + struct xcvr_status *xcvr;
Likewise.
> +static int ionic_get_module_eeprom(struct net_device *netdev,
> + struct ethtool_eeprom *ee,
> + u8 *data)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_dev *idev = &lif->ionic->idev;
> + struct xcvr_status *xcvr;
> + u32 len;
Likewise.
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 13/19] ionic: Add initial ethtool support
2019-07-23 21:35 ` David Miller
@ 2019-07-23 22:50 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-23 22:50 UTC (permalink / raw)
To: David Miller; +Cc: netdev
On 7/23/19 2:35 PM, David Miller wrote:
> From: Shannon Nelson <snelson@pensando.io>
> Date: Mon, 22 Jul 2019 14:40:17 -0700
>
>> +static int ionic_get_link_ksettings(struct net_device *netdev,
>> + struct ethtool_link_ksettings *ks)
>> +{
>> + struct lif *lif = netdev_priv(netdev);
>> + struct ionic_dev *idev = &lif->ionic->idev;
>> + int copper_seen = 0;
> Reverse christmas tree ordering here please.
Sure. Most of these are because I wanted to do the one assignment
first, from which the others are based. I'll rework these to add the
init lines after the declarations. Same in the other files.
sln
>> +static int ionic_set_link_ksettings(struct net_device *netdev,
>> + const struct ethtool_link_ksettings *ks)
>> +{
>> + struct lif *lif = netdev_priv(netdev);
>> + struct ionic *ionic = lif->ionic;
>> + struct ionic_dev *idev = &lif->ionic->idev;
>> + u8 fec_type = PORT_FEC_TYPE_NONE;
>> + u32 req_rs, req_fc;
>> + int err = 0;
> Likewise.
>> +static void ionic_get_pauseparam(struct net_device *netdev,
>> + struct ethtool_pauseparam *pause)
>> +{
>> + struct lif *lif = netdev_priv(netdev);
>> + struct ionic_dev *idev = &lif->ionic->idev;
>> + uint8_t pause_type = idev->port_info->config.pause_type;
> Likewise.
>
>> +static int ionic_set_pauseparam(struct net_device *netdev,
>> + struct ethtool_pauseparam *pause)
>> +{
>> + struct lif *lif = netdev_priv(netdev);
>> + struct ionic *ionic = lif->ionic;
>> + struct ionic_dev *idev = &lif->ionic->idev;
>> + u32 requested_pause;
>> + int err;
> Likewise.
>> +static int ionic_get_module_info(struct net_device *netdev,
>> + struct ethtool_modinfo *modinfo)
>> +
>> +{
>> + struct lif *lif = netdev_priv(netdev);
>> + struct ionic_dev *idev = &lif->ionic->idev;
>> + struct xcvr_status *xcvr;
> Likewise.
>
>> +static int ionic_get_module_eeprom(struct net_device *netdev,
>> + struct ethtool_eeprom *ee,
>> + u8 *data)
>> +{
>> + struct lif *lif = netdev_priv(netdev);
>> + struct ionic_dev *idev = &lif->ionic->idev;
>> + struct xcvr_status *xcvr;
>> + u32 len;
> Likewise.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 13/19] ionic: Add initial ethtool support
2019-07-22 21:40 ` [PATCH v4 net-next 13/19] ionic: Add initial ethtool support Shannon Nelson
2019-07-23 21:35 ` David Miller
@ 2019-07-25 0:17 ` Saeed Mahameed
2019-07-30 18:57 ` Shannon Nelson
2019-07-25 13:28 ` Andrew Lunn
2019-07-25 13:35 ` Andrew Lunn
3 siblings, 1 reply; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-25 0:17 UTC (permalink / raw)
To: snelson, netdev, davem
On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> Add in the basic ethtool callbacks for device information
> and control.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
> ---
> drivers/net/ethernet/pensando/ionic/Makefile | 2 +-
> .../net/ethernet/pensando/ionic/ionic_dev.h | 3 +
> .../ethernet/pensando/ionic/ionic_ethtool.c | 495
> ++++++++++++++++++
> .../ethernet/pensando/ionic/ionic_ethtool.h | 9 +
> .../net/ethernet/pensando/ionic/ionic_lif.c | 2 +
> .../net/ethernet/pensando/ionic/ionic_lif.h | 8 +
> 6 files changed, 518 insertions(+), 1 deletion(-)
> create mode 100644
> drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> create mode 100644
> drivers/net/ethernet/pensando/ionic/ionic_ethtool.h
>
> diff --git a/drivers/net/ethernet/pensando/ionic/Makefile
> b/drivers/net/ethernet/pensando/ionic/Makefile
> index 7d9cdc5f02a1..9b19bf57a489 100644
> --- a/drivers/net/ethernet/pensando/ionic/Makefile
> +++ b/drivers/net/ethernet/pensando/ionic/Makefile
> @@ -3,5 +3,5 @@
>
> obj-$(CONFIG_IONIC) := ionic.o
>
> -ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o \
> +ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_ethtool.o
> \
> ionic_lif.o ionic_rx_filter.o ionic_debugfs.o
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_dev.h
> b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
> index 523927566925..bacc9c557329 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_dev.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_dev.h
> @@ -12,6 +12,9 @@
>
> #define IONIC_MIN_MTU ETH_MIN_MTU
> #define IONIC_MAX_MTU 9194
> +#define IONIC_MAX_TXRX_DESC 16384
> +#define IONIC_MIN_TXRX_DESC 16
> +#define IONIC_DEF_TXRX_DESC 4096
> #define IONIC_LIFS_MAX 1024
>
> struct ionic_dev_bar {
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> new file mode 100644
> index 000000000000..f7899be547c3
> --- /dev/null
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> @@ -0,0 +1,495 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
> +
> +#include <linux/module.h>
> +#include <linux/netdevice.h>
> +
> +#include "ionic.h"
> +#include "ionic_bus.h"
> +#include "ionic_lif.h"
> +#include "ionic_ethtool.h"
> +
> +static void ionic_get_drvinfo(struct net_device *netdev,
> + struct ethtool_drvinfo *drvinfo)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic *ionic = lif->ionic;
> + struct ionic_dev *idev = &ionic->idev;
> +
> + strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
> + strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo-
> >version));
> + strlcpy(drvinfo->fw_version, idev->dev_info.fw_version,
> + sizeof(drvinfo->fw_version));
> + strlcpy(drvinfo->bus_info, ionic_bus_info(ionic),
> + sizeof(drvinfo->bus_info));
> +}
> +
> +#define DEV_CMD_REG_VERSION 1
> +#define DEV_INFO_REG_COUNT 32
> +#define DEV_CMD_REG_COUNT 32
> +static int ionic_get_regs_len(struct net_device *netdev)
> +{
> + return (DEV_INFO_REG_COUNT + DEV_CMD_REG_COUNT) * sizeof(u32);
> +}
> +
> +static void ionic_get_regs(struct net_device *netdev, struct
> ethtool_regs *regs,
> + void *p)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + unsigned int size;
> +
> + regs->version = DEV_CMD_REG_VERSION;
> +
> + size = DEV_INFO_REG_COUNT * sizeof(u32);
> + memcpy_fromio(p, lif->ionic->idev.dev_info_regs->words, size);
> +
> + size = DEV_CMD_REG_COUNT * sizeof(u32);
> + memcpy_fromio(p, lif->ionic->idev.dev_cmd_regs->words, size);
> +}
> +
> +static int ionic_get_link_ksettings(struct net_device *netdev,
> + struct ethtool_link_ksettings *ks)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_dev *idev = &lif->ionic->idev;
> + int copper_seen = 0;
> +
> + ethtool_link_ksettings_zero_link_mode(ks, supported);
> +
> + /* The port_info data is found in a DMA space that the NIC
> keeps
> + * up-to-date, so there's no need to request the data from the
> + * NIC, we already have it in our memory space.
> + */
> +
> + switch (le16_to_cpu(idev->port_info->status.xcvr.pid)) {
> + /* Copper */
> + case XCVR_PID_QSFP_100G_CR4:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 100000baseCR4_Full
> );
> + copper_seen++;
> + break;
> + case XCVR_PID_QSFP_40GBASE_CR4:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 40000baseCR4_Full)
> ;
> + copper_seen++;
> + break;
> + case XCVR_PID_SFP_25GBASE_CR_S:
> + case XCVR_PID_SFP_25GBASE_CR_L:
> + case XCVR_PID_SFP_25GBASE_CR_N:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 25000baseCR_Full);
> + copper_seen++;
> + break;
> + case XCVR_PID_SFP_10GBASE_AOC:
> + case XCVR_PID_SFP_10GBASE_CU:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 10000baseCR_Full);
> + copper_seen++;
> + break;
> +
> + /* Fibre */
> + case XCVR_PID_QSFP_100G_SR4:
> + case XCVR_PID_QSFP_100G_AOC:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 100000baseSR4_Full
> );
> + break;
> + case XCVR_PID_QSFP_100G_LR4:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 100000baseLR4_ER4_
> Full);
> + break;
> + case XCVR_PID_QSFP_100G_ER4:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 100000baseLR4_ER4_
> Full);
> + break;
> + case XCVR_PID_QSFP_40GBASE_SR4:
> + case XCVR_PID_QSFP_40GBASE_AOC:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 40000baseSR4_Full)
> ;
> + break;
> + case XCVR_PID_QSFP_40GBASE_LR4:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 40000baseLR4_Full)
> ;
> + break;
> + case XCVR_PID_SFP_25GBASE_SR:
> + case XCVR_PID_SFP_25GBASE_AOC:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 25000baseSR_Full);
> + break;
> + case XCVR_PID_SFP_10GBASE_SR:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 10000baseSR_Full);
> + break;
> + case XCVR_PID_SFP_10GBASE_LR:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 10000baseLR_Full);
> + break;
> + case XCVR_PID_SFP_10GBASE_LRM:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 10000baseLRM_Full)
> ;
> + break;
> + case XCVR_PID_SFP_10GBASE_ER:
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> + 10000baseER_Full);
> + break;
> + case XCVR_PID_UNKNOWN:
> + break;
> + default:
> + dev_info(lif->ionic->dev, "unknown xcvr type pid=%d /
> 0x%x\n",
> + idev->port_info->status.xcvr.pid,
> + idev->port_info->status.xcvr.pid);
> + break;
> + }
> + ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
> +
> + if (ionic_is_pf(lif->ionic))
> + ethtool_link_ksettings_add_link_mode(ks, supported,
> Autoneg);
> +
> + bitmap_copy(ks->link_modes.advertising, ks-
> >link_modes.supported,
> + __ETHTOOL_LINK_MODE_MASK_NBITS);
> +
> + ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
> + ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
> + ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
> +
> + if (idev->port_info->config.fec_type == PORT_FEC_TYPE_FC)
> + ethtool_link_ksettings_add_link_mode(ks, advertising,
> FEC_BASER);
> + else if (idev->port_info->config.fec_type == PORT_FEC_TYPE_RS)
> + ethtool_link_ksettings_add_link_mode(ks, advertising,
> FEC_RS);
> + else if (idev->port_info->config.fec_type ==
> PORT_FEC_TYPE_NONE)
> + ethtool_link_ksettings_add_link_mode(ks, advertising,
> FEC_NONE);
> +
> + ethtool_link_ksettings_add_link_mode(ks, supported, Pause);
> + if (idev->port_info->config.pause_type)
> + ethtool_link_ksettings_add_link_mode(ks, advertising,
> Pause);
> +
> + if (idev->port_info->status.xcvr.phy == PHY_TYPE_COPPER ||
> + copper_seen) {
> + ks->base.port = PORT_DA;
> + } else if (idev->port_info->status.xcvr.phy == PHY_TYPE_FIBER)
> {
> + ks->base.port = PORT_FIBRE;
> + } else {
> + ks->base.port = PORT_OTHER;
> + }
> +
> + ks->base.speed = le32_to_cpu(lif->info->status.link_speed);
> +
> + if (idev->port_info->config.an_enable)
> + ks->base.autoneg = AUTONEG_ENABLE;
> +
> + if (le16_to_cpu(lif->info->status.link_status))
> + ks->base.duplex = DUPLEX_FULL;
> + else
> + ks->base.duplex = DUPLEX_UNKNOWN;
> +
> + return 0;
> +}
> +
> +static int ionic_set_link_ksettings(struct net_device *netdev,
> + const struct ethtool_link_ksettings
> *ks)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic *ionic = lif->ionic;
> + struct ionic_dev *idev = &lif->ionic->idev;
> + u8 fec_type = PORT_FEC_TYPE_NONE;
> + u32 req_rs, req_fc;
> + int err = 0;
> +
> + /* set autoneg */
> + if (ks->base.autoneg != idev->port_info->config.an_enable) {
> + mutex_lock(&ionic->dev_cmd_lock);
> + ionic_dev_cmd_port_autoneg(idev, ks->base.autoneg);
> + err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
> + mutex_unlock(&ionic->dev_cmd_lock);
> + if (err)
> + return err;
> + }
> +
> + /* set speed */
> + if (ks->base.speed != le32_to_cpu(idev->port_info-
> >config.speed)) {
> + mutex_lock(&ionic->dev_cmd_lock);
> + ionic_dev_cmd_port_speed(idev, ks->base.speed);
> + err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
> + mutex_unlock(&ionic->dev_cmd_lock);
> + if (err)
> + return err;
> + }
> +
> + /* set FEC */
> + req_rs = ethtool_link_ksettings_test_link_mode(ks, advertising,
> FEC_RS);
> + req_fc = ethtool_link_ksettings_test_link_mode(ks, advertising,
> FEC_BASER);
> + if (req_rs && req_fc) {
> + netdev_info(netdev, "Only select one FEC mode at a
> time\n");
> + return -EINVAL;
> + } else if (req_fc &&
> + idev->port_info->config.fec_type !=
> PORT_FEC_TYPE_FC) {
> + fec_type = PORT_FEC_TYPE_FC;
> + } else if (req_rs &&
> + idev->port_info->config.fec_type !=
> PORT_FEC_TYPE_RS) {
> + fec_type = PORT_FEC_TYPE_RS;
> + } else if (!(req_rs | req_fc) &&
> + idev->port_info->config.fec_type !=
> PORT_FEC_TYPE_NONE) {
> + fec_type = PORT_FEC_TYPE_NONE;
> + }
> +
> + if (fec_type != idev->port_info->config.fec_type) {
> + mutex_lock(&ionic->dev_cmd_lock);
> + ionic_dev_cmd_port_fec(idev, fec_type);
> + err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
> + mutex_unlock(&ionic->dev_cmd_lock);
> + if (err)
> + return err;
> +
> + idev->port_info->config.fec_type = fec_type;
> + }
> +
> + return 0;
> +}
> +
> +static void ionic_get_pauseparam(struct net_device *netdev,
> + struct ethtool_pauseparam *pause)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_dev *idev = &lif->ionic->idev;
> + uint8_t pause_type = idev->port_info->config.pause_type;
> +
> + pause->autoneg = 0;
> +
> + if (pause_type) {
> + pause->rx_pause = pause_type & IONIC_PAUSE_F_RX ? 1 :
> 0;
> + pause->tx_pause = pause_type & IONIC_PAUSE_F_TX ? 1 :
> 0;
> + }
> +}
> +
> +static int ionic_set_pauseparam(struct net_device *netdev,
> + struct ethtool_pauseparam *pause)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic *ionic = lif->ionic;
> + struct ionic_dev *idev = &lif->ionic->idev;
> + u32 requested_pause;
> + int err;
> +
> + if (pause->autoneg == AUTONEG_ENABLE) {
> + netdev_info(netdev, "Please use 'ethtool -s ...' to
> change autoneg\n");
> + return -EOPNOTSUPP;
> + }
> +
> + /* change both at the same time */
> + requested_pause = PORT_PAUSE_TYPE_LINK;
> + if (pause->rx_pause)
> + requested_pause |= IONIC_PAUSE_F_RX;
> + if (pause->tx_pause)
> + requested_pause |= IONIC_PAUSE_F_TX;
> +
> + if (requested_pause == idev->port_info->config.pause_type)
> + return 0;
> +
> + idev->port_info->config.pause_type = requested_pause;
> +
> + mutex_lock(&ionic->dev_cmd_lock);
> + ionic_dev_cmd_port_pause(idev, requested_pause);
> + err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
> + mutex_unlock(&ionic->dev_cmd_lock);
> + if (err)
> + return err;
> +
> + return 0;
> +}
> +
> +static int ionic_get_coalesce(struct net_device *netdev,
> + struct ethtool_coalesce *coalesce)
> +{
> + struct lif *lif = netdev_priv(netdev);
> +
> + coalesce->tx_coalesce_usecs = lif->tx_coalesce_usecs;
> + coalesce->rx_coalesce_usecs = lif->rx_coalesce_usecs;
> +
> + return 0;
> +}
> +
> +static void ionic_get_ringparam(struct net_device *netdev,
> + struct ethtool_ringparam *ring)
> +{
> + struct lif *lif = netdev_priv(netdev);
> +
> + ring->tx_max_pending = IONIC_MAX_TXRX_DESC;
> + ring->tx_pending = lif->ntxq_descs;
> + ring->rx_max_pending = IONIC_MAX_TXRX_DESC;
> + ring->rx_pending = lif->nrxq_descs;
> +}
> +
> +static int ionic_set_ringparam(struct net_device *netdev,
> + struct ethtool_ringparam *ring)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + bool running;
> +
> + if (ring->rx_mini_pending || ring->rx_jumbo_pending) {
> + netdev_info(netdev, "Changing jumbo or mini descriptors
> not supported\n");
> + return -EINVAL;
> + }
> +
> + if (!is_power_of_2(ring->tx_pending) ||
> + !is_power_of_2(ring->rx_pending)) {
> + netdev_info(netdev, "Descriptor count must be a power
> of 2\n");
> + return -EINVAL;
> + }
> +
> + /* if nothing to do return success */
> + if (ring->tx_pending == lif->ntxq_descs &&
> + ring->rx_pending == lif->nrxq_descs)
> + return 0;
> +
> + while (test_and_set_bit(LIF_QUEUE_RESET, lif->state))
> + usleep_range(200, 400);
> +
> + running = test_bit(LIF_UP, lif->state);
> + if (running)
> + ionic_stop(netdev);
> +
> + lif->ntxq_descs = ring->tx_pending;
> + lif->nrxq_descs = ring->rx_pending;
> +
> + if (running)
> + ionic_open(netdev);
> + clear_bit(LIF_QUEUE_RESET, lif->state);
> +
> + return 0;
> +}
> +
> +static void ionic_get_channels(struct net_device *netdev,
> + struct ethtool_channels *ch)
> +{
> + struct lif *lif = netdev_priv(netdev);
> +
> + /* report maximum channels */
> + ch->max_combined = lif->ionic->ntxqs_per_lif;
> +
> + /* report current channels */
> + ch->combined_count = lif->nxqs;
> +}
> +
> +static int ionic_set_channels(struct net_device *netdev,
> + struct ethtool_channels *ch)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + bool running;
> +
> + if (!ch->combined_count || ch->other_count ||
> + ch->rx_count || ch->tx_count)
> + return -EINVAL;
> +
> + if (ch->combined_count == lif->nxqs)
> + return 0;
> +
> + while (test_and_set_bit(LIF_QUEUE_RESET, lif->state))
> + usleep_range(200, 400);
> +
I see this is recurring a lot in the driver, i suggest to have a helper
function (wait_pending_reset_timeout) and make it return with timeout
errno after a reasonable amount of time, especially on user context
flows.
> + running = test_bit(LIF_UP, lif->state);
> + if (running)
> + ionic_stop(netdev);
> +
> + lif->nxqs = ch->combined_count;
> +
> + if (running)
> + ionic_open(netdev);
> + clear_bit(LIF_QUEUE_RESET, lif->state);
> +
> + return 0;
> +}
> +
> +static int ionic_get_module_info(struct net_device *netdev,
> + struct ethtool_modinfo *modinfo)
> +
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_dev *idev = &lif->ionic->idev;
> + struct xcvr_status *xcvr;
> +
> + xcvr = &idev->port_info->status.xcvr;
> +
> + /* report the module data type and length */
> + switch (xcvr->sprom[0]) {
> + case 0x03: /* SFP */
> + modinfo->type = ETH_MODULE_SFF_8079;
> + modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
> + break;
> + case 0x0D: /* QSFP */
> + case 0x11: /* QSFP28 */
> + modinfo->type = ETH_MODULE_SFF_8436;
> + modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
> + break;
> + default:
> + netdev_info(netdev, "unknown xcvr type 0x%02x\n",
> + xcvr->sprom[0]);
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static int ionic_get_module_eeprom(struct net_device *netdev,
> + struct ethtool_eeprom *ee,
> + u8 *data)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_dev *idev = &lif->ionic->idev;
> + struct xcvr_status *xcvr;
> + u32 len;
> +
> + /* The NIC keeps the module prom up-to-date in the DMA space
> + * so we can simply copy the module bytes into the data buffer.
> + */
> + xcvr = &idev->port_info->status.xcvr;
> + len = min_t(u32, sizeof(xcvr->sprom), ee->len);
> + memcpy(data, xcvr->sprom, len);
> +
> + return 0;
> +}
> +
> +static int ionic_nway_reset(struct net_device *netdev)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic *ionic = lif->ionic;
> + int err = 0;
> +
> + /* flap the link to force auto-negotiation */
> +
> + mutex_lock(&ionic->dev_cmd_lock);
> +
> + ionic_dev_cmd_port_state(&ionic->idev, PORT_ADMIN_STATE_DOWN);
> + err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
> +
> + if (!err) {
> + ionic_dev_cmd_port_state(&ionic->idev,
> PORT_ADMIN_STATE_UP);
> + err = ionic_dev_cmd_wait(ionic, devcmd_timeout);
> + }
> +
> + mutex_unlock(&ionic->dev_cmd_lock);
> +
> + return err;
> +}
> +
> +static const struct ethtool_ops ionic_ethtool_ops = {
> + .get_drvinfo = ionic_get_drvinfo,
> + .get_regs_len = ionic_get_regs_len,
> + .get_regs = ionic_get_regs,
> + .get_link = ethtool_op_get_link,
> + .get_link_ksettings = ionic_get_link_ksettings,
> + .get_coalesce = ionic_get_coalesce,
> + .get_ringparam = ionic_get_ringparam,
> + .set_ringparam = ionic_set_ringparam,
> + .get_channels = ionic_get_channels,
> + .set_channels = ionic_set_channels,
> + .get_module_info = ionic_get_module_info,
> + .get_module_eeprom = ionic_get_module_eeprom,
> + .get_pauseparam = ionic_get_pauseparam,
> + .set_pauseparam = ionic_set_pauseparam,
> + .set_link_ksettings = ionic_set_link_ksettings,
> + .nway_reset = ionic_nway_reset,
> +};
> +
> +void ionic_ethtool_set_ops(struct net_device *netdev)
> +{
> + netdev->ethtool_ops = &ionic_ethtool_ops;
> +}
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.h
> b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.h
> new file mode 100644
> index 000000000000..38b91b1d70ae
> --- /dev/null
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.h
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
> +
> +#ifndef _IONIC_ETHTOOL_H_
> +#define _IONIC_ETHTOOL_H_
> +
> +void ionic_ethtool_set_ops(struct net_device *netdev);
> +
> +#endif /* _IONIC_ETHTOOL_H_ */
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> index f52af9cb6264..2bd8ce61c4a0 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> @@ -10,6 +10,7 @@
> #include "ionic.h"
> #include "ionic_bus.h"
> #include "ionic_lif.h"
> +#include "ionic_ethtool.h"
> #include "ionic_debugfs.h"
>
> static void ionic_lif_rx_mode(struct lif *lif, unsigned int
> rx_mode);
> @@ -980,6 +981,7 @@ static struct lif *ionic_lif_alloc(struct ionic
> *ionic, unsigned int index)
> lif->netdev = netdev;
> ionic->master_lif = lif;
> netdev->netdev_ops = &ionic_netdev_ops;
> + ionic_ethtool_set_ops(netdev);
>
> netdev->watchdog_timeo = 2 * HZ;
> netdev->min_mtu = IONIC_MIN_MTU;
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> index 9930b9390c8a..d8589a306aa5 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> @@ -111,6 +111,8 @@ struct lif {
> u64 last_eid;
> unsigned int neqs;
> unsigned int nxqs;
> + unsigned int ntxq_descs;
> + unsigned int nrxq_descs;
> unsigned int rx_mode;
> u64 hw_features;
> bool mc_overflow;
> @@ -124,6 +126,8 @@ struct lif {
>
> struct rx_filters rx_filters;
> struct ionic_deferred deferred;
> + u32 tx_coalesce_usecs;
> + u32 rx_coalesce_usecs;
> unsigned long *dbid_inuse;
> unsigned int dbid_count;
> struct dentry *dentry;
> @@ -165,6 +169,10 @@ int ionic_lif_identify(struct ionic *ionic, u8
> lif_type,
> union lif_identity *lif_ident);
> int ionic_lifs_size(struct ionic *ionic);
>
> +int ionic_open(struct net_device *netdev);
> +int ionic_stop(struct net_device *netdev);
> +int ionic_reset_queues(struct lif *lif);
> +
> static inline void debug_stats_napi_poll(struct qcq *qcq,
> unsigned int work_done)
> {
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 13/19] ionic: Add initial ethtool support
2019-07-25 0:17 ` Saeed Mahameed
@ 2019-07-30 18:57 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-30 18:57 UTC (permalink / raw)
To: Saeed Mahameed, netdev, davem
On 7/24/19 5:17 PM, Saeed Mahameed wrote:
> On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
>> Add in the basic ethtool callbacks for device information
>> and control.
>>
>> Signed-off-by: Shannon Nelson <snelson@pensando.io>
>> ---
>> +
>> + while (test_and_set_bit(LIF_QUEUE_RESET, lif->state))
>> + usleep_range(200, 400);
>> +
> I see this is recurring a lot in the driver, i suggest to have a helper
> function (wait_pending_reset_timeout) and make it return with timeout
> errno after a reasonable amount of time, especially on user context
> flows.
>
>
Sure.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 13/19] ionic: Add initial ethtool support
2019-07-22 21:40 ` [PATCH v4 net-next 13/19] ionic: Add initial ethtool support Shannon Nelson
2019-07-23 21:35 ` David Miller
2019-07-25 0:17 ` Saeed Mahameed
@ 2019-07-25 13:28 ` Andrew Lunn
2019-07-25 13:35 ` Andrew Lunn
3 siblings, 0 replies; 69+ messages in thread
From: Andrew Lunn @ 2019-07-25 13:28 UTC (permalink / raw)
To: Shannon Nelson; +Cc: netdev, davem
On Mon, Jul 22, 2019 at 02:40:17PM -0700, Shannon Nelson wrote:
> +static void ionic_get_pauseparam(struct net_device *netdev,
> + struct ethtool_pauseparam *pause)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_dev *idev = &lif->ionic->idev;
> + uint8_t pause_type = idev->port_info->config.pause_type;
> +
> + pause->autoneg = 0;
> +
> + if (pause_type) {
> + pause->rx_pause = pause_type & IONIC_PAUSE_F_RX ? 1 : 0;
> + pause->tx_pause = pause_type & IONIC_PAUSE_F_TX ? 1 : 0;
> + }
> +}
> +
> +static int ionic_set_pauseparam(struct net_device *netdev,
> + struct ethtool_pauseparam *pause)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic *ionic = lif->ionic;
> + struct ionic_dev *idev = &lif->ionic->idev;
> + u32 requested_pause;
> + int err;
> +
> + if (pause->autoneg == AUTONEG_ENABLE) {
> + netdev_info(netdev, "Please use 'ethtool -s ...' to change autoneg\n");
> + return -EOPNOTSUPP;
> + }
> +
> + /* change both at the same time */
> + requested_pause = PORT_PAUSE_TYPE_LINK;
> + if (pause->rx_pause)
> + requested_pause |= IONIC_PAUSE_F_RX;
> + if (pause->tx_pause)
> + requested_pause |= IONIC_PAUSE_F_TX;
Hi Shannon
This not what i was expecting, and i'm guessing what you have here is
not right.
So you don't support the case of pause->autoneg ==
AUTONEG_ENABLE. That implies that setting pause values directly
configures the MAC. The values from auto-neg are always ignored. Then
why did you set PAUSE in the get ksettings function?
If you always ignore the values from auto-neg, then your info message
also makes no sense.
What really does the firmware do?
Andrew
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 13/19] ionic: Add initial ethtool support
2019-07-22 21:40 ` [PATCH v4 net-next 13/19] ionic: Add initial ethtool support Shannon Nelson
` (2 preceding siblings ...)
2019-07-25 13:28 ` Andrew Lunn
@ 2019-07-25 13:35 ` Andrew Lunn
2019-07-30 21:51 ` Shannon Nelson
3 siblings, 1 reply; 69+ messages in thread
From: Andrew Lunn @ 2019-07-25 13:35 UTC (permalink / raw)
To: Shannon Nelson; +Cc: netdev, davem
> +static int ionic_get_module_eeprom(struct net_device *netdev,
> + struct ethtool_eeprom *ee,
> + u8 *data)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct ionic_dev *idev = &lif->ionic->idev;
> + struct xcvr_status *xcvr;
> + u32 len;
> +
> + /* The NIC keeps the module prom up-to-date in the DMA space
> + * so we can simply copy the module bytes into the data buffer.
> + */
> + xcvr = &idev->port_info->status.xcvr;
> + len = min_t(u32, sizeof(xcvr->sprom), ee->len);
> + memcpy(data, xcvr->sprom, len);
> +
> + return 0;
> +}
Is the firmware doing this DMA update atomically? The diagnostic
values are u16s. Is there any chance we do this memcpy at the same
time the DMA is active and we get a mix of old and new data?
Often in cases like this you do the copy twice and ensure you get the
same values each time. If not, keep repeating the copy until you do
get the same values twice.
Andrew
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 13/19] ionic: Add initial ethtool support
2019-07-25 13:35 ` Andrew Lunn
@ 2019-07-30 21:51 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-30 21:51 UTC (permalink / raw)
To: Andrew Lunn; +Cc: netdev, davem
On 7/25/19 6:35 AM, Andrew Lunn wrote:
>> +static int ionic_get_module_eeprom(struct net_device *netdev,
>> + struct ethtool_eeprom *ee,
>> + u8 *data)
>> +{
>> + struct lif *lif = netdev_priv(netdev);
>> + struct ionic_dev *idev = &lif->ionic->idev;
>> + struct xcvr_status *xcvr;
>> + u32 len;
>> +
>> + /* The NIC keeps the module prom up-to-date in the DMA space
>> + * so we can simply copy the module bytes into the data buffer.
>> + */
>> + xcvr = &idev->port_info->status.xcvr;
>> + len = min_t(u32, sizeof(xcvr->sprom), ee->len);
>> + memcpy(data, xcvr->sprom, len);
>> +
>> + return 0;
>> +}
> Is the firmware doing this DMA update atomically? The diagnostic
> values are u16s. Is there any chance we do this memcpy at the same
> time the DMA is active and we get a mix of old and new data?
>
> Often in cases like this you do the copy twice and ensure you get the
> same values each time. If not, keep repeating the copy until you do
> get the same values twice.
Regardless of how the structs are all aligned and our PCI block does
large writes, I can see how an unoptimized memcpy() that is doing
byte-by-byte copy rather than by words might result in a mangled value.
I think this is the only buffer that may be susceptible to this. Sure,
doing a double copy should work here.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 14/19] ionic: Add Tx and Rx handling
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (12 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 13/19] ionic: Add initial ethtool support Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-23 21:36 ` David Miller
2019-07-25 23:48 ` Saeed Mahameed
2019-07-22 21:40 ` [PATCH v4 net-next 15/19] ionic: Add netdev-event handling Shannon Nelson
` (4 subsequent siblings)
18 siblings, 2 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Add both the Tx and Rx queue setup and handling. The related
stats display comes later. Instead of using the generic napi
routines used by the slow-path commands, the Tx and Rx paths
are simplified and inlined in one file in order to get better
compiler optimizations.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/Makefile | 2 +-
.../net/ethernet/pensando/ionic/ionic_lif.c | 387 ++++++++
.../net/ethernet/pensando/ionic/ionic_lif.h | 52 ++
.../net/ethernet/pensando/ionic/ionic_txrx.c | 879 ++++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_txrx.h | 15 +
5 files changed, 1334 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_txrx.c
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_txrx.h
diff --git a/drivers/net/ethernet/pensando/ionic/Makefile b/drivers/net/ethernet/pensando/ionic/Makefile
index 9b19bf57a489..0e2dc53f08d4 100644
--- a/drivers/net/ethernet/pensando/ionic/Makefile
+++ b/drivers/net/ethernet/pensando/ionic/Makefile
@@ -4,4 +4,4 @@
obj-$(CONFIG_IONIC) := ionic.o
ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_ethtool.o \
- ionic_lif.o ionic_rx_filter.o ionic_debugfs.o
+ ionic_lif.o ionic_rx_filter.o ionic_txrx.o ionic_debugfs.o
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index 2bd8ce61c4a0..40d3b1cb362a 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -10,6 +10,7 @@
#include "ionic.h"
#include "ionic_bus.h"
#include "ionic_lif.h"
+#include "ionic_txrx.h"
#include "ionic_ethtool.h"
#include "ionic_debugfs.h"
@@ -18,6 +19,13 @@ static int ionic_lif_addr_add(struct lif *lif, const u8 *addr);
static int ionic_lif_addr_del(struct lif *lif, const u8 *addr);
static void ionic_link_status_check(struct lif *lif);
+static int ionic_lif_stop(struct lif *lif);
+static int ionic_txrx_alloc(struct lif *lif);
+static int ionic_txrx_init(struct lif *lif);
+static void ionic_qcq_free(struct lif *lif, struct qcq *qcq);
+static int ionic_lif_txqs_init(struct lif *lif);
+static int ionic_lif_rxqs_init(struct lif *lif);
+static void ionic_lif_qcq_deinit(struct lif *lif, struct qcq *qcq);
static int ionic_set_nic_features(struct lif *lif, netdev_features_t features);
static int ionic_notifyq_clean(struct lif *lif, int budget);
@@ -66,12 +74,96 @@ static void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
schedule_work(&def->work);
}
+static int ionic_qcq_enable(struct qcq *qcq)
+{
+ struct queue *q = &qcq->q;
+ struct lif *lif = q->lif;
+ struct device *dev = lif->ionic->dev;
+ struct ionic_dev *idev = &lif->ionic->idev;
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.q_control = {
+ .opcode = CMD_OPCODE_Q_CONTROL,
+ .lif_index = cpu_to_le16(lif->index),
+ .type = q->type,
+ .index = cpu_to_le32(q->index),
+ .oper = IONIC_Q_ENABLE,
+ },
+ };
+
+ dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",
+ ctx.cmd.q_control.index, ctx.cmd.q_control.type);
+
+ if (qcq->flags & QCQ_F_INTR) {
+ irq_set_affinity_hint(qcq->intr.vector,
+ &qcq->intr.affinity_mask);
+ napi_enable(&qcq->napi);
+ ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
+ ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
+ IONIC_INTR_MASK_CLEAR);
+ }
+
+ return ionic_adminq_post_wait(lif, &ctx);
+}
+
+static int ionic_qcq_disable(struct qcq *qcq)
+{
+ struct queue *q = &qcq->q;
+ struct lif *lif = q->lif;
+ struct device *dev = lif->ionic->dev;
+ struct ionic_dev *idev = &lif->ionic->idev;
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.q_control = {
+ .opcode = CMD_OPCODE_Q_CONTROL,
+ .lif_index = cpu_to_le16(lif->index),
+ .type = q->type,
+ .index = cpu_to_le32(q->index),
+ .oper = IONIC_Q_DISABLE,
+ },
+ };
+
+ dev_dbg(dev, "q_disable.index %d q_disable.qtype %d\n",
+ ctx.cmd.q_control.index, ctx.cmd.q_control.type);
+
+ if (qcq->flags & QCQ_F_INTR) {
+ ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
+ IONIC_INTR_MASK_SET);
+ synchronize_irq(qcq->intr.vector);
+ irq_set_affinity_hint(qcq->intr.vector, NULL);
+ napi_disable(&qcq->napi);
+ }
+
+ return ionic_adminq_post_wait(lif, &ctx);
+}
+
int ionic_open(struct net_device *netdev)
{
struct lif *lif = netdev_priv(netdev);
+ unsigned int i;
+ int err;
netif_carrier_off(netdev);
+ err = ionic_txrx_alloc(lif);
+ if (err)
+ return err;
+
+ err = ionic_txrx_init(lif);
+ if (err)
+ goto err_out;
+
+ for (i = 0; i < lif->nxqs; i++) {
+ err = ionic_qcq_enable(lif->txqcqs[i].qcq);
+ if (err)
+ goto err_out;
+
+ ionic_rx_fill(&lif->rxqcqs[i].qcq->q);
+ err = ionic_qcq_enable(lif->rxqcqs[i].qcq);
+ if (err)
+ goto err_out;
+ }
+
set_bit(LIF_UP, lif->state);
ionic_link_status_check(lif);
@@ -79,11 +171,16 @@ int ionic_open(struct net_device *netdev)
netif_tx_wake_all_queues(netdev);
return 0;
+
+err_out:
+ ionic_lif_stop(lif);
+ return err;
}
static int ionic_lif_stop(struct lif *lif)
{
struct net_device *ndev = lif->netdev;
+ unsigned int i;
int err = 0;
if (!test_bit(LIF_UP, lif->state)) {
@@ -100,6 +197,21 @@ static int ionic_lif_stop(struct lif *lif)
netif_tx_disable(ndev);
synchronize_rcu();
+ for (i = 0; i < lif->nxqs; i++) {
+ (void)ionic_qcq_disable(lif->txqcqs[i].qcq);
+ ionic_tx_flush(&lif->txqcqs[i].qcq->cq);
+ ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq);
+ ionic_qcq_free(lif, lif->txqcqs[i].qcq);
+ lif->txqcqs[i].qcq = NULL;
+
+ (void)ionic_qcq_disable(lif->rxqcqs[i].qcq);
+ ionic_rx_flush(&lif->rxqcqs[i].qcq->cq);
+ ionic_lif_qcq_deinit(lif, lif->rxqcqs[i].qcq);
+ ionic_rx_empty(&lif->rxqcqs[i].qcq->q);
+ ionic_qcq_free(lif, lif->rxqcqs[i].qcq);
+ lif->rxqcqs[i].qcq = NULL;
+ }
+
return err;
}
@@ -694,6 +806,7 @@ static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
static const struct net_device_ops ionic_netdev_ops = {
.ndo_open = ionic_open,
.ndo_stop = ionic_stop,
+ .ndo_start_xmit = ionic_start_xmit,
.ndo_get_stats64 = ionic_get_stats64,
.ndo_set_rx_mode = ionic_set_rx_mode,
.ndo_set_features = ionic_set_features,
@@ -909,10 +1022,83 @@ static void ionic_qcq_free(struct lif *lif, struct qcq *qcq)
devm_kfree(dev, qcq);
}
+static int ionic_txrx_alloc(struct lif *lif)
+{
+ unsigned int flags;
+ unsigned int i;
+ int err = 0;
+
+ flags = QCQ_F_TX_STATS | QCQ_F_SG;
+ for (i = 0; i < lif->nxqs; i++) {
+ err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags,
+ lif->ntxq_descs,
+ sizeof(struct txq_desc),
+ sizeof(struct txq_comp),
+ sizeof(struct txq_sg_desc),
+ lif->kern_pid, &lif->txqcqs[i].qcq);
+ if (err)
+ goto err_out_free_txqcqs;
+
+ lif->txqcqs[i].qcq->stats = lif->txqcqs[i].stats;
+ }
+
+ flags = QCQ_F_RX_STATS | QCQ_F_INTR;
+ for (i = 0; i < lif->nxqs; i++) {
+ err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags,
+ lif->nrxq_descs,
+ sizeof(struct rxq_desc),
+ sizeof(struct rxq_comp),
+ 0, lif->kern_pid, &lif->rxqcqs[i].qcq);
+ if (err)
+ goto err_out_free_rxqcqs;
+
+ lif->rxqcqs[i].qcq->stats = lif->rxqcqs[i].stats;
+
+ ionic_link_qcq_interrupts(lif->rxqcqs[i].qcq,
+ lif->txqcqs[i].qcq);
+ }
+
+ return 0;
+
+err_out_free_rxqcqs:
+ for (i = 0; i < lif->nxqs; i++)
+ ionic_qcq_free(lif, lif->rxqcqs[i].qcq);
+err_out_free_txqcqs:
+ for (i = 0; i < lif->nxqs; i++)
+ ionic_qcq_free(lif, lif->txqcqs[i].qcq);
+
+ return err;
+}
+
+static int ionic_txrx_init(struct lif *lif)
+{
+ int err;
+
+ err = ionic_lif_txqs_init(lif);
+ if (err)
+ return err;
+
+ err = ionic_lif_rxqs_init(lif);
+ if (err)
+ goto err_out;
+
+ ionic_set_rx_mode(lif->netdev);
+
+ return 0;
+
+err_out:
+ ionic_stop(lif->netdev);
+
+ return err;
+}
+
static int ionic_qcqs_alloc(struct lif *lif)
{
+ struct device *dev = lif->ionic->dev;
+ unsigned int q_list_size;
unsigned int flags;
int err;
+ int i;
flags = QCQ_F_INTR;
err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
@@ -937,8 +1123,47 @@ static int ionic_qcqs_alloc(struct lif *lif)
ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq);
}
+ q_list_size = sizeof(*lif->txqcqs) * lif->nxqs;
+ err = -ENOMEM;
+ lif->txqcqs = devm_kzalloc(dev, q_list_size, GFP_KERNEL);
+ if (!lif->txqcqs)
+ goto err_out_free_notifyqcq;
+ for (i = 0; i < lif->nxqs; i++) {
+ lif->txqcqs[i].stats = devm_kzalloc(dev, sizeof(struct q_stats),
+ GFP_KERNEL);
+ if (!lif->txqcqs[i].stats)
+ goto err_out_free_tx_stats;
+ }
+
+ lif->rxqcqs = devm_kzalloc(dev, q_list_size, GFP_KERNEL);
+ if (!lif->rxqcqs)
+ goto err_out_free_tx_stats;
+ for (i = 0; i < lif->nxqs; i++) {
+ lif->rxqcqs[i].stats = devm_kzalloc(dev, sizeof(struct q_stats),
+ GFP_KERNEL);
+ if (!lif->rxqcqs[i].stats)
+ goto err_out_free_rx_stats;
+ }
+
return 0;
+err_out_free_rx_stats:
+ for (i = 0; i < lif->nxqs; i++)
+ if (lif->rxqcqs[i].stats)
+ devm_kfree(dev, lif->rxqcqs[i].stats);
+ devm_kfree(dev, lif->rxqcqs);
+ lif->rxqcqs = NULL;
+err_out_free_tx_stats:
+ for (i = 0; i < lif->nxqs; i++)
+ if (lif->txqcqs[i].stats)
+ devm_kfree(dev, lif->txqcqs[i].stats);
+ devm_kfree(dev, lif->txqcqs);
+ lif->txqcqs = NULL;
+err_out_free_notifyqcq:
+ if (lif->notifyqcq) {
+ ionic_qcq_free(lif, lif->notifyqcq);
+ lif->notifyqcq = NULL;
+ }
err_out_free_adminqcq:
ionic_qcq_free(lif, lif->adminqcq);
lif->adminqcq = NULL;
@@ -948,6 +1173,9 @@ static int ionic_qcqs_alloc(struct lif *lif)
static void ionic_qcqs_free(struct lif *lif)
{
+ struct device *dev = lif->ionic->dev;
+ unsigned int i;
+
if (lif->notifyqcq) {
ionic_qcq_free(lif, lif->notifyqcq);
lif->notifyqcq = NULL;
@@ -957,6 +1185,20 @@ static void ionic_qcqs_free(struct lif *lif)
ionic_qcq_free(lif, lif->adminqcq);
lif->adminqcq = NULL;
}
+
+ for (i = 0; i < lif->nxqs; i++)
+ if (lif->rxqcqs[i].stats)
+ devm_kfree(dev, lif->rxqcqs[i].stats);
+
+ devm_kfree(dev, lif->rxqcqs);
+ lif->rxqcqs = NULL;
+
+ for (i = 0; i < lif->nxqs; i++)
+ if (lif->txqcqs[i].stats)
+ devm_kfree(dev, lif->txqcqs[i].stats);
+
+ devm_kfree(dev, lif->txqcqs);
+ lif->txqcqs = NULL;
}
static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
@@ -992,6 +1234,8 @@ static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
lif->ionic = ionic;
lif->index = index;
+ lif->ntxq_descs = IONIC_DEF_TXRX_DESC;
+ lif->nrxq_descs = IONIC_DEF_TXRX_DESC;
snprintf(lif->name, sizeof(lif->name), "lif%u", index);
@@ -1432,6 +1676,147 @@ static int ionic_init_nic_features(struct lif *lif)
return 0;
}
+static int ionic_lif_txq_init(struct lif *lif, struct qcq *qcq)
+{
+ struct device *dev = lif->ionic->dev;
+ struct queue *q = &qcq->q;
+ struct cq *cq = &qcq->cq;
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.q_init = {
+ .opcode = CMD_OPCODE_Q_INIT,
+ .lif_index = cpu_to_le16(lif->index),
+ .type = q->type,
+ .index = cpu_to_le32(q->index),
+ .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
+ IONIC_QINIT_F_SG),
+ .intr_index = cpu_to_le16(lif->rxqcqs[q->index].qcq->intr.index),
+ .pid = cpu_to_le16(q->pid),
+ .ring_size = ilog2(q->num_descs),
+ .ring_base = cpu_to_le64(q->base_pa),
+ .cq_ring_base = cpu_to_le64(cq->base_pa),
+ .sg_ring_base = cpu_to_le64(q->sg_base_pa),
+ },
+ };
+ int err;
+
+ dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid);
+ dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index);
+ dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
+ dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
+
+ err = ionic_adminq_post_wait(lif, &ctx);
+ if (err)
+ return err;
+
+ q->hw_type = ctx.comp.q_init.hw_type;
+ q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
+ q->dbval = IONIC_DBELL_QID(q->hw_index);
+
+ dev_dbg(dev, "txq->hw_type %d\n", q->hw_type);
+ dev_dbg(dev, "txq->hw_index %d\n", q->hw_index);
+
+ qcq->flags |= QCQ_F_INITED;
+
+ ionic_debugfs_add_qcq(lif, qcq);
+
+ return 0;
+}
+
+static int ionic_lif_txqs_init(struct lif *lif)
+{
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < lif->nxqs; i++) {
+ err = ionic_lif_txq_init(lif, lif->txqcqs[i].qcq);
+ if (err)
+ goto err_out;
+ }
+
+ return 0;
+
+err_out:
+ for (; i > 0; i--)
+ ionic_lif_qcq_deinit(lif, lif->txqcqs[i-1].qcq);
+
+ return err;
+}
+
+static int ionic_lif_rxq_init(struct lif *lif, struct qcq *qcq)
+{
+ struct device *dev = lif->ionic->dev;
+ struct queue *q = &qcq->q;
+ struct cq *cq = &qcq->cq;
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.q_init = {
+ .opcode = CMD_OPCODE_Q_INIT,
+ .lif_index = cpu_to_le16(lif->index),
+ .type = q->type,
+ .index = cpu_to_le32(q->index),
+ .flags = cpu_to_le16(IONIC_QINIT_F_IRQ),
+ .intr_index = cpu_to_le16(cq->bound_intr->index),
+ .pid = cpu_to_le16(q->pid),
+ .ring_size = ilog2(q->num_descs),
+ .ring_base = cpu_to_le64(q->base_pa),
+ .cq_ring_base = cpu_to_le64(cq->base_pa),
+ },
+ };
+ int err;
+
+ dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid);
+ dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index);
+ dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
+ dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
+
+ err = ionic_adminq_post_wait(lif, &ctx);
+ if (err)
+ return err;
+
+ q->hw_type = ctx.comp.q_init.hw_type;
+ q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
+ q->dbval = IONIC_DBELL_QID(q->hw_index);
+
+ dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type);
+ dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index);
+
+ netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi,
+ NAPI_POLL_WEIGHT);
+
+ err = ionic_request_irq(lif, qcq);
+ if (err) {
+ netif_napi_del(&qcq->napi);
+ return err;
+ }
+
+ qcq->flags |= QCQ_F_INITED;
+
+ ionic_debugfs_add_qcq(lif, qcq);
+
+ return 0;
+}
+
+static int ionic_lif_rxqs_init(struct lif *lif)
+{
+ unsigned int i;
+ int err;
+
+ for (i = 0; i < lif->nxqs; i++) {
+ err = ionic_lif_rxq_init(lif, lif->rxqcqs[i].qcq);
+ if (err)
+ goto err_out;
+ }
+
+ return 0;
+
+err_out:
+ for (; i > 0; i--)
+ ionic_lif_qcq_deinit(lif, lif->rxqcqs[i-1].qcq);
+
+ return err;
+}
+
static int ionic_station_set(struct lif *lif)
{
struct net_device *netdev = lif->netdev;
@@ -1531,6 +1916,8 @@ static int ionic_lif_init(struct lif *lif)
if (err)
goto err_out_notifyq_deinit;
+ lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT;
+
set_bit(LIF_INITED, lif->state);
ionic_link_status_check(lif);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index d8589a306aa5..88d5bf8f58a1 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -14,20 +14,38 @@
#define MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1)
#define GET_SG_CNTR_IDX(num_sg_elems) (num_sg_elems)
#define MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1)
+#define IONIC_RX_COPYBREAK_DEFAULT 256
struct tx_stats {
+ u64 dma_map_err;
u64 pkts;
u64 bytes;
+ u64 clean;
+ u64 linearize;
+ u64 no_csum;
+ u64 csum;
+ u64 crc32_csum;
+ u64 tso;
+ u64 frags;
+ u64 sg_cntr[MAX_NUM_SG_CNTR];
};
struct rx_stats {
+ u64 dma_map_err;
+ u64 alloc_err;
u64 pkts;
u64 bytes;
+ u64 csum_none;
+ u64 csum_complete;
+ u64 csum_error;
+ u64 buffers_posted;
};
#define QCQ_F_INITED BIT(0)
#define QCQ_F_SG BIT(1)
#define QCQ_F_INTR BIT(2)
+#define QCQ_F_TX_STATS BIT(3)
+#define QCQ_F_RX_STATS BIT(4)
#define QCQ_F_NOTIFYQ BIT(5)
struct napi_stats {
@@ -56,7 +74,14 @@ struct qcq {
struct dentry *dentry;
};
+struct qcqst {
+ struct qcq *qcq;
+ struct q_stats *stats;
+};
+
#define q_to_qcq(q) container_of(q, struct qcq, q)
+#define q_to_tx_stats(q) (&q_to_qcq(q)->stats->tx)
+#define q_to_rx_stats(q) (&q_to_qcq(q)->stats->rx)
#define napi_to_qcq(napi) container_of(napi, struct qcq, napi)
#define napi_to_cq(napi) (&napi_to_qcq(napi)->cq)
@@ -108,11 +133,14 @@ struct lif {
spinlock_t adminq_lock; /* lock for AdminQ operations */
struct qcq *adminqcq;
struct qcq *notifyqcq;
+ struct qcqst *txqcqs;
+ struct qcqst *rxqcqs;
u64 last_eid;
unsigned int neqs;
unsigned int nxqs;
unsigned int ntxq_descs;
unsigned int nrxq_descs;
+ u32 rx_copybreak;
unsigned int rx_mode;
u64 hw_features;
bool mc_overflow;
@@ -134,6 +162,11 @@ struct lif {
u32 flags;
};
+#define lif_to_txqcq(lif, i) ((lif)->txqcqs[i].qcq)
+#define lif_to_rxqcq(lif, i) ((lif)->rxqcqs[i].qcq)
+#define lif_to_txq(lif, i) (&lif_to_txqcq((lif), i)->q)
+#define lif_to_rxq(lif, i) (&lif_to_txqcq((lif), i)->q)
+
static inline bool ionic_is_pf(struct ionic *ionic)
{
return ionic->pdev &&
@@ -173,6 +206,22 @@ int ionic_open(struct net_device *netdev);
int ionic_stop(struct net_device *netdev);
int ionic_reset_queues(struct lif *lif);
+static inline void debug_stats_txq_post(struct qcq *qcq,
+ struct txq_desc *desc, bool dbell)
+{
+ u8 num_sg_elems = ((le64_to_cpu(desc->cmd) >> IONIC_TXQ_DESC_NSGE_SHIFT)
+ & IONIC_TXQ_DESC_NSGE_MASK);
+ u8 sg_cntr_idx;
+
+ qcq->q.dbell_count += dbell;
+
+ sg_cntr_idx = GET_SG_CNTR_IDX(num_sg_elems);
+ if (sg_cntr_idx > (MAX_NUM_SG_CNTR - 1))
+ sg_cntr_idx = MAX_NUM_SG_CNTR - 1;
+
+ qcq->stats->tx.sg_cntr[sg_cntr_idx]++;
+}
+
static inline void debug_stats_napi_poll(struct qcq *qcq,
unsigned int work_done)
{
@@ -188,7 +237,10 @@ static inline void debug_stats_napi_poll(struct qcq *qcq,
}
#define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++)
+#define DEBUG_STATS_RX_BUFF_CNT(qcq) ((qcq)->stats->rx.buffers_posted++)
#define DEBUG_STATS_INTR_REARM(intr) ((intr)->rearm_count++)
+#define DEBUG_STATS_TXQ_POST(qcq, txdesc, dbell) \
+ debug_stats_txq_post(qcq, txdesc, dbell)
#define DEBUG_STATS_NAPI_POLL(qcq, work_done) \
debug_stats_napi_poll(qcq, work_done)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_txrx.c b/drivers/net/ethernet/pensando/ionic/ionic_txrx.c
new file mode 100644
index 000000000000..7787e7dd5504
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_txrx.c
@@ -0,0 +1,879 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/if_vlan.h>
+#include <net/ip6_checksum.h>
+
+#include "ionic.h"
+#include "ionic_lif.h"
+#include "ionic_txrx.h"
+
+static void ionic_tx_clean(struct queue *q, struct desc_info *desc_info,
+ struct cq_info *cq_info, void *cb_arg);
+static void ionic_rx_clean(struct queue *q, struct desc_info *desc_info,
+ struct cq_info *cq_info, void *cb_arg);
+
+static inline void ionic_txq_post(struct queue *q, bool ring_dbell,
+ desc_cb cb_func, void *cb_arg)
+{
+ DEBUG_STATS_TXQ_POST(q_to_qcq(q), q->head->desc, ring_dbell);
+
+ ionic_q_post(q, ring_dbell, cb_func, cb_arg);
+}
+
+static inline void ionic_rxq_post(struct queue *q, bool ring_dbell,
+ desc_cb cb_func, void *cb_arg)
+{
+ ionic_q_post(q, ring_dbell, cb_func, cb_arg);
+
+ DEBUG_STATS_RX_BUFF_CNT(q_to_qcq(q));
+}
+
+static void ionic_rx_recycle(struct queue *q, struct desc_info *desc_info,
+ struct sk_buff *skb)
+{
+ struct rxq_desc *old = desc_info->desc;
+ struct rxq_desc *new = q->head->desc;
+
+ new->addr = old->addr;
+ new->len = old->len;
+
+ ionic_rxq_post(q, true, ionic_rx_clean, skb);
+}
+
+static bool ionic_rx_copybreak(struct queue *q, struct desc_info *desc_info,
+ struct cq_info *cq_info, struct sk_buff **skb)
+{
+ struct net_device *netdev = q->lif->netdev;
+ struct device *dev = q->lif->ionic->dev;
+ struct rxq_desc *desc = desc_info->desc;
+ struct rxq_comp *comp = cq_info->cq_desc;
+ struct sk_buff *new_skb;
+ u16 clen, dlen;
+
+ clen = le16_to_cpu(comp->len);
+ dlen = le16_to_cpu(desc->len);
+ if (clen > q->lif->rx_copybreak) {
+ dma_unmap_single(dev, (dma_addr_t)le64_to_cpu(desc->addr),
+ dlen, DMA_FROM_DEVICE);
+ return false;
+ }
+
+ new_skb = netdev_alloc_skb_ip_align(netdev, clen);
+ if (!new_skb) {
+ dma_unmap_single(dev, (dma_addr_t)le64_to_cpu(desc->addr),
+ dlen, DMA_FROM_DEVICE);
+ return false;
+ }
+
+ dma_sync_single_for_cpu(dev, (dma_addr_t)le64_to_cpu(desc->addr),
+ clen, DMA_FROM_DEVICE);
+
+ memcpy(new_skb->data, (*skb)->data, clen);
+
+ ionic_rx_recycle(q, desc_info, *skb);
+ *skb = new_skb;
+
+ return true;
+}
+
+static void ionic_rx_clean(struct queue *q, struct desc_info *desc_info,
+ struct cq_info *cq_info, void *cb_arg)
+{
+ struct rxq_comp *comp = cq_info->cq_desc;
+ struct sk_buff *skb = cb_arg;
+ struct qcq *qcq = q_to_qcq(q);
+ struct net_device *netdev;
+ struct rx_stats *stats;
+
+ stats = q_to_rx_stats(q);
+ netdev = q->lif->netdev;
+
+ if (comp->status) {
+ ionic_rx_recycle(q, desc_info, skb);
+ return;
+ }
+
+ if (unlikely(test_bit(LIF_QUEUE_RESET, q->lif->state))) {
+ /* no packet processing while resetting */
+ ionic_rx_recycle(q, desc_info, skb);
+ return;
+ }
+
+ stats->pkts++;
+ stats->bytes += le16_to_cpu(comp->len);
+
+ ionic_rx_copybreak(q, desc_info, cq_info, &skb);
+
+ skb_put(skb, le16_to_cpu(comp->len));
+ skb->protocol = eth_type_trans(skb, netdev);
+
+ skb_record_rx_queue(skb, q->index);
+
+ if (netdev->features & NETIF_F_RXHASH) {
+ switch (comp->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) {
+ case PKT_TYPE_IPV4:
+ case PKT_TYPE_IPV6:
+ skb_set_hash(skb, le32_to_cpu(comp->rss_hash),
+ PKT_HASH_TYPE_L3);
+ break;
+ case PKT_TYPE_IPV4_TCP:
+ case PKT_TYPE_IPV6_TCP:
+ case PKT_TYPE_IPV4_UDP:
+ case PKT_TYPE_IPV6_UDP:
+ skb_set_hash(skb, le32_to_cpu(comp->rss_hash),
+ PKT_HASH_TYPE_L4);
+ break;
+ }
+ }
+
+ if (netdev->features & NETIF_F_RXCSUM) {
+ if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) {
+ skb->ip_summed = CHECKSUM_COMPLETE;
+ skb->csum = (__wsum)le16_to_cpu(comp->csum);
+ stats->csum_complete++;
+ }
+ } else {
+ stats->csum_none++;
+ }
+
+ if ((comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_BAD) ||
+ (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_BAD) ||
+ (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD))
+ stats->csum_error++;
+
+ if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
+ if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN)
+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
+ le16_to_cpu(comp->vlan_tci));
+ }
+
+ napi_gro_receive(&qcq->napi, skb);
+}
+
+static bool ionic_rx_service(struct cq *cq, struct cq_info *cq_info)
+{
+ struct rxq_comp *comp = cq_info->cq_desc;
+ struct queue *q = cq->bound_q;
+ struct desc_info *desc_info;
+
+ if (!color_match(comp->pkt_type_color, cq->done_color))
+ return false;
+
+ /* check for empty queue */
+ if (q->tail->index == q->head->index)
+ return false;
+
+ desc_info = q->tail;
+ if (desc_info->index != le16_to_cpu(comp->comp_index))
+ return false;
+
+ q->tail = desc_info->next;
+
+ /* clean the related q entry, only one per qc completion */
+ ionic_rx_clean(q, desc_info, cq_info, desc_info->cb_arg);
+
+ desc_info->cb = NULL;
+ desc_info->cb_arg = NULL;
+
+ return true;
+}
+
+static u32 ionic_rx_walk_cq(struct cq *rxcq, u32 limit)
+{
+ u32 work_done = 0;
+
+ while (ionic_rx_service(rxcq, rxcq->tail)) {
+ if (rxcq->tail->last)
+ rxcq->done_color = !rxcq->done_color;
+ rxcq->tail = rxcq->tail->next;
+ DEBUG_STATS_CQE_CNT(rxcq);
+
+ if (++work_done >= limit)
+ break;
+ }
+
+ return work_done;
+}
+
+void ionic_rx_flush(struct cq *cq)
+{
+ struct ionic_dev *idev = &cq->lif->ionic->idev;
+ u32 work_done;
+
+ work_done = ionic_rx_walk_cq(cq, cq->num_descs);
+
+ if (work_done)
+ ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index,
+ work_done, IONIC_INTR_CRED_RESET_COALESCE);
+}
+
+void ionic_tx_flush(struct cq *cq)
+{
+ struct ionic_dev *idev = &cq->lif->ionic->idev;
+ struct txq_comp *comp = cq->tail->cq_desc;
+ struct queue *q = cq->bound_q;
+ struct desc_info *desc_info;
+ unsigned int work_done = 0;
+
+ /* walk the completed cq entries */
+ while (work_done < cq->num_descs &&
+ color_match(comp->color, cq->done_color)) {
+
+ /* clean the related q entries, there could be
+ * several q entries completed for each cq completion
+ */
+ do {
+ desc_info = q->tail;
+ q->tail = desc_info->next;
+ ionic_tx_clean(q, desc_info, cq->tail,
+ desc_info->cb_arg);
+ desc_info->cb = NULL;
+ desc_info->cb_arg = NULL;
+ } while (desc_info->index != le16_to_cpu(comp->comp_index));
+
+ if (cq->tail->last)
+ cq->done_color = !cq->done_color;
+
+ cq->tail = cq->tail->next;
+ comp = cq->tail->cq_desc;
+ DEBUG_STATS_CQE_CNT(cq);
+
+ work_done++;
+ }
+
+ if (work_done)
+ ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index,
+ work_done, 0);
+}
+
+static struct sk_buff *ionic_rx_skb_alloc(struct queue *q, unsigned int len,
+ dma_addr_t *dma_addr)
+{
+ struct lif *lif = q->lif;
+ struct net_device *netdev = lif->netdev;
+ struct device *dev = lif->ionic->dev;
+ struct rx_stats *stats;
+ struct sk_buff *skb;
+
+ stats = q_to_rx_stats(q);
+ skb = netdev_alloc_skb_ip_align(netdev, len);
+ if (!skb) {
+ net_warn_ratelimited("%s: SKB alloc failed on %s!\n",
+ netdev->name, q->name);
+ stats->alloc_err++;
+ return NULL;
+ }
+
+ *dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
+ if (dma_mapping_error(dev, *dma_addr)) {
+ dev_kfree_skb(skb);
+ net_warn_ratelimited("%s: DMA single map failed on %s!\n",
+ netdev->name, q->name);
+ stats->dma_map_err++;
+ return NULL;
+ }
+
+ return skb;
+}
+
+static void ionic_rx_skb_free(struct queue *q, struct sk_buff *skb,
+ unsigned int len, dma_addr_t dma_addr)
+{
+ struct device *dev = q->lif->ionic->dev;
+
+ dma_unmap_single(dev, dma_addr, len, DMA_FROM_DEVICE);
+ dev_kfree_skb(skb);
+}
+
+#define RX_RING_DOORBELL_STRIDE ((1 << 2) - 1)
+
+void ionic_rx_fill(struct queue *q)
+{
+ struct net_device *netdev = q->lif->netdev;
+ struct rxq_desc *desc;
+ struct sk_buff *skb;
+ dma_addr_t dma_addr;
+ bool ring_doorbell;
+ unsigned int len;
+ unsigned int i;
+
+ len = netdev->mtu + ETH_HLEN;
+
+ for (i = ionic_q_space_avail(q); i; i--) {
+ skb = ionic_rx_skb_alloc(q, len, &dma_addr);
+ if (!skb)
+ return;
+
+ desc = q->head->desc;
+ desc->addr = cpu_to_le64(dma_addr);
+ desc->len = cpu_to_le16(len);
+ desc->opcode = RXQ_DESC_OPCODE_SIMPLE;
+
+ ring_doorbell = ((q->head->index + 1) &
+ RX_RING_DOORBELL_STRIDE) == 0;
+
+ ionic_rxq_post(q, ring_doorbell, ionic_rx_clean, skb);
+ }
+}
+
+static void ionic_rx_fill_cb(void *arg)
+{
+ ionic_rx_fill(arg);
+}
+
+void ionic_rx_empty(struct queue *q)
+{
+ struct desc_info *cur = q->tail;
+ struct rxq_desc *desc;
+
+ while (cur != q->head) {
+ desc = cur->desc;
+
+ ionic_rx_skb_free(q, cur->cb_arg, le16_to_cpu(desc->len),
+ le64_to_cpu(desc->addr));
+ cur->cb_arg = NULL;
+
+ cur = cur->next;
+ }
+}
+
+int ionic_rx_napi(struct napi_struct *napi, int budget)
+{
+ struct qcq *qcq = napi_to_qcq(napi);
+ struct cq *rxcq = napi_to_cq(napi);
+ unsigned int qi = rxcq->bound_q->index;
+ struct lif *lif = rxcq->bound_q->lif;
+ struct ionic_dev *idev = &lif->ionic->idev;
+ struct cq *txcq = &lif->txqcqs[qi].qcq->cq;
+ u32 work_done = 0;
+ u32 flags = 0;
+
+ ionic_tx_flush(txcq);
+
+ work_done = ionic_rx_walk_cq(rxcq, budget);
+
+ if (work_done)
+ ionic_rx_fill_cb(rxcq->bound_q);
+
+ if (work_done < budget && napi_complete_done(napi, work_done)) {
+ flags |= IONIC_INTR_CRED_UNMASK;
+ DEBUG_STATS_INTR_REARM(rxcq->bound_intr);
+ }
+
+ if (work_done || flags) {
+ flags |= IONIC_INTR_CRED_RESET_COALESCE;
+ ionic_intr_credits(idev->intr_ctrl, rxcq->bound_intr->index,
+ work_done, flags);
+ }
+
+ DEBUG_STATS_NAPI_POLL(qcq, work_done);
+
+ return work_done;
+}
+
+static dma_addr_t ionic_tx_map_single(struct queue *q, void *data, size_t len)
+{
+ struct tx_stats *stats = q_to_tx_stats(q);
+ struct device *dev = q->lif->ionic->dev;
+ dma_addr_t dma_addr;
+
+ dma_addr = dma_map_single(dev, data, len, DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, dma_addr)) {
+ net_warn_ratelimited("%s: DMA single map failed on %s!\n",
+ q->lif->netdev->name, q->name);
+ stats->dma_map_err++;
+ return 0;
+ }
+ return dma_addr;
+}
+
+static dma_addr_t ionic_tx_map_frag(struct queue *q, const skb_frag_t *frag,
+ size_t offset, size_t len)
+{
+ struct tx_stats *stats = q_to_tx_stats(q);
+ struct device *dev = q->lif->ionic->dev;
+ dma_addr_t dma_addr;
+
+ dma_addr = skb_frag_dma_map(dev, frag, offset, len, DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, dma_addr)) {
+ net_warn_ratelimited("%s: DMA frag map failed on %s!\n",
+ q->lif->netdev->name, q->name);
+ stats->dma_map_err++;
+ return 0;
+ }
+ return dma_addr;
+}
+
+static void ionic_tx_clean(struct queue *q, struct desc_info *desc_info,
+ struct cq_info *cq_info, void *cb_arg)
+{
+ struct txq_sg_desc *sg_desc = desc_info->sg_desc;
+ struct txq_sg_elem *elem = sg_desc->elems;
+ struct tx_stats *stats = q_to_tx_stats(q);
+ struct txq_desc *desc = desc_info->desc;
+ struct device *dev = q->lif->ionic->dev;
+ struct sk_buff *skb = cb_arg;
+ u8 opcode, flags, nsge;
+ u16 queue_index;
+ unsigned int i;
+ u64 addr;
+
+ decode_txq_desc_cmd(le64_to_cpu(desc->cmd),
+ &opcode, &flags, &nsge, &addr);
+
+ dma_unmap_page(dev, (dma_addr_t)addr,
+ le16_to_cpu(desc->len), DMA_TO_DEVICE);
+ for (i = 0; i < nsge; i++, elem++)
+ dma_unmap_page(dev, (dma_addr_t)le64_to_cpu(elem->addr),
+ le16_to_cpu(elem->len), DMA_TO_DEVICE);
+
+ if (skb) {
+ queue_index = skb_get_queue_mapping(skb);
+ if (unlikely(__netif_subqueue_stopped(q->lif->netdev,
+ queue_index))) {
+ netif_wake_subqueue(q->lif->netdev, queue_index);
+ q->wake++;
+ }
+ dev_kfree_skb_any(skb);
+ stats->clean++;
+ }
+}
+
+static void ionic_tx_tcp_inner_pseudo_csum(struct sk_buff *skb)
+{
+ skb_cow_head(skb, 0);
+
+ if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
+ inner_ip_hdr(skb)->check = 0;
+ inner_tcp_hdr(skb)->check =
+ ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr,
+ inner_ip_hdr(skb)->daddr,
+ 0, IPPROTO_TCP, 0);
+ } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
+ inner_tcp_hdr(skb)->check =
+ ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr,
+ &inner_ipv6_hdr(skb)->daddr,
+ 0, IPPROTO_TCP, 0);
+ }
+}
+
+static void ionic_tx_tcp_pseudo_csum(struct sk_buff *skb)
+{
+ skb_cow_head(skb, 0);
+
+ if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
+ ip_hdr(skb)->check = 0;
+ tcp_hdr(skb)->check =
+ ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
+ ip_hdr(skb)->daddr,
+ 0, IPPROTO_TCP, 0);
+ } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
+ tcp_hdr(skb)->check =
+ ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
+ &ipv6_hdr(skb)->daddr,
+ 0, IPPROTO_TCP, 0);
+ }
+}
+
+static void ionic_tx_tso_post(struct queue *q, struct txq_desc *desc,
+ struct sk_buff *skb,
+ dma_addr_t addr, u8 nsge, u16 len,
+ unsigned int hdrlen, unsigned int mss,
+ bool outer_csum,
+ u16 vlan_tci, bool has_vlan,
+ bool start, bool done)
+{
+ u8 flags = 0;
+ u64 cmd;
+
+ flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
+ flags |= outer_csum ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
+ flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
+ flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
+
+ cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO, flags, nsge, addr);
+ desc->cmd = cpu_to_le64(cmd);
+ desc->len = cpu_to_le16(len);
+ desc->vlan_tci = cpu_to_le16(vlan_tci);
+ desc->hdr_len = cpu_to_le16(hdrlen);
+ desc->mss = cpu_to_le16(mss);
+
+ if (done) {
+ skb_tx_timestamp(skb);
+ ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb);
+ } else {
+ ionic_txq_post(q, false, ionic_tx_clean, NULL);
+ }
+}
+
+static struct txq_desc *ionic_tx_tso_next(struct queue *q,
+ struct txq_sg_elem **elem)
+{
+ struct txq_sg_desc *sg_desc = q->head->sg_desc;
+ struct txq_desc *desc = q->head->desc;
+
+ *elem = sg_desc->elems;
+ return desc;
+}
+
+static int ionic_tx_tso(struct queue *q, struct sk_buff *skb)
+{
+ struct tx_stats *stats = q_to_tx_stats(q);
+ struct desc_info *abort = q->head;
+ struct desc_info *rewind = abort;
+ unsigned int frag_left = 0;
+ struct txq_sg_elem *elem;
+ unsigned int offset = 0;
+ unsigned int len_left;
+ struct txq_desc *desc;
+ dma_addr_t desc_addr;
+ unsigned int hdrlen;
+ unsigned int nfrags;
+ unsigned int seglen;
+ u64 total_bytes = 0;
+ u64 total_pkts = 0;
+ unsigned int left;
+ unsigned int len;
+ unsigned int mss;
+ skb_frag_t *frag;
+ bool start, done;
+ bool outer_csum;
+ bool has_vlan;
+ u16 desc_len;
+ u8 desc_nsge;
+ u16 vlan_tci;
+ bool encap;
+
+ mss = skb_shinfo(skb)->gso_size;
+ nfrags = skb_shinfo(skb)->nr_frags;
+ len_left = skb->len - skb_headlen(skb);
+ outer_csum = (skb_shinfo(skb)->gso_type & SKB_GSO_GRE_CSUM) ||
+ (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM);
+ has_vlan = !!skb_vlan_tag_present(skb);
+ vlan_tci = skb_vlan_tag_get(skb);
+ encap = skb->encapsulation;
+
+ /* Preload inner-most TCP csum field with IP pseudo hdr
+ * calculated with IP length set to zero. HW will later
+ * add in length to each TCP segment resulting from the TSO.
+ */
+
+ if (encap)
+ ionic_tx_tcp_inner_pseudo_csum(skb);
+ else
+ ionic_tx_tcp_pseudo_csum(skb);
+
+ if (encap)
+ hdrlen = skb_inner_transport_header(skb) - skb->data +
+ inner_tcp_hdrlen(skb);
+ else
+ hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
+
+ seglen = hdrlen + mss;
+ left = skb_headlen(skb);
+
+ desc = ionic_tx_tso_next(q, &elem);
+ start = true;
+
+ /* Chop skb->data up into desc segments */
+
+ while (left > 0) {
+ len = min(seglen, left);
+ frag_left = seglen - len;
+ desc_addr = ionic_tx_map_single(q, skb->data + offset, len);
+ if (!desc_addr)
+ goto err_out_abort;
+ desc_len = len;
+ desc_nsge = 0;
+ left -= len;
+ offset += len;
+ if (nfrags > 0 && frag_left > 0)
+ continue;
+ done = (nfrags == 0 && left == 0);
+ ionic_tx_tso_post(q, desc, skb,
+ desc_addr, desc_nsge, desc_len,
+ hdrlen, mss,
+ outer_csum,
+ vlan_tci, has_vlan,
+ start, done);
+ total_pkts++;
+ total_bytes += start ? len : len + hdrlen;
+ desc = ionic_tx_tso_next(q, &elem);
+ start = false;
+ seglen = mss;
+ }
+
+ /* Chop skb frags into desc segments */
+
+ for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
+ offset = 0;
+ left = skb_frag_size(frag);
+ len_left -= left;
+ nfrags--;
+ stats->frags++;
+
+ while (left > 0) {
+ if (frag_left > 0) {
+ len = min(frag_left, left);
+ frag_left -= len;
+ elem->addr =
+ cpu_to_le64(ionic_tx_map_frag(q, frag,
+ offset, len));
+ if (!elem->addr)
+ goto err_out_abort;
+ elem->len = cpu_to_le16(len);
+ elem++;
+ desc_nsge++;
+ left -= len;
+ offset += len;
+ if (nfrags > 0 && frag_left > 0)
+ continue;
+ done = (nfrags == 0 && left == 0);
+ ionic_tx_tso_post(q, desc, skb, desc_addr,
+ desc_nsge, desc_len,
+ hdrlen, mss, outer_csum,
+ vlan_tci, has_vlan,
+ start, done);
+ total_pkts++;
+ total_bytes += start ? len : len + hdrlen;
+ desc = ionic_tx_tso_next(q, &elem);
+ start = false;
+ } else {
+ len = min(mss, left);
+ frag_left = mss - len;
+ desc_addr = ionic_tx_map_frag(q, frag,
+ offset, len);
+ if (!desc_addr)
+ goto err_out_abort;
+ desc_len = len;
+ desc_nsge = 0;
+ left -= len;
+ offset += len;
+ if (nfrags > 0 && frag_left > 0)
+ continue;
+ done = (nfrags == 0 && left == 0);
+ ionic_tx_tso_post(q, desc, skb, desc_addr,
+ desc_nsge, desc_len,
+ hdrlen, mss, outer_csum,
+ vlan_tci, has_vlan,
+ start, done);
+ total_pkts++;
+ total_bytes += start ? len : len + hdrlen;
+ desc = ionic_tx_tso_next(q, &elem);
+ start = false;
+ }
+ }
+ }
+
+ stats->pkts += total_pkts;
+ stats->bytes += total_bytes;
+ stats->tso++;
+
+ return 0;
+
+err_out_abort:
+ while (rewind->desc != q->head->desc) {
+ ionic_tx_clean(q, rewind, NULL, NULL);
+ rewind = rewind->next;
+ }
+ q->head = abort;
+
+ return -ENOMEM;
+}
+
+static int ionic_tx_calc_csum(struct queue *q, struct sk_buff *skb)
+{
+ struct tx_stats *stats = q_to_tx_stats(q);
+ struct txq_desc *desc = q->head->desc;
+ dma_addr_t addr;
+ bool has_vlan;
+ u8 flags = 0;
+ bool encap;
+ u64 cmd;
+
+ has_vlan = !!skb_vlan_tag_present(skb);
+ encap = skb->encapsulation;
+
+ addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb));
+ if (!addr)
+ return -ENOMEM;
+
+ flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
+ flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
+
+ cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL,
+ flags, skb_shinfo(skb)->nr_frags, addr);
+ desc->cmd = cpu_to_le64(cmd);
+ desc->len = cpu_to_le16(skb_headlen(skb));
+ desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
+ desc->csum_start = cpu_to_le16(skb_checksum_start_offset(skb));
+ desc->csum_offset = cpu_to_le16(skb->csum_offset);
+
+ if (skb->csum_not_inet)
+ stats->crc32_csum++;
+ else
+ stats->csum++;
+
+ return 0;
+}
+
+static int ionic_tx_calc_no_csum(struct queue *q, struct sk_buff *skb)
+{
+ struct tx_stats *stats = q_to_tx_stats(q);
+ struct txq_desc *desc = q->head->desc;
+ dma_addr_t addr;
+ bool has_vlan;
+ u8 flags = 0;
+ bool encap;
+ u64 cmd;
+
+ has_vlan = !!skb_vlan_tag_present(skb);
+ encap = skb->encapsulation;
+
+ addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb));
+ if (!addr)
+ return -ENOMEM;
+
+ flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
+ flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
+
+ cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_NONE,
+ flags, skb_shinfo(skb)->nr_frags, addr);
+ desc->cmd = cpu_to_le64(cmd);
+ desc->len = cpu_to_le16(skb_headlen(skb));
+ desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
+
+ stats->no_csum++;
+
+ return 0;
+}
+
+static int ionic_tx_skb_frags(struct queue *q, struct sk_buff *skb)
+{
+ unsigned int len_left = skb->len - skb_headlen(skb);
+ struct txq_sg_desc *sg_desc = q->head->sg_desc;
+ struct txq_sg_elem *elem = sg_desc->elems;
+ struct tx_stats *stats = q_to_tx_stats(q);
+ dma_addr_t dma_addr;
+ skb_frag_t *frag;
+ u16 len;
+
+ for (frag = skb_shinfo(skb)->frags; len_left; frag++, elem++) {
+ len = skb_frag_size(frag);
+ elem->len = cpu_to_le16(len);
+ dma_addr = ionic_tx_map_frag(q, frag, 0, len);
+ if (!dma_addr)
+ return -ENOMEM;
+ elem->addr = cpu_to_le64(dma_addr);
+ len_left -= len;
+ stats->frags++;
+ }
+
+ return 0;
+}
+
+static int ionic_tx(struct queue *q, struct sk_buff *skb)
+{
+ struct tx_stats *stats = q_to_tx_stats(q);
+ int err;
+
+ if (skb->ip_summed == CHECKSUM_PARTIAL)
+ err = ionic_tx_calc_csum(q, skb);
+ else
+ err = ionic_tx_calc_no_csum(q, skb);
+ if (err)
+ return err;
+
+ err = ionic_tx_skb_frags(q, skb);
+ if (err)
+ return err;
+
+ skb_tx_timestamp(skb);
+ stats->pkts++;
+ stats->bytes += skb->len;
+
+ ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb);
+
+ return 0;
+}
+
+static int ionic_tx_descs_needed(struct queue *q, struct sk_buff *skb)
+{
+ struct tx_stats *stats = q_to_tx_stats(q);
+ int err;
+
+ /* If TSO, need roundup(skb->len/mss) descs */
+ if (skb_is_gso(skb))
+ return (skb->len / skb_shinfo(skb)->gso_size) + 1;
+
+ /* If non-TSO, just need 1 desc and nr_frags sg elems */
+ if (skb_shinfo(skb)->nr_frags <= IONIC_TX_MAX_SG_ELEMS)
+ return 1;
+
+ /* Too many frags, so linearize */
+ err = skb_linearize(skb);
+ if (err)
+ return err;
+
+ stats->linearize++;
+
+ /* Need 1 desc and zero sg elems */
+ return 1;
+}
+
+netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+ u16 queue_index = skb_get_queue_mapping(skb);
+ struct lif *lif = netdev_priv(netdev);
+ struct queue *q;
+ int ndescs;
+ int err;
+
+ if (unlikely(!test_bit(LIF_UP, lif->state))) {
+ dev_kfree_skb(skb);
+ return NETDEV_TX_OK;
+ }
+
+ if (likely(lif_to_txqcq(lif, queue_index)))
+ q = lif_to_txq(lif, queue_index);
+ else
+ q = lif_to_txq(lif, 0);
+
+ ndescs = ionic_tx_descs_needed(q, skb);
+ if (ndescs < 0)
+ goto err_out_drop;
+
+ if (!ionic_q_has_space(q, ndescs)) {
+ netif_stop_subqueue(netdev, queue_index);
+ q->stop++;
+
+ /* Might race with ionic_tx_clean, check again */
+ smp_rmb();
+ if (ionic_q_has_space(q, ndescs)) {
+ netif_wake_subqueue(netdev, queue_index);
+ q->wake++;
+ } else {
+ return NETDEV_TX_BUSY;
+ }
+ }
+
+ if (skb_is_gso(skb))
+ err = ionic_tx_tso(q, skb);
+ else
+ err = ionic_tx(q, skb);
+
+ if (err)
+ goto err_out_drop;
+
+ return NETDEV_TX_OK;
+
+err_out_drop:
+ netif_stop_subqueue(netdev, queue_index);
+ q->stop++;
+ q->drop++;
+ dev_kfree_skb(skb);
+ return NETDEV_TX_OK;
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_txrx.h b/drivers/net/ethernet/pensando/ionic/ionic_txrx.h
new file mode 100644
index 000000000000..2391a0eec65a
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_txrx.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#ifndef _IONIC_TXRX_H_
+#define _IONIC_TXRX_H_
+
+void ionic_rx_flush(struct cq *cq);
+void ionic_tx_flush(struct cq *cq);
+
+void ionic_rx_fill(struct queue *q);
+void ionic_rx_empty(struct queue *q);
+int ionic_rx_napi(struct napi_struct *napi, int budget);
+netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device *netdev);
+
+#endif /* _IONIC_TXRX_H_ */
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 14/19] ionic: Add Tx and Rx handling
2019-07-22 21:40 ` [PATCH v4 net-next 14/19] ionic: Add Tx and Rx handling Shannon Nelson
@ 2019-07-23 21:36 ` David Miller
2019-07-25 23:48 ` Saeed Mahameed
1 sibling, 0 replies; 69+ messages in thread
From: David Miller @ 2019-07-23 21:36 UTC (permalink / raw)
To: snelson; +Cc: netdev
From: Shannon Nelson <snelson@pensando.io>
Date: Mon, 22 Jul 2019 14:40:18 -0700
> Add both the Tx and Rx queue setup and handling. The related
> stats display comes later. Instead of using the generic napi
> routines used by the slow-path commands, the Tx and Rx paths
> are simplified and inlined in one file in order to get better
> compiler optimizations.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
A lot of reverse christmas tree ordering violations here, please
fix all of them.
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 14/19] ionic: Add Tx and Rx handling
2019-07-22 21:40 ` [PATCH v4 net-next 14/19] ionic: Add Tx and Rx handling Shannon Nelson
2019-07-23 21:36 ` David Miller
@ 2019-07-25 23:48 ` Saeed Mahameed
2019-08-09 22:27 ` Shannon Nelson
1 sibling, 1 reply; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-25 23:48 UTC (permalink / raw)
To: snelson, netdev, davem
On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> Add both the Tx and Rx queue setup and handling. The related
> stats display comes later. Instead of using the generic napi
> routines used by the slow-path commands, the Tx and Rx paths
> are simplified and inlined in one file in order to get better
> compiler optimizations.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
> ---
> drivers/net/ethernet/pensando/ionic/Makefile | 2 +-
> .../net/ethernet/pensando/ionic/ionic_lif.c | 387 ++++++++
> .../net/ethernet/pensando/ionic/ionic_lif.h | 52 ++
> .../net/ethernet/pensando/ionic/ionic_txrx.c | 879
> ++++++++++++++++++
> .../net/ethernet/pensando/ionic/ionic_txrx.h | 15 +
> 5 files changed, 1334 insertions(+), 1 deletion(-)
> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_txrx.c
> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_txrx.h
>
> diff --git a/drivers/net/ethernet/pensando/ionic/Makefile
> b/drivers/net/ethernet/pensando/ionic/Makefile
> index 9b19bf57a489..0e2dc53f08d4 100644
> --- a/drivers/net/ethernet/pensando/ionic/Makefile
> +++ b/drivers/net/ethernet/pensando/ionic/Makefile
> @@ -4,4 +4,4 @@
> obj-$(CONFIG_IONIC) := ionic.o
>
> ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_ethtool.o
> \
> - ionic_lif.o ionic_rx_filter.o ionic_debugfs.o
> + ionic_lif.o ionic_rx_filter.o ionic_txrx.o ionic_debugfs.o
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> index 2bd8ce61c4a0..40d3b1cb362a 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> @@ -10,6 +10,7 @@
> #include "ionic.h"
> #include "ionic_bus.h"
> #include "ionic_lif.h"
> +#include "ionic_txrx.h"
> #include "ionic_ethtool.h"
> #include "ionic_debugfs.h"
>
> @@ -18,6 +19,13 @@ static int ionic_lif_addr_add(struct lif *lif,
> const u8 *addr);
> static int ionic_lif_addr_del(struct lif *lif, const u8 *addr);
> static void ionic_link_status_check(struct lif *lif);
>
> +static int ionic_lif_stop(struct lif *lif);
> +static int ionic_txrx_alloc(struct lif *lif);
> +static int ionic_txrx_init(struct lif *lif);
> +static void ionic_qcq_free(struct lif *lif, struct qcq *qcq);
> +static int ionic_lif_txqs_init(struct lif *lif);
> +static int ionic_lif_rxqs_init(struct lif *lif);
> +static void ionic_lif_qcq_deinit(struct lif *lif, struct qcq *qcq);
> static int ionic_set_nic_features(struct lif *lif, netdev_features_t
> features);
> static int ionic_notifyq_clean(struct lif *lif, int budget);
>
> @@ -66,12 +74,96 @@ static void ionic_lif_deferred_enqueue(struct
> ionic_deferred *def,
> schedule_work(&def->work);
> }
Bottom up or top down ? your current design is very mixed and I had to
to scroll down and up too often just to understand what a function is
doing, i strongly suggest to pick an use one approach.
[1]
https://en.wikipedia.org/wiki/Top-down_and_bottom-up_design#Programming
>
> +static int ionic_qcq_enable(struct qcq *qcq)
> +{
> + struct queue *q = &qcq->q;
> + struct lif *lif = q->lif;
> + struct device *dev = lif->ionic->dev;
> + struct ionic_dev *idev = &lif->ionic->idev;
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.q_control = {
> + .opcode = CMD_OPCODE_Q_CONTROL,
> + .lif_index = cpu_to_le16(lif->index),
> + .type = q->type,
> + .index = cpu_to_le32(q->index),
> + .oper = IONIC_Q_ENABLE,
> + },
> + };
> +
> + dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",
> + ctx.cmd.q_control.index, ctx.cmd.q_control.type);
> +
> + if (qcq->flags & QCQ_F_INTR) {
> + irq_set_affinity_hint(qcq->intr.vector,
> + &qcq->intr.affinity_mask);
> + napi_enable(&qcq->napi);
> + ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
> + ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
> + IONIC_INTR_MASK_CLEAR);
> + }
> +
> + return ionic_adminq_post_wait(lif, &ctx);
> +}
> +
> +static int ionic_qcq_disable(struct qcq *qcq)
> +{
> + struct queue *q = &qcq->q;
> + struct lif *lif = q->lif;
> + struct device *dev = lif->ionic->dev;
> + struct ionic_dev *idev = &lif->ionic->idev;
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.q_control = {
> + .opcode = CMD_OPCODE_Q_CONTROL,
> + .lif_index = cpu_to_le16(lif->index),
> + .type = q->type,
> + .index = cpu_to_le32(q->index),
> + .oper = IONIC_Q_DISABLE,
> + },
> + };
> +
> + dev_dbg(dev, "q_disable.index %d q_disable.qtype %d\n",
> + ctx.cmd.q_control.index, ctx.cmd.q_control.type);
> +
> + if (qcq->flags & QCQ_F_INTR) {
> + ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
> + IONIC_INTR_MASK_SET);
> + synchronize_irq(qcq->intr.vector);
> + irq_set_affinity_hint(qcq->intr.vector, NULL);
> + napi_disable(&qcq->napi);
> + }
> +
> + return ionic_adminq_post_wait(lif, &ctx);
> +}
> +
> int ionic_open(struct net_device *netdev)
> {
> struct lif *lif = netdev_priv(netdev);
> + unsigned int i;
> + int err;
>
> netif_carrier_off(netdev);
>
> + err = ionic_txrx_alloc(lif);
> + if (err)
> + return err;
> +
> + err = ionic_txrx_init(lif);
> + if (err)
> + goto err_out;
> +
> + for (i = 0; i < lif->nxqs; i++) {
> + err = ionic_qcq_enable(lif->txqcqs[i].qcq);
> + if (err)
> + goto err_out;
> +
> + ionic_rx_fill(&lif->rxqcqs[i].qcq->q);
> + err = ionic_qcq_enable(lif->rxqcqs[i].qcq);
> + if (err)
> + goto err_out;
> + }
> +
> set_bit(LIF_UP, lif->state);
>
> ionic_link_status_check(lif);
> @@ -79,11 +171,16 @@ int ionic_open(struct net_device *netdev)
> netif_tx_wake_all_queues(netdev);
>
> return 0;
> +
> +err_out:
> + ionic_lif_stop(lif);
This is dangerous, maybe now it is ok to stop a partially open driver,
but future development might break this assumption, and to avoid this i
strongly recommend to have a symmetrical cleanup flow, or have a
documentation that says ionic_lif_stop might be called with partially
open resources and proper checks must be done.
> + return err;
> }
>
> static int ionic_lif_stop(struct lif *lif)
> {
> struct net_device *ndev = lif->netdev;
> + unsigned int i;
> int err = 0;
>
> if (!test_bit(LIF_UP, lif->state)) {
> @@ -100,6 +197,21 @@ static int ionic_lif_stop(struct lif *lif)
> netif_tx_disable(ndev);
> synchronize_rcu();
>
> + for (i = 0; i < lif->nxqs; i++) {
> + (void)ionic_qcq_disable(lif->txqcqs[i].qcq);
> + ionic_tx_flush(&lif->txqcqs[i].qcq->cq);
> + ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq);
> + ionic_qcq_free(lif, lif->txqcqs[i].qcq);
> + lif->txqcqs[i].qcq = NULL;
> +
> + (void)ionic_qcq_disable(lif->rxqcqs[i].qcq);
> + ionic_rx_flush(&lif->rxqcqs[i].qcq->cq);
> + ionic_lif_qcq_deinit(lif, lif->rxqcqs[i].qcq);
> + ionic_rx_empty(&lif->rxqcqs[i].qcq->q);
> + ionic_qcq_free(lif, lif->rxqcqs[i].qcq);
> + lif->rxqcqs[i].qcq = NULL;
> + }
> +
Why don't you break this down to stages/functions (disbale/uninit/free)
as you did on open (alloc/ini/enable) ? will be easier to review and
to spot inconsistencies
> return err;
> }
>
> @@ -694,6 +806,7 @@ static int ionic_vlan_rx_kill_vid(struct
> net_device *netdev, __be16 proto,
> static const struct net_device_ops ionic_netdev_ops = {
> .ndo_open = ionic_open,
> .ndo_stop = ionic_stop,
> + .ndo_start_xmit = ionic_start_xmit,
> .ndo_get_stats64 = ionic_get_stats64,
> .ndo_set_rx_mode = ionic_set_rx_mode,
> .ndo_set_features = ionic_set_features,
> @@ -909,10 +1022,83 @@ static void ionic_qcq_free(struct lif *lif,
> struct qcq *qcq)
> devm_kfree(dev, qcq);
> }
>
> +static int ionic_txrx_alloc(struct lif *lif)
> +{
> + unsigned int flags;
> + unsigned int i;
> + int err = 0;
> +
> + flags = QCQ_F_TX_STATS | QCQ_F_SG;
> + for (i = 0; i < lif->nxqs; i++) {
> + err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx",
> flags,
> + lif->ntxq_descs,
> + sizeof(struct txq_desc),
> + sizeof(struct txq_comp),
> + sizeof(struct txq_sg_desc),
> + lif->kern_pid, &lif-
> >txqcqs[i].qcq);
> + if (err)
> + goto err_out_free_txqcqs;
> +
> + lif->txqcqs[i].qcq->stats = lif->txqcqs[i].stats;
> + }
> +
> + flags = QCQ_F_RX_STATS | QCQ_F_INTR;
> + for (i = 0; i < lif->nxqs; i++) {
> + err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx",
> flags,
> + lif->nrxq_descs,
> + sizeof(struct rxq_desc),
> + sizeof(struct rxq_comp),
> + 0, lif->kern_pid, &lif-
> >rxqcqs[i].qcq);
> + if (err)
> + goto err_out_free_rxqcqs;
> +
> + lif->rxqcqs[i].qcq->stats = lif->rxqcqs[i].stats;
> +
> + ionic_link_qcq_interrupts(lif->rxqcqs[i].qcq,
> + lif->txqcqs[i].qcq);
> + }
> +
> + return 0;
> +
> +err_out_free_rxqcqs:
> + for (i = 0; i < lif->nxqs; i++)
> + ionic_qcq_free(lif, lif->rxqcqs[i].qcq);
> +err_out_free_txqcqs:
> + for (i = 0; i < lif->nxqs; i++)
> + ionic_qcq_free(lif, lif->txqcqs[i].qcq);
> +
> + return err;
> +}
> +
> +static int ionic_txrx_init(struct lif *lif)
> +{
> + int err;
> +
> + err = ionic_lif_txqs_init(lif);
> + if (err)
> + return err;
> +
> + err = ionic_lif_rxqs_init(lif);
> + if (err)
> + goto err_out;
> +
> + ionic_set_rx_mode(lif->netdev);
> +
> + return 0;
> +
> +err_out:
> + ionic_stop(lif->netdev);
I would move error handling to the caller, keep the code flow and err
path symmetrical with good path.
> +
> + return err;
> +}
> +
> static int ionic_qcqs_alloc(struct lif *lif)
> {
> + struct device *dev = lif->ionic->dev;
> + unsigned int q_list_size;
> unsigned int flags;
> int err;
> + int i;
>
> flags = QCQ_F_INTR;
> err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin",
> flags,
> @@ -937,8 +1123,47 @@ static int ionic_qcqs_alloc(struct lif *lif)
> ionic_link_qcq_interrupts(lif->adminqcq, lif-
> >notifyqcq);
> }
>
> + q_list_size = sizeof(*lif->txqcqs) * lif->nxqs;
> + err = -ENOMEM;
> + lif->txqcqs = devm_kzalloc(dev, q_list_size, GFP_KERNEL);
> + if (!lif->txqcqs)
> + goto err_out_free_notifyqcq;
> + for (i = 0; i < lif->nxqs; i++) {
> + lif->txqcqs[i].stats = devm_kzalloc(dev, sizeof(struct
> q_stats),
> + GFP_KERNEL);
why not inlineing stats into txqcq struct and avoid this kzalloc ?
> + if (!lif->txqcqs[i].stats)
> + goto err_out_free_tx_stats;
> + }
> +
> + lif->rxqcqs = devm_kzalloc(dev, q_list_size, GFP_KERNEL);
> + if (!lif->rxqcqs)
> + goto err_out_free_tx_stats;
> + for (i = 0; i < lif->nxqs; i++) {
> + lif->rxqcqs[i].stats = devm_kzalloc(dev, sizeof(struct
> q_stats),
> + GFP_KERNEL);
> + if (!lif->rxqcqs[i].stats)
> + goto err_out_free_rx_stats;
same
> + }
> +
> return 0;
>
> +err_out_free_rx_stats:
> + for (i = 0; i < lif->nxqs; i++)
> + if (lif->rxqcqs[i].stats)
> + devm_kfree(dev, lif->rxqcqs[i].stats);
> + devm_kfree(dev, lif->rxqcqs);
> + lif->rxqcqs = NULL;
> +err_out_free_tx_stats:
> + for (i = 0; i < lif->nxqs; i++)
> + if (lif->txqcqs[i].stats)
> + devm_kfree(dev, lif->txqcqs[i].stats);
> + devm_kfree(dev, lif->txqcqs);
> + lif->txqcqs = NULL;
> +err_out_free_notifyqcq:
> + if (lif->notifyqcq) {
> + ionic_qcq_free(lif, lif->notifyqcq);
> + lif->notifyqcq = NULL;
> + }
> err_out_free_adminqcq:
> ionic_qcq_free(lif, lif->adminqcq);
> lif->adminqcq = NULL;
> @@ -948,6 +1173,9 @@ static int ionic_qcqs_alloc(struct lif *lif)
>
> static void ionic_qcqs_free(struct lif *lif)
> {
> + struct device *dev = lif->ionic->dev;
> + unsigned int i;
> +
> if (lif->notifyqcq) {
> ionic_qcq_free(lif, lif->notifyqcq);
> lif->notifyqcq = NULL;
> @@ -957,6 +1185,20 @@ static void ionic_qcqs_free(struct lif *lif)
> ionic_qcq_free(lif, lif->adminqcq);
> lif->adminqcq = NULL;
> }
> +
> + for (i = 0; i < lif->nxqs; i++)
> + if (lif->rxqcqs[i].stats)
> + devm_kfree(dev, lif->rxqcqs[i].stats);
> +
> + devm_kfree(dev, lif->rxqcqs);
> + lif->rxqcqs = NULL;
> +
> + for (i = 0; i < lif->nxqs; i++)
> + if (lif->txqcqs[i].stats)
> + devm_kfree(dev, lif->txqcqs[i].stats);
> +
> + devm_kfree(dev, lif->txqcqs);
> + lif->txqcqs = NULL;
> }
>
> static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int
> index)
> @@ -992,6 +1234,8 @@ static struct lif *ionic_lif_alloc(struct ionic
> *ionic, unsigned int index)
>
> lif->ionic = ionic;
> lif->index = index;
> + lif->ntxq_descs = IONIC_DEF_TXRX_DESC;
> + lif->nrxq_descs = IONIC_DEF_TXRX_DESC;
>
> snprintf(lif->name, sizeof(lif->name), "lif%u", index);
>
> @@ -1432,6 +1676,147 @@ static int ionic_init_nic_features(struct lif
> *lif)
> return 0;
> }
>
> +static int ionic_lif_txq_init(struct lif *lif, struct qcq *qcq)
> +{
> + struct device *dev = lif->ionic->dev;
> + struct queue *q = &qcq->q;
> + struct cq *cq = &qcq->cq;
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.q_init = {
> + .opcode = CMD_OPCODE_Q_INIT,
> + .lif_index = cpu_to_le16(lif->index),
> + .type = q->type,
> + .index = cpu_to_le32(q->index),
> + .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
> + IONIC_QINIT_F_SG),
> + .intr_index = cpu_to_le16(lif->rxqcqs[q-
> >index].qcq->intr.index),
> + .pid = cpu_to_le16(q->pid),
> + .ring_size = ilog2(q->num_descs),
> + .ring_base = cpu_to_le64(q->base_pa),
> + .cq_ring_base = cpu_to_le64(cq->base_pa),
> + .sg_ring_base = cpu_to_le64(q->sg_base_pa),
> + },
> + };
> + int err;
> +
> + dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid);
> + dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index);
> + dev_dbg(dev, "txq_init.ring_base 0x%llx\n",
> ctx.cmd.q_init.ring_base);
> + dev_dbg(dev, "txq_init.ring_size %d\n",
> ctx.cmd.q_init.ring_size);
> +
> + err = ionic_adminq_post_wait(lif, &ctx);
> + if (err)
> + return err;
> +
> + q->hw_type = ctx.comp.q_init.hw_type;
> + q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
> + q->dbval = IONIC_DBELL_QID(q->hw_index);
> +
> + dev_dbg(dev, "txq->hw_type %d\n", q->hw_type);
> + dev_dbg(dev, "txq->hw_index %d\n", q->hw_index);
> +
> + qcq->flags |= QCQ_F_INITED;
> +
> + ionic_debugfs_add_qcq(lif, qcq);
> +
> + return 0;
> +}
> +
> +static int ionic_lif_txqs_init(struct lif *lif)
> +{
> + unsigned int i;
> + int err;
> +
> + for (i = 0; i < lif->nxqs; i++) {
> + err = ionic_lif_txq_init(lif, lif->txqcqs[i].qcq);
> + if (err)
> + goto err_out;
> + }
> +
> + return 0;
> +
> +err_out:
> + for (; i > 0; i--)
> + ionic_lif_qcq_deinit(lif, lif->txqcqs[i-1].qcq);
> +
> + return err;
> +}
> +
> +static int ionic_lif_rxq_init(struct lif *lif, struct qcq *qcq)
> +{
> + struct device *dev = lif->ionic->dev;
> + struct queue *q = &qcq->q;
> + struct cq *cq = &qcq->cq;
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.q_init = {
> + .opcode = CMD_OPCODE_Q_INIT,
> + .lif_index = cpu_to_le16(lif->index),
> + .type = q->type,
> + .index = cpu_to_le32(q->index),
> + .flags = cpu_to_le16(IONIC_QINIT_F_IRQ),
> + .intr_index = cpu_to_le16(cq->bound_intr-
> >index),
> + .pid = cpu_to_le16(q->pid),
> + .ring_size = ilog2(q->num_descs),
> + .ring_base = cpu_to_le64(q->base_pa),
> + .cq_ring_base = cpu_to_le64(cq->base_pa),
> + },
> + };
> + int err;
> +
> + dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid);
> + dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index);
> + dev_dbg(dev, "rxq_init.ring_base 0x%llx\n",
> ctx.cmd.q_init.ring_base);
> + dev_dbg(dev, "rxq_init.ring_size %d\n",
> ctx.cmd.q_init.ring_size);
> +
> + err = ionic_adminq_post_wait(lif, &ctx);
> + if (err)
> + return err;
> +
> + q->hw_type = ctx.comp.q_init.hw_type;
> + q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
> + q->dbval = IONIC_DBELL_QID(q->hw_index);
> +
> + dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type);
> + dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index);
> +
> + netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi,
> + NAPI_POLL_WEIGHT);
> +
> + err = ionic_request_irq(lif, qcq);
Again, your init/deinit objects code paths is very asymmetrical
I was looking for where you do free_irq, and eventually found it in
ionic_lif_qcq_deinit which is shared between rx/tx queues, but it is
very hard to follow who sets the QCQ_F_INTR flag so
ionic_lif_qcq_deinit would free the irq. so i gave up !
I strongly suggest for you to make the code symmetrical as much as
possible by following two simple rules:
1) each function "do_foo" must have a reverse function "undo_foo"..
2) each function "do_foo" should handle its own error path rollback and
NOT by blindly calling "undo_foo"
This is a very well defined code structure and useful technique to help
reviewers and developers keep track of what is happening, and most
importantly a very good practice that reduces the number of current
bugs and future bugs by an order of magnitude!
example:
open()
alloc_txrx_queues()
init_txrx_queues()
request_irqs()
enable_txrx_queues()
close()
disable_txrx_queues()
free_irqs()
deinit_txrx_queues()
dealloc_txrxqs()
this will remove the need for some flags and unnecessary state tracking
for when a resources is open/close/inited, if each function is
symmetrical and handles its own rollback, so at any point in the code
you would know what to do without any extra if statement branches.
> + if (err) {
> + netif_napi_del(&qcq->napi);
> + return err;
> + }
> +
> + qcq->flags |= QCQ_F_INITED;
> +
> + ionic_debugfs_add_qcq(lif, qcq);
> +
> + return 0;
> +}
> +
> +static int ionic_lif_rxqs_init(struct lif *lif)
> +{
> + unsigned int i;
> + int err;
> +
> + for (i = 0; i < lif->nxqs; i++) {
> + err = ionic_lif_rxq_init(lif, lif->rxqcqs[i].qcq);
> + if (err)
> + goto err_out;
> + }
> +
> + return 0;
> +
> +err_out:
> + for (; i > 0; i--)
> + ionic_lif_qcq_deinit(lif, lif->rxqcqs[i-1].qcq);
> +
> + return err;
> +}
> +
> static int ionic_station_set(struct lif *lif)
> {
> struct net_device *netdev = lif->netdev;
> @@ -1531,6 +1916,8 @@ static int ionic_lif_init(struct lif *lif)
> if (err)
> goto err_out_notifyq_deinit;
>
> + lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT;
> +
> set_bit(LIF_INITED, lif->state);
>
> ionic_link_status_check(lif);
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> index d8589a306aa5..88d5bf8f58a1 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> @@ -14,20 +14,38 @@
> #define MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1)
> #define GET_SG_CNTR_IDX(num_sg_elems) (num_sg_elems)
> #define MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1)
> +#define IONIC_RX_COPYBREAK_DEFAULT 256
>
> struct tx_stats {
> + u64 dma_map_err;
> u64 pkts;
> u64 bytes;
> + u64 clean;
> + u64 linearize;
> + u64 no_csum;
> + u64 csum;
> + u64 crc32_csum;
> + u64 tso;
> + u64 frags;
> + u64 sg_cntr[MAX_NUM_SG_CNTR];
> };
>
> struct rx_stats {
> + u64 dma_map_err;
> + u64 alloc_err;
> u64 pkts;
> u64 bytes;
> + u64 csum_none;
> + u64 csum_complete;
> + u64 csum_error;
> + u64 buffers_posted;
> };
>
> #define QCQ_F_INITED BIT(0)
> #define QCQ_F_SG BIT(1)
> #define QCQ_F_INTR BIT(2)
> +#define QCQ_F_TX_STATS BIT(3)
> +#define QCQ_F_RX_STATS BIT(4)
> #define QCQ_F_NOTIFYQ BIT(5)
>
> struct napi_stats {
> @@ -56,7 +74,14 @@ struct qcq {
> struct dentry *dentry;
> };
>
> +struct qcqst {
> + struct qcq *qcq;
> + struct q_stats *stats;
> +};
> +
> #define q_to_qcq(q) container_of(q, struct qcq, q)
> +#define q_to_tx_stats(q) (&q_to_qcq(q)->stats->tx)
> +#define q_to_rx_stats(q) (&q_to_qcq(q)->stats->rx)
> #define napi_to_qcq(napi) container_of(napi, struct qcq, napi)
> #define napi_to_cq(napi) (&napi_to_qcq(napi)->cq)
>
> @@ -108,11 +133,14 @@ struct lif {
> spinlock_t adminq_lock; /* lock for AdminQ operations
> */
> struct qcq *adminqcq;
> struct qcq *notifyqcq;
> + struct qcqst *txqcqs;
> + struct qcqst *rxqcqs;
> u64 last_eid;
> unsigned int neqs;
> unsigned int nxqs;
> unsigned int ntxq_descs;
> unsigned int nrxq_descs;
> + u32 rx_copybreak;
> unsigned int rx_mode;
> u64 hw_features;
> bool mc_overflow;
> @@ -134,6 +162,11 @@ struct lif {
> u32 flags;
> };
>
> +#define lif_to_txqcq(lif, i) ((lif)->txqcqs[i].qcq)
> +#define lif_to_rxqcq(lif, i) ((lif)->rxqcqs[i].qcq)
> +#define lif_to_txq(lif, i) (&lif_to_txqcq((lif), i)->q)
> +#define lif_to_rxq(lif, i) (&lif_to_txqcq((lif), i)->q)
> +
> static inline bool ionic_is_pf(struct ionic *ionic)
> {
> return ionic->pdev &&
> @@ -173,6 +206,22 @@ int ionic_open(struct net_device *netdev);
> int ionic_stop(struct net_device *netdev);
> int ionic_reset_queues(struct lif *lif);
>
> +static inline void debug_stats_txq_post(struct qcq *qcq,
> + struct txq_desc *desc, bool
> dbell)
> +{
> + u8 num_sg_elems = ((le64_to_cpu(desc->cmd) >>
> IONIC_TXQ_DESC_NSGE_SHIFT)
> + &
> IONIC_TXQ_DESC_NSGE_MASK);
> + u8 sg_cntr_idx;
> +
> + qcq->q.dbell_count += dbell;
> +
> + sg_cntr_idx = GET_SG_CNTR_IDX(num_sg_elems);
> + if (sg_cntr_idx > (MAX_NUM_SG_CNTR - 1))
> + sg_cntr_idx = MAX_NUM_SG_CNTR - 1;
> +
> + qcq->stats->tx.sg_cntr[sg_cntr_idx]++;
> +}
> +
> static inline void debug_stats_napi_poll(struct qcq *qcq,
> unsigned int work_done)
> {
> @@ -188,7 +237,10 @@ static inline void debug_stats_napi_poll(struct
> qcq *qcq,
> }
>
> #define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++)
> +#define DEBUG_STATS_RX_BUFF_CNT(qcq) ((qcq)->stats-
> >rx.buffers_posted++)
> #define DEBUG_STATS_INTR_REARM(intr) ((intr)->rearm_count++)
> +#define DEBUG_STATS_TXQ_POST(qcq, txdesc, dbell) \
> + debug_stats_txq_post(qcq, txdesc, dbell)
> #define DEBUG_STATS_NAPI_POLL(qcq, work_done) \
> debug_stats_napi_poll(qcq, work_done)
>
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_txrx.c
> b/drivers/net/ethernet/pensando/ionic/ionic_txrx.c
> new file mode 100644
> index 000000000000..7787e7dd5504
> --- /dev/null
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_txrx.c
> @@ -0,0 +1,879 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
> +
> +#include <linux/ip.h>
> +#include <linux/ipv6.h>
> +#include <linux/if_vlan.h>
> +#include <net/ip6_checksum.h>
> +
> +#include "ionic.h"
> +#include "ionic_lif.h"
> +#include "ionic_txrx.h"
> +
> +static void ionic_tx_clean(struct queue *q, struct desc_info
> *desc_info,
> + struct cq_info *cq_info, void *cb_arg);
> +static void ionic_rx_clean(struct queue *q, struct desc_info
> *desc_info,
> + struct cq_info *cq_info, void *cb_arg);
> +
> +static inline void ionic_txq_post(struct queue *q, bool ring_dbell,
> + desc_cb cb_func, void *cb_arg)
> +{
> + DEBUG_STATS_TXQ_POST(q_to_qcq(q), q->head->desc, ring_dbell);
> +
> + ionic_q_post(q, ring_dbell, cb_func, cb_arg);
> +}
> +
> +static inline void ionic_rxq_post(struct queue *q, bool ring_dbell,
> + desc_cb cb_func, void *cb_arg)
> +{
> + ionic_q_post(q, ring_dbell, cb_func, cb_arg);
> +
> + DEBUG_STATS_RX_BUFF_CNT(q_to_qcq(q));
> +}
> +
> +static void ionic_rx_recycle(struct queue *q, struct desc_info
> *desc_info,
> + struct sk_buff *skb)
> +{
> + struct rxq_desc *old = desc_info->desc;
> + struct rxq_desc *new = q->head->desc;
> +
> + new->addr = old->addr;
> + new->len = old->len;
> +
> + ionic_rxq_post(q, true, ionic_rx_clean, skb);
> +}
> +
> +static bool ionic_rx_copybreak(struct queue *q, struct desc_info
> *desc_info,
> + struct cq_info *cq_info, struct sk_buff
> **skb)
> +{
> + struct net_device *netdev = q->lif->netdev;
> + struct device *dev = q->lif->ionic->dev;
> + struct rxq_desc *desc = desc_info->desc;
> + struct rxq_comp *comp = cq_info->cq_desc;
> + struct sk_buff *new_skb;
> + u16 clen, dlen;
> +
> + clen = le16_to_cpu(comp->len);
> + dlen = le16_to_cpu(desc->len);
> + if (clen > q->lif->rx_copybreak) {
> + dma_unmap_single(dev, (dma_addr_t)le64_to_cpu(desc-
> >addr),
> + dlen, DMA_FROM_DEVICE);
> + return false;
> + }
> +
> + new_skb = netdev_alloc_skb_ip_align(netdev, clen);
> + if (!new_skb) {
> + dma_unmap_single(dev, (dma_addr_t)le64_to_cpu(desc-
> >addr),
> + dlen, DMA_FROM_DEVICE);
> + return false;
> + }
> +
> + dma_sync_single_for_cpu(dev, (dma_addr_t)le64_to_cpu(desc-
> >addr),
> + clen, DMA_FROM_DEVICE);
> +
> + memcpy(new_skb->data, (*skb)->data, clen);
> +
> + ionic_rx_recycle(q, desc_info, *skb);
> + *skb = new_skb;
> +
> + return true;
> +}
> +
> +static void ionic_rx_clean(struct queue *q, struct desc_info
> *desc_info,
> + struct cq_info *cq_info, void *cb_arg)
> +{
> + struct rxq_comp *comp = cq_info->cq_desc;
> + struct sk_buff *skb = cb_arg;
> + struct qcq *qcq = q_to_qcq(q);
> + struct net_device *netdev;
> + struct rx_stats *stats;
> +
> + stats = q_to_rx_stats(q);
> + netdev = q->lif->netdev;
> +
> + if (comp->status) {
> + ionic_rx_recycle(q, desc_info, skb);
> + return;
> + }
> +
> + if (unlikely(test_bit(LIF_QUEUE_RESET, q->lif->state))) {
> + /* no packet processing while resetting */
> + ionic_rx_recycle(q, desc_info, skb);
> + return;
> + }
> +
> + stats->pkts++;
> + stats->bytes += le16_to_cpu(comp->len);
> +
> + ionic_rx_copybreak(q, desc_info, cq_info, &skb);
> +
> + skb_put(skb, le16_to_cpu(comp->len));
> + skb->protocol = eth_type_trans(skb, netdev);
> +
> + skb_record_rx_queue(skb, q->index);
> +
> + if (netdev->features & NETIF_F_RXHASH) {
> + switch (comp->pkt_type_color &
> IONIC_RXQ_COMP_PKT_TYPE_MASK) {
> + case PKT_TYPE_IPV4:
> + case PKT_TYPE_IPV6:
> + skb_set_hash(skb, le32_to_cpu(comp->rss_hash),
> + PKT_HASH_TYPE_L3);
> + break;
> + case PKT_TYPE_IPV4_TCP:
> + case PKT_TYPE_IPV6_TCP:
> + case PKT_TYPE_IPV4_UDP:
> + case PKT_TYPE_IPV6_UDP:
> + skb_set_hash(skb, le32_to_cpu(comp->rss_hash),
> + PKT_HASH_TYPE_L4);
> + break;
> + }
> + }
> +
> + if (netdev->features & NETIF_F_RXCSUM) {
> + if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) {
> + skb->ip_summed = CHECKSUM_COMPLETE;
> + skb->csum = (__wsum)le16_to_cpu(comp->csum);
> + stats->csum_complete++;
> + }
> + } else {
> + stats->csum_none++;
> + }
> +
> + if ((comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_BAD) ||
> + (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_BAD) ||
> + (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD))
> + stats->csum_error++;
> +
> + if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
> + if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN)
> + __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
> + le16_to_cpu(comp-
> >vlan_tci));
> + }
> +
> + napi_gro_receive(&qcq->napi, skb);
> +}
> +
> +static bool ionic_rx_service(struct cq *cq, struct cq_info *cq_info)
> +{
> + struct rxq_comp *comp = cq_info->cq_desc;
> + struct queue *q = cq->bound_q;
> + struct desc_info *desc_info;
> +
> + if (!color_match(comp->pkt_type_color, cq->done_color))
> + return false;
> +
> + /* check for empty queue */
> + if (q->tail->index == q->head->index)
> + return false;
> +
> + desc_info = q->tail;
> + if (desc_info->index != le16_to_cpu(comp->comp_index))
> + return false;
> +
> + q->tail = desc_info->next;
> +
> + /* clean the related q entry, only one per qc completion */
> + ionic_rx_clean(q, desc_info, cq_info, desc_info->cb_arg);
> +
> + desc_info->cb = NULL;
> + desc_info->cb_arg = NULL;
> +
> + return true;
> +}
> +
> +static u32 ionic_rx_walk_cq(struct cq *rxcq, u32 limit)
> +{
> + u32 work_done = 0;
> +
> + while (ionic_rx_service(rxcq, rxcq->tail)) {
> + if (rxcq->tail->last)
> + rxcq->done_color = !rxcq->done_color;
> + rxcq->tail = rxcq->tail->next;
> + DEBUG_STATS_CQE_CNT(rxcq);
> +
> + if (++work_done >= limit)
> + break;
> + }
> +
> + return work_done;
> +}
> +
> +void ionic_rx_flush(struct cq *cq)
> +{
> + struct ionic_dev *idev = &cq->lif->ionic->idev;
> + u32 work_done;
> +
> + work_done = ionic_rx_walk_cq(cq, cq->num_descs);
> +
> + if (work_done)
> + ionic_intr_credits(idev->intr_ctrl, cq->bound_intr-
> >index,
> + work_done,
> IONIC_INTR_CRED_RESET_COALESCE);
> +}
mixing between rx and tx unrelated flows, very hard to review.
> +
> +void ionic_tx_flush(struct cq *cq)
> +{
> + struct ionic_dev *idev = &cq->lif->ionic->idev;
> + struct txq_comp *comp = cq->tail->cq_desc;
> + struct queue *q = cq->bound_q;
> + struct desc_info *desc_info;
> + unsigned int work_done = 0;
> +
> + /* walk the completed cq entries */
> + while (work_done < cq->num_descs &&
> + color_match(comp->color, cq->done_color)) {
> +
> + /* clean the related q entries, there could be
> + * several q entries completed for each cq completion
> + */
> + do {
> + desc_info = q->tail;
> + q->tail = desc_info->next;
> + ionic_tx_clean(q, desc_info, cq->tail,
> + desc_info->cb_arg);
> + desc_info->cb = NULL;
> + desc_info->cb_arg = NULL;
> + } while (desc_info->index != le16_to_cpu(comp-
> >comp_index));
> +
> + if (cq->tail->last)
> + cq->done_color = !cq->done_color;
> +
> + cq->tail = cq->tail->next;
> + comp = cq->tail->cq_desc;
> + DEBUG_STATS_CQE_CNT(cq);
> +
> + work_done++;
> + }
> +
> + if (work_done)
> + ionic_intr_credits(idev->intr_ctrl, cq->bound_intr-
> >index,
> + work_done, 0);
> +}
> +
> +static struct sk_buff *ionic_rx_skb_alloc(struct queue *q, unsigned
> int len,
> + dma_addr_t *dma_addr)
> +{
> + struct lif *lif = q->lif;
> + struct net_device *netdev = lif->netdev;
> + struct device *dev = lif->ionic->dev;
> + struct rx_stats *stats;
> + struct sk_buff *skb;
> +
> + stats = q_to_rx_stats(q);
> + skb = netdev_alloc_skb_ip_align(netdev, len);
> + if (!skb) {
> + net_warn_ratelimited("%s: SKB alloc failed on %s!\n",
> + netdev->name, q->name);
> + stats->alloc_err++;
> + return NULL;
> + }
> +
> + *dma_addr = dma_map_single(dev, skb->data, len,
> DMA_FROM_DEVICE);
> + if (dma_mapping_error(dev, *dma_addr)) {
> + dev_kfree_skb(skb);
> + net_warn_ratelimited("%s: DMA single map failed on
> %s!\n",
> + netdev->name, q->name);
> + stats->dma_map_err++;
> + return NULL;
> + }
> +
> + return skb;
> +}
> +
> +static void ionic_rx_skb_free(struct queue *q, struct sk_buff *skb,
> + unsigned int len, dma_addr_t dma_addr)
> +{
> + struct device *dev = q->lif->ionic->dev;
> +
> + dma_unmap_single(dev, dma_addr, len, DMA_FROM_DEVICE);
> + dev_kfree_skb(skb);
> +}
> +
> +#define RX_RING_DOORBELL_STRIDE ((1 << 2) - 1)
> +
> +void ionic_rx_fill(struct queue *q)
> +{
> + struct net_device *netdev = q->lif->netdev;
> + struct rxq_desc *desc;
> + struct sk_buff *skb;
> + dma_addr_t dma_addr;
> + bool ring_doorbell;
> + unsigned int len;
> + unsigned int i;
> +
> + len = netdev->mtu + ETH_HLEN;
> +
> + for (i = ionic_q_space_avail(q); i; i--) {
> + skb = ionic_rx_skb_alloc(q, len, &dma_addr);
> + if (!skb)
> + return;
> +
> + desc = q->head->desc;
> + desc->addr = cpu_to_le64(dma_addr);
> + desc->len = cpu_to_le16(len);
> + desc->opcode = RXQ_DESC_OPCODE_SIMPLE;
> +
> + ring_doorbell = ((q->head->index + 1) &
> + RX_RING_DOORBELL_STRIDE) == 0;
> +
> + ionic_rxq_post(q, ring_doorbell, ionic_rx_clean, skb);
> + }
> +}
> +
> +static void ionic_rx_fill_cb(void *arg)
> +{
> + ionic_rx_fill(arg);
> +}
> +
> +void ionic_rx_empty(struct queue *q)
> +{
> + struct desc_info *cur = q->tail;
> + struct rxq_desc *desc;
> +
> + while (cur != q->head) {
> + desc = cur->desc;
> +
> + ionic_rx_skb_free(q, cur->cb_arg, le16_to_cpu(desc-
> >len),
> + le64_to_cpu(desc->addr));
> + cur->cb_arg = NULL;
> +
> + cur = cur->next;
> + }
> +}
> +
> +int ionic_rx_napi(struct napi_struct *napi, int budget)
> +{
> + struct qcq *qcq = napi_to_qcq(napi);
> + struct cq *rxcq = napi_to_cq(napi);
> + unsigned int qi = rxcq->bound_q->index;
> + struct lif *lif = rxcq->bound_q->lif;
> + struct ionic_dev *idev = &lif->ionic->idev;
> + struct cq *txcq = &lif->txqcqs[qi].qcq->cq;
> + u32 work_done = 0;
> + u32 flags = 0;
> +
> + ionic_tx_flush(txcq);
> +
> + work_done = ionic_rx_walk_cq(rxcq, budget);
> +
> + if (work_done)
> + ionic_rx_fill_cb(rxcq->bound_q);
> +
> + if (work_done < budget && napi_complete_done(napi, work_done))
> {
> + flags |= IONIC_INTR_CRED_UNMASK;
> + DEBUG_STATS_INTR_REARM(rxcq->bound_intr);
> + }
> +
> + if (work_done || flags) {
> + flags |= IONIC_INTR_CRED_RESET_COALESCE;
> + ionic_intr_credits(idev->intr_ctrl, rxcq->bound_intr-
> >index,
> + work_done, flags);
> + }
> +
> + DEBUG_STATS_NAPI_POLL(qcq, work_done);
> +
> + return work_done;
> +}
> +
> +static dma_addr_t ionic_tx_map_single(struct queue *q, void *data,
> size_t len)
> +{
> + struct tx_stats *stats = q_to_tx_stats(q);
> + struct device *dev = q->lif->ionic->dev;
> + dma_addr_t dma_addr;
> +
> + dma_addr = dma_map_single(dev, data, len, DMA_TO_DEVICE);
> + if (dma_mapping_error(dev, dma_addr)) {
> + net_warn_ratelimited("%s: DMA single map failed on
> %s!\n",
> + q->lif->netdev->name, q->name);
> + stats->dma_map_err++;
> + return 0;
> + }
> + return dma_addr;
> +}
> +
> +static dma_addr_t ionic_tx_map_frag(struct queue *q, const
> skb_frag_t *frag,
> + size_t offset, size_t len)
> +{
> + struct tx_stats *stats = q_to_tx_stats(q);
> + struct device *dev = q->lif->ionic->dev;
> + dma_addr_t dma_addr;
> +
> + dma_addr = skb_frag_dma_map(dev, frag, offset, len,
> DMA_TO_DEVICE);
> + if (dma_mapping_error(dev, dma_addr)) {
> + net_warn_ratelimited("%s: DMA frag map failed on
> %s!\n",
> + q->lif->netdev->name, q->name);
> + stats->dma_map_err++;
> + return 0;
> + }
> + return dma_addr;
> +}
> +
> +static void ionic_tx_clean(struct queue *q, struct desc_info
> *desc_info,
> + struct cq_info *cq_info, void *cb_arg)
> +{
> + struct txq_sg_desc *sg_desc = desc_info->sg_desc;
> + struct txq_sg_elem *elem = sg_desc->elems;
> + struct tx_stats *stats = q_to_tx_stats(q);
> + struct txq_desc *desc = desc_info->desc;
> + struct device *dev = q->lif->ionic->dev;
> + struct sk_buff *skb = cb_arg;
> + u8 opcode, flags, nsge;
> + u16 queue_index;
> + unsigned int i;
> + u64 addr;
> +
> + decode_txq_desc_cmd(le64_to_cpu(desc->cmd),
> + &opcode, &flags, &nsge, &addr);
> +
> + dma_unmap_page(dev, (dma_addr_t)addr,
> + le16_to_cpu(desc->len), DMA_TO_DEVICE);
> + for (i = 0; i < nsge; i++, elem++)
> + dma_unmap_page(dev, (dma_addr_t)le64_to_cpu(elem-
> >addr),
> + le16_to_cpu(elem->len), DMA_TO_DEVICE);
> +
> + if (skb) {
when skb is null and queue is stopped what do you do ?
also you should do this at the end of napi cycle.. and not per packet.
> + queue_index = skb_get_queue_mapping(skb);
> + if (unlikely(__netif_subqueue_stopped(q->lif->netdev,
> + queue_index))) {
> + netif_wake_subqueue(q->lif->netdev,
> queue_index);
> + q->wake++;
> + }
> + dev_kfree_skb_any(skb);
> + stats->clean++;
> + }
> +}
> +
> +static void ionic_tx_tcp_inner_pseudo_csum(struct sk_buff *skb)
> +{
> + skb_cow_head(skb, 0);
> +
> + if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
> + inner_ip_hdr(skb)->check = 0;
> + inner_tcp_hdr(skb)->check =
> + ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr,
> + inner_ip_hdr(skb)->daddr,
> + 0, IPPROTO_TCP, 0);
> + } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
> + inner_tcp_hdr(skb)->check =
> + ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr,
> + &inner_ipv6_hdr(skb)->daddr,
> + 0, IPPROTO_TCP, 0);
> + }
> +}
> +
> +static void ionic_tx_tcp_pseudo_csum(struct sk_buff *skb)
> +{
> + skb_cow_head(skb, 0);
> +
> + if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
> + ip_hdr(skb)->check = 0;
> + tcp_hdr(skb)->check =
> + ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
> + ip_hdr(skb)->daddr,
> + 0, IPPROTO_TCP, 0);
> + } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) {
> + tcp_hdr(skb)->check =
> + ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
> + &ipv6_hdr(skb)->daddr,
> + 0, IPPROTO_TCP, 0);
> + }
> +}
> +
> +static void ionic_tx_tso_post(struct queue *q, struct txq_desc
> *desc,
> + struct sk_buff *skb,
> + dma_addr_t addr, u8 nsge, u16 len,
> + unsigned int hdrlen, unsigned int mss,
> + bool outer_csum,
> + u16 vlan_tci, bool has_vlan,
> + bool start, bool done)
> +{
> + u8 flags = 0;
> + u64 cmd;
> +
> + flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
> + flags |= outer_csum ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
> + flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0;
> + flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0;
> +
> + cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO, flags,
> nsge, addr);
> + desc->cmd = cpu_to_le64(cmd);
> + desc->len = cpu_to_le16(len);
> + desc->vlan_tci = cpu_to_le16(vlan_tci);
> + desc->hdr_len = cpu_to_le16(hdrlen);
> + desc->mss = cpu_to_le16(mss);
> +
> + if (done) {
> + skb_tx_timestamp(skb);
> + ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean,
> skb);
> + } else {
> + ionic_txq_post(q, false, ionic_tx_clean, NULL);
> + }
> +}
> +
> +static struct txq_desc *ionic_tx_tso_next(struct queue *q,
> + struct txq_sg_elem **elem)
> +{
> + struct txq_sg_desc *sg_desc = q->head->sg_desc;
> + struct txq_desc *desc = q->head->desc;
> +
> + *elem = sg_desc->elems;
> + return desc;
> +}
> +
> +static int ionic_tx_tso(struct queue *q, struct sk_buff *skb)
> +{
> + struct tx_stats *stats = q_to_tx_stats(q);
> + struct desc_info *abort = q->head;
> + struct desc_info *rewind = abort;
> + unsigned int frag_left = 0;
> + struct txq_sg_elem *elem;
> + unsigned int offset = 0;
> + unsigned int len_left;
> + struct txq_desc *desc;
> + dma_addr_t desc_addr;
> + unsigned int hdrlen;
> + unsigned int nfrags;
> + unsigned int seglen;
> + u64 total_bytes = 0;
> + u64 total_pkts = 0;
> + unsigned int left;
> + unsigned int len;
> + unsigned int mss;
> + skb_frag_t *frag;
> + bool start, done;
> + bool outer_csum;
> + bool has_vlan;
> + u16 desc_len;
> + u8 desc_nsge;
> + u16 vlan_tci;
> + bool encap;
> +
> + mss = skb_shinfo(skb)->gso_size;
> + nfrags = skb_shinfo(skb)->nr_frags;
> + len_left = skb->len - skb_headlen(skb);
> + outer_csum = (skb_shinfo(skb)->gso_type & SKB_GSO_GRE_CSUM) ||
> + (skb_shinfo(skb)->gso_type &
> SKB_GSO_UDP_TUNNEL_CSUM);
> + has_vlan = !!skb_vlan_tag_present(skb);
> + vlan_tci = skb_vlan_tag_get(skb);
> + encap = skb->encapsulation;
> +
> + /* Preload inner-most TCP csum field with IP pseudo hdr
> + * calculated with IP length set to zero. HW will later
> + * add in length to each TCP segment resulting from the TSO.
> + */
> +
> + if (encap)
> + ionic_tx_tcp_inner_pseudo_csum(skb);
> + else
> + ionic_tx_tcp_pseudo_csum(skb);
> +
> + if (encap)
> + hdrlen = skb_inner_transport_header(skb) - skb->data +
> + inner_tcp_hdrlen(skb);
> + else
> + hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
> +
> + seglen = hdrlen + mss;
> + left = skb_headlen(skb);
> +
> + desc = ionic_tx_tso_next(q, &elem);
> + start = true;
> +
> + /* Chop skb->data up into desc segments */
> +
> + while (left > 0) {
> + len = min(seglen, left);
> + frag_left = seglen - len;
> + desc_addr = ionic_tx_map_single(q, skb->data + offset,
> len);
> + if (!desc_addr)
> + goto err_out_abort;
> + desc_len = len;
> + desc_nsge = 0;
> + left -= len;
> + offset += len;
> + if (nfrags > 0 && frag_left > 0)
> + continue;
> + done = (nfrags == 0 && left == 0);
> + ionic_tx_tso_post(q, desc, skb,
> + desc_addr, desc_nsge, desc_len,
> + hdrlen, mss,
> + outer_csum,
> + vlan_tci, has_vlan,
> + start, done);
> + total_pkts++;
> + total_bytes += start ? len : len + hdrlen;
> + desc = ionic_tx_tso_next(q, &elem);
> + start = false;
> + seglen = mss;
> + }
> +
> + /* Chop skb frags into desc segments */
> +
> + for (frag = skb_shinfo(skb)->frags; len_left; frag++) {
> + offset = 0;
> + left = skb_frag_size(frag);
> + len_left -= left;
> + nfrags--;
> + stats->frags++;
> +
> + while (left > 0) {
> + if (frag_left > 0) {
> + len = min(frag_left, left);
> + frag_left -= len;
> + elem->addr =
> + cpu_to_le64(ionic_tx_map_frag(q,
> frag,
> + offse
> t, len));
> + if (!elem->addr)
> + goto err_out_abort;
> + elem->len = cpu_to_le16(len);
> + elem++;
> + desc_nsge++;
> + left -= len;
> + offset += len;
> + if (nfrags > 0 && frag_left > 0)
> + continue;
> + done = (nfrags == 0 && left == 0);
> + ionic_tx_tso_post(q, desc, skb,
> desc_addr,
> + desc_nsge, desc_len,
> + hdrlen, mss,
> outer_csum,
> + vlan_tci, has_vlan,
> + start, done);
> + total_pkts++;
> + total_bytes += start ? len : len +
> hdrlen;
> + desc = ionic_tx_tso_next(q, &elem);
> + start = false;
> + } else {
> + len = min(mss, left);
> + frag_left = mss - len;
> + desc_addr = ionic_tx_map_frag(q, frag,
> + offset,
> len);
> + if (!desc_addr)
> + goto err_out_abort;
> + desc_len = len;
> + desc_nsge = 0;
> + left -= len;
> + offset += len;
> + if (nfrags > 0 && frag_left > 0)
> + continue;
> + done = (nfrags == 0 && left == 0);
> + ionic_tx_tso_post(q, desc, skb,
> desc_addr,
> + desc_nsge, desc_len,
> + hdrlen, mss,
> outer_csum,
> + vlan_tci, has_vlan,
> + start, done);
> + total_pkts++;
> + total_bytes += start ? len : len +
> hdrlen;
> + desc = ionic_tx_tso_next(q, &elem);
> + start = false;
> + }
> + }
> + }
> +
> + stats->pkts += total_pkts;
> + stats->bytes += total_bytes;
> + stats->tso++;
> +
> + return 0;
> +
> +err_out_abort:
> + while (rewind->desc != q->head->desc) {
> + ionic_tx_clean(q, rewind, NULL, NULL);
> + rewind = rewind->next;
> + }
> + q->head = abort;
> +
> + return -ENOMEM;
> +}
> +
> +static int ionic_tx_calc_csum(struct queue *q, struct sk_buff *skb)
> +{
> + struct tx_stats *stats = q_to_tx_stats(q);
> + struct txq_desc *desc = q->head->desc;
> + dma_addr_t addr;
> + bool has_vlan;
> + u8 flags = 0;
> + bool encap;
> + u64 cmd;
> +
> + has_vlan = !!skb_vlan_tag_present(skb);
> + encap = skb->encapsulation;
> +
> + addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb));
> + if (!addr)
> + return -ENOMEM;
> +
> + flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
> + flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
> +
> + cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL,
> + flags, skb_shinfo(skb)->nr_frags,
> addr);
> + desc->cmd = cpu_to_le64(cmd);
> + desc->len = cpu_to_le16(skb_headlen(skb));
> + desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
> + desc->csum_start = cpu_to_le16(skb_checksum_start_offset(skb));
> + desc->csum_offset = cpu_to_le16(skb->csum_offset);
> +
> + if (skb->csum_not_inet)
> + stats->crc32_csum++;
> + else
> + stats->csum++;
> +
> + return 0;
> +}
> +
> +static int ionic_tx_calc_no_csum(struct queue *q, struct sk_buff
> *skb)
> +{
> + struct tx_stats *stats = q_to_tx_stats(q);
> + struct txq_desc *desc = q->head->desc;
> + dma_addr_t addr;
> + bool has_vlan;
> + u8 flags = 0;
> + bool encap;
> + u64 cmd;
> +
> + has_vlan = !!skb_vlan_tag_present(skb);
> + encap = skb->encapsulation;
> +
> + addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb));
> + if (!addr)
> + return -ENOMEM;
> +
> + flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0;
> + flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0;
> +
> + cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_NONE,
> + flags, skb_shinfo(skb)->nr_frags,
> addr);
> + desc->cmd = cpu_to_le64(cmd);
> + desc->len = cpu_to_le16(skb_headlen(skb));
> + desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb));
> +
> + stats->no_csum++;
> +
> + return 0;
> +}
> +
> +static int ionic_tx_skb_frags(struct queue *q, struct sk_buff *skb)
> +{
> + unsigned int len_left = skb->len - skb_headlen(skb);
> + struct txq_sg_desc *sg_desc = q->head->sg_desc;
> + struct txq_sg_elem *elem = sg_desc->elems;
> + struct tx_stats *stats = q_to_tx_stats(q);
> + dma_addr_t dma_addr;
> + skb_frag_t *frag;
> + u16 len;
> +
> + for (frag = skb_shinfo(skb)->frags; len_left; frag++, elem++) {
> + len = skb_frag_size(frag);
> + elem->len = cpu_to_le16(len);
> + dma_addr = ionic_tx_map_frag(q, frag, 0, len);
> + if (!dma_addr)
> + return -ENOMEM;
> + elem->addr = cpu_to_le64(dma_addr);
> + len_left -= len;
> + stats->frags++;
> + }
> +
> + return 0;
> +}
> +
> +static int ionic_tx(struct queue *q, struct sk_buff *skb)
> +{
> + struct tx_stats *stats = q_to_tx_stats(q);
> + int err;
> +
> + if (skb->ip_summed == CHECKSUM_PARTIAL)
> + err = ionic_tx_calc_csum(q, skb);
> + else
> + err = ionic_tx_calc_no_csum(q, skb);
> + if (err)
> + return err;
> +
> + err = ionic_tx_skb_frags(q, skb);
> + if (err)
> + return err;
> +
> + skb_tx_timestamp(skb);
> + stats->pkts++;
> + stats->bytes += skb->len;
> +
> + ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb);
> +
> + return 0;
> +}
> +
> +static int ionic_tx_descs_needed(struct queue *q, struct sk_buff
> *skb)
> +{
> + struct tx_stats *stats = q_to_tx_stats(q);
> + int err;
> +
> + /* If TSO, need roundup(skb->len/mss) descs */
> + if (skb_is_gso(skb))
> + return (skb->len / skb_shinfo(skb)->gso_size) + 1;
> +
> + /* If non-TSO, just need 1 desc and nr_frags sg elems */
> + if (skb_shinfo(skb)->nr_frags <= IONIC_TX_MAX_SG_ELEMS)
> + return 1;
> +
> + /* Too many frags, so linearize */
> + err = skb_linearize(skb);
> + if (err)
> + return err;
> +
> + stats->linearize++;
> +
> + /* Need 1 desc and zero sg elems */
> + return 1;
> +}
> +
> +netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device
> *netdev)
> +{
> + u16 queue_index = skb_get_queue_mapping(skb);
> + struct lif *lif = netdev_priv(netdev);
> + struct queue *q;
> + int ndescs;
> + int err;
> +
> + if (unlikely(!test_bit(LIF_UP, lif->state))) {
> + dev_kfree_skb(skb);
> + return NETDEV_TX_OK;
> + }
> +
> + if (likely(lif_to_txqcq(lif, queue_index)))
> + q = lif_to_txq(lif, queue_index);
> + else
> + q = lif_to_txq(lif, 0);
> +
> + ndescs = ionic_tx_descs_needed(q, skb);
> + if (ndescs < 0)
> + goto err_out_drop;
> +
> + if (!ionic_q_has_space(q, ndescs)) {
> + netif_stop_subqueue(netdev, queue_index);
> + q->stop++;
> +
> + /* Might race with ionic_tx_clean, check again */
> + smp_rmb();
> + if (ionic_q_has_space(q, ndescs)) {
> + netif_wake_subqueue(netdev, queue_index);
> + q->wake++;
> + } else {
> + return NETDEV_TX_BUSY;
> + }
> + }
> +
You are missing netdev_tx_sent_queue() here
and corresponding netdev_tx_completed_queue() on completion.
> + if (skb_is_gso(skb))
> + err = ionic_tx_tso(q, skb);
> + else
> + err = ionic_tx(q, skb);
> +
> + if (err)
> + goto err_out_drop;
> +
> + return NETDEV_TX_OK;
> +
> +err_out_drop:
> + netif_stop_subqueue(netdev, queue_index);
> + q->stop++;
> + q->drop++;
> + dev_kfree_skb(skb);
> + return NETDEV_TX_OK;
> +}
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_txrx.h
> b/drivers/net/ethernet/pensando/ionic/ionic_txrx.h
> new file mode 100644
> index 000000000000..2391a0eec65a
> --- /dev/null
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_txrx.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
> +
> +#ifndef _IONIC_TXRX_H_
> +#define _IONIC_TXRX_H_
> +
> +void ionic_rx_flush(struct cq *cq);
> +void ionic_tx_flush(struct cq *cq);
> +
> +void ionic_rx_fill(struct queue *q);
> +void ionic_rx_empty(struct queue *q);
> +int ionic_rx_napi(struct napi_struct *napi, int budget);
> +netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device
> *netdev);
> +
> +#endif /* _IONIC_TXRX_H_ */
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 14/19] ionic: Add Tx and Rx handling
2019-07-25 23:48 ` Saeed Mahameed
@ 2019-08-09 22:27 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-08-09 22:27 UTC (permalink / raw)
To: Saeed Mahameed, netdev, davem
On 7/25/19 4:48 PM, Saeed Mahameed wrote:
> On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
>> Add both the Tx and Rx queue setup and handling. The related
>> stats display comes later. Instead of using the generic napi
>> routines used by the slow-path commands, the Tx and Rx paths
>> are simplified and inlined in one file in order to get better
>> compiler optimizations.
>>
>> Signed-off-by: Shannon Nelson<snelson@pensando.io>
>> ---
>> drivers/net/ethernet/pensando/ionic/Makefile | 2 +-
>> .../net/ethernet/pensando/ionic/ionic_lif.c | 387 ++++++++
>> .../net/ethernet/pensando/ionic/ionic_lif.h | 52 ++
>> .../net/ethernet/pensando/ionic/ionic_txrx.c | 879
>> ++++++++++++++++++
>> .../net/ethernet/pensando/ionic/ionic_txrx.h | 15 +
>> 5 files changed, 1334 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_txrx.c
>> create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_txrx.h
>>
>> diff --git a/drivers/net/ethernet/pensando/ionic/Makefile
>> b/drivers/net/ethernet/pensando/ionic/Makefile
>> index 9b19bf57a489..0e2dc53f08d4 100644
>> --- a/drivers/net/ethernet/pensando/ionic/Makefile
>> +++ b/drivers/net/ethernet/pensando/ionic/Makefile
>> @@ -4,4 +4,4 @@
>> obj-$(CONFIG_IONIC) := ionic.o
>>
>> ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_ethtool.o
>> \
>> - ionic_lif.o ionic_rx_filter.o ionic_debugfs.o
>> + ionic_lif.o ionic_rx_filter.o ionic_txrx.o ionic_debugfs.o
>> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
>> b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
>> index 2bd8ce61c4a0..40d3b1cb362a 100644
>> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
>> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
>> @@ -10,6 +10,7 @@
>> #include "ionic.h"
>> #include "ionic_bus.h"
>> #include "ionic_lif.h"
>> +#include "ionic_txrx.h"
>> #include "ionic_ethtool.h"
>> #include "ionic_debugfs.h"
>>
>> @@ -18,6 +19,13 @@ static int ionic_lif_addr_add(struct lif *lif,
>> const u8 *addr);
>> static int ionic_lif_addr_del(struct lif *lif, const u8 *addr);
>> static void ionic_link_status_check(struct lif *lif);
>>
>> +static int ionic_lif_stop(struct lif *lif);
>> +static int ionic_txrx_alloc(struct lif *lif);
>> +static int ionic_txrx_init(struct lif *lif);
>> +static void ionic_qcq_free(struct lif *lif, struct qcq *qcq);
>> +static int ionic_lif_txqs_init(struct lif *lif);
>> +static int ionic_lif_rxqs_init(struct lif *lif);
>> +static void ionic_lif_qcq_deinit(struct lif *lif, struct qcq *qcq);
>> static int ionic_set_nic_features(struct lif *lif, netdev_features_t
>> features);
>> static int ionic_notifyq_clean(struct lif *lif, int budget);
>>
>> @@ -66,12 +74,96 @@ static void ionic_lif_deferred_enqueue(struct
>> ionic_deferred *def,
>> schedule_work(&def->work);
>> }
> Bottom up or top down ? your current design is very mixed and I had to
> to scroll down and up too often just to understand what a function is
> doing, i strongly suggest to pick an use one approach.
>
> [1]
> https://en.wikipedia.org/wiki/Top-down_and_bottom-up_design#Programming
Hi Saeed,
Sorry it has taken me so long to address the comments you had on this
patch: I've been contemplating them while working some internal issues.
Part of my hesitance is also because, while correct, these are
suggesting some significant rework and juggling of stable code. I've
been aware of these issues since I inherited the code, and have been
addressing them over time while trying to keep on top of stability, and
was planning to continue doing so. It sounds like I need to evolve the
driver a little further before the next patchset version. I think I'll
have time in the next week to do this, so I'm hoping to have a new
patchset out in another week or so.
Thanks for the inputs,
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 15/19] ionic: Add netdev-event handling
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (13 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 14/19] ionic: Add Tx and Rx handling Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-25 23:55 ` Saeed Mahameed
2019-07-30 23:39 ` Stephen Hemminger
2019-07-22 21:40 ` [PATCH v4 net-next 16/19] ionic: Add driver stats Shannon Nelson
` (3 subsequent siblings)
18 siblings, 2 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
When the netdev gets a new name from userland, pass that name
down to the NIC for internal tracking.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/ionic.h | 2 +
.../net/ethernet/pensando/ionic/ionic_lif.c | 65 +++++++++++++++++++
2 files changed, 67 insertions(+)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
index d7eee79b2a10..9b720187b549 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -42,6 +42,8 @@ struct ionic {
DECLARE_BITMAP(lifbits, IONIC_LIFS_MAX);
unsigned int nintrs;
DECLARE_BITMAP(intrs, INTR_CTRL_REGS_MAX);
+ struct work_struct nb_work;
+ struct notifier_block nb;
};
struct ionic_admin_ctx {
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index 40d3b1cb362a..9e032d813269 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -1954,10 +1954,69 @@ int ionic_lifs_init(struct ionic *ionic)
return 0;
}
+static void ionic_lif_notify_work(struct work_struct *ws)
+{
+}
+
+static void ionic_lif_set_netdev_info(struct lif *lif)
+{
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.lif_setattr = {
+ .opcode = CMD_OPCODE_LIF_SETATTR,
+ .index = cpu_to_le16(lif->index),
+ .attr = IONIC_LIF_ATTR_NAME,
+ },
+ };
+
+ strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name,
+ sizeof(ctx.cmd.lif_setattr.name));
+
+ dev_info(lif->ionic->dev, "NETDEV_CHANGENAME %s %s\n",
+ lif->name, ctx.cmd.lif_setattr.name);
+
+ ionic_adminq_post_wait(lif, &ctx);
+}
+
+static struct lif *ionic_netdev_lif(struct net_device *netdev)
+{
+ if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit)
+ return NULL;
+
+ return netdev_priv(netdev);
+}
+
+static int ionic_lif_notify(struct notifier_block *nb,
+ unsigned long event, void *info)
+{
+ struct net_device *ndev = netdev_notifier_info_to_dev(info);
+ struct ionic *ionic = container_of(nb, struct ionic, nb);
+ struct lif *lif = ionic_netdev_lif(ndev);
+
+ if (!lif || lif->ionic != ionic)
+ return NOTIFY_DONE;
+
+ switch (event) {
+ case NETDEV_CHANGENAME:
+ ionic_lif_set_netdev_info(lif);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
int ionic_lifs_register(struct ionic *ionic)
{
int err;
+ INIT_WORK(&ionic->nb_work, ionic_lif_notify_work);
+
+ ionic->nb.notifier_call = ionic_lif_notify;
+
+ err = register_netdevice_notifier(&ionic->nb);
+ if (err)
+ ionic->nb.notifier_call = NULL;
+
/* only register LIF0 for now */
err = register_netdev(ionic->master_lif->netdev);
if (err) {
@@ -1973,6 +2032,12 @@ int ionic_lifs_register(struct ionic *ionic)
void ionic_lifs_unregister(struct ionic *ionic)
{
+ if (ionic->nb.notifier_call) {
+ unregister_netdevice_notifier(&ionic->nb);
+ cancel_work_sync(&ionic->nb_work);
+ ionic->nb.notifier_call = NULL;
+ }
+
/* There is only one lif ever registered in the
* current model, so don't bother searching the
* ionic->lif for candidates to unregister
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 15/19] ionic: Add netdev-event handling
2019-07-22 21:40 ` [PATCH v4 net-next 15/19] ionic: Add netdev-event handling Shannon Nelson
@ 2019-07-25 23:55 ` Saeed Mahameed
2019-07-30 22:53 ` Shannon Nelson
2019-07-30 23:39 ` Stephen Hemminger
1 sibling, 1 reply; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-25 23:55 UTC (permalink / raw)
To: snelson, netdev, davem
On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> When the netdev gets a new name from userland, pass that name
> down to the NIC for internal tracking.
>
Just out of curiosity, why your NIC internal device/firmware need to
keep tracking of the netdev name ?
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 15/19] ionic: Add netdev-event handling
2019-07-25 23:55 ` Saeed Mahameed
@ 2019-07-30 22:53 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-30 22:53 UTC (permalink / raw)
To: Saeed Mahameed, netdev, davem
On 7/25/19 4:55 PM, Saeed Mahameed wrote:
> On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
>> When the netdev gets a new name from userland, pass that name
>> down to the NIC for internal tracking.
>>
> Just out of curiosity, why your NIC internal device/firmware need to
> keep tracking of the netdev name ?
>
>
It is helpful in a debugging method inside the NIC firmware.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* Re: [PATCH v4 net-next 15/19] ionic: Add netdev-event handling
2019-07-22 21:40 ` [PATCH v4 net-next 15/19] ionic: Add netdev-event handling Shannon Nelson
2019-07-25 23:55 ` Saeed Mahameed
@ 2019-07-30 23:39 ` Stephen Hemminger
2019-07-31 1:10 ` Shannon Nelson
1 sibling, 1 reply; 69+ messages in thread
From: Stephen Hemminger @ 2019-07-30 23:39 UTC (permalink / raw)
To: Shannon Nelson; +Cc: netdev, davem
On Mon, 22 Jul 2019 14:40:19 -0700
Shannon Nelson <snelson@pensando.io> wrote:
> +
> +static void ionic_lif_set_netdev_info(struct lif *lif)
> +{
> + struct ionic_admin_ctx ctx = {
> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
> + .cmd.lif_setattr = {
> + .opcode = CMD_OPCODE_LIF_SETATTR,
> + .index = cpu_to_le16(lif->index),
> + .attr = IONIC_LIF_ATTR_NAME,
> + },
> + };
> +
> + strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name,
> + sizeof(ctx.cmd.lif_setattr.name));
> +
> + dev_info(lif->ionic->dev, "NETDEV_CHANGENAME %s %s\n",
> + lif->name, ctx.cmd.lif_setattr.name);
> +
There is already a kernel message for this. Repeating the same thing in the
driver is redundant.
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 15/19] ionic: Add netdev-event handling
2019-07-30 23:39 ` Stephen Hemminger
@ 2019-07-31 1:10 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-31 1:10 UTC (permalink / raw)
To: Stephen Hemminger; +Cc: netdev, davem
On 7/30/19 4:39 PM, Stephen Hemminger wrote:
> On Mon, 22 Jul 2019 14:40:19 -0700
> Shannon Nelson <snelson@pensando.io> wrote:
>
>> +
>> +static void ionic_lif_set_netdev_info(struct lif *lif)
>> +{
>> + struct ionic_admin_ctx ctx = {
>> + .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
>> + .cmd.lif_setattr = {
>> + .opcode = CMD_OPCODE_LIF_SETATTR,
>> + .index = cpu_to_le16(lif->index),
>> + .attr = IONIC_LIF_ATTR_NAME,
>> + },
>> + };
>> +
>> + strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name,
>> + sizeof(ctx.cmd.lif_setattr.name));
>> +
>> + dev_info(lif->ionic->dev, "NETDEV_CHANGENAME %s %s\n",
>> + lif->name, ctx.cmd.lif_setattr.name);
>> +
> There is already a kernel message for this. Repeating the same thing in the
> driver is redundant.
True, except for the lif name information. But since that really is
debugging information, and I was getting tired of seeing those redundant
messages, I was planning to remove them soon anyway. Thanks for the
extra nudge.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 16/19] ionic: Add driver stats
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (14 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 15/19] ionic: Add netdev-event handling Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-22 21:40 ` [PATCH v4 net-next 17/19] ionic: Add RSS support Shannon Nelson
` (2 subsequent siblings)
18 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Add in the detailed statistics for ethtool -S that the driver
keeps as it processes packets. Display of the additional
debug statistics can be enabled through the ethtool priv-flags
feature.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/Makefile | 3 +-
.../ethernet/pensando/ionic/ionic_ethtool.c | 101 ++++++
.../net/ethernet/pensando/ionic/ionic_lif.h | 14 +
.../net/ethernet/pensando/ionic/ionic_stats.c | 333 ++++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_stats.h | 53 +++
5 files changed, 503 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_stats.c
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_stats.h
diff --git a/drivers/net/ethernet/pensando/ionic/Makefile b/drivers/net/ethernet/pensando/ionic/Makefile
index 0e2dc53f08d4..4f3cfbf36c23 100644
--- a/drivers/net/ethernet/pensando/ionic/Makefile
+++ b/drivers/net/ethernet/pensando/ionic/Makefile
@@ -4,4 +4,5 @@
obj-$(CONFIG_IONIC) := ionic.o
ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_ethtool.o \
- ionic_lif.o ionic_rx_filter.o ionic_txrx.o ionic_debugfs.o
+ ionic_lif.o ionic_rx_filter.o ionic_txrx.o ionic_debugfs.o \
+ ionic_stats.o
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
index f7899be547c3..d7503a3dafb7 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
@@ -8,6 +8,76 @@
#include "ionic_bus.h"
#include "ionic_lif.h"
#include "ionic_ethtool.h"
+#include "ionic_stats.h"
+
+static const char ionic_priv_flags_strings[][ETH_GSTRING_LEN] = {
+#define PRIV_F_SW_DBG_STATS BIT(0)
+ "sw-dbg-stats",
+};
+#define PRIV_FLAGS_COUNT ARRAY_SIZE(ionic_priv_flags_strings)
+
+static void ionic_get_stats_strings(struct lif *lif, u8 *buf)
+{
+ u32 i;
+
+ for (i = 0; i < ionic_num_stats_grps; i++)
+ ionic_stats_groups[i].get_strings(lif, &buf);
+}
+
+static void ionic_get_stats(struct net_device *netdev,
+ struct ethtool_stats *stats, u64 *buf)
+{
+ struct lif *lif;
+ u32 i;
+
+ lif = netdev_priv(netdev);
+
+ memset(buf, 0, stats->n_stats * sizeof(*buf));
+ for (i = 0; i < ionic_num_stats_grps; i++)
+ ionic_stats_groups[i].get_values(lif, &buf);
+}
+
+static int ionic_get_stats_count(struct lif *lif)
+{
+ int i, num_stats = 0;
+
+ for (i = 0; i < ionic_num_stats_grps; i++)
+ num_stats += ionic_stats_groups[i].get_count(lif);
+
+ return num_stats;
+}
+
+static int ionic_get_sset_count(struct net_device *netdev, int sset)
+{
+ struct lif *lif = netdev_priv(netdev);
+ int count = 0;
+
+ switch (sset) {
+ case ETH_SS_STATS:
+ count = ionic_get_stats_count(lif);
+ break;
+ case ETH_SS_PRIV_FLAGS:
+ count = PRIV_FLAGS_COUNT;
+ break;
+ }
+ return count;
+}
+
+static void ionic_get_strings(struct net_device *netdev,
+ u32 sset, u8 *buf)
+{
+ struct lif *lif = netdev_priv(netdev);
+
+ switch (sset) {
+ case ETH_SS_STATS:
+ ionic_get_stats_strings(lif, buf);
+ break;
+ case ETH_SS_PRIV_FLAGS:
+ memcpy(buf, ionic_priv_flags_strings,
+ PRIV_FLAGS_COUNT * ETH_GSTRING_LEN);
+ break;
+ }
+}
static void ionic_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *drvinfo)
@@ -398,6 +468,32 @@ static int ionic_set_channels(struct net_device *netdev,
return 0;
}
+static u32 ionic_get_priv_flags(struct net_device *netdev)
+{
+ struct lif *lif = netdev_priv(netdev);
+ u32 priv_flags = 0;
+
+ if (test_bit(LIF_SW_DEBUG_STATS, lif->state))
+ priv_flags |= PRIV_F_SW_DBG_STATS;
+
+ return priv_flags;
+}
+
+static int ionic_set_priv_flags(struct net_device *netdev, u32 priv_flags)
+{
+ struct lif *lif = netdev_priv(netdev);
+ u32 flags = lif->flags;
+
+ clear_bit(LIF_SW_DEBUG_STATS, lif->state);
+ if (priv_flags & PRIV_F_SW_DBG_STATS)
+ set_bit(LIF_SW_DEBUG_STATS, lif->state);
+
+ if (flags != lif->flags)
+ lif->flags = flags;
+
+ return 0;
+}
+
static int ionic_get_module_info(struct net_device *netdev,
struct ethtool_modinfo *modinfo)
@@ -481,6 +577,11 @@ static const struct ethtool_ops ionic_ethtool_ops = {
.set_ringparam = ionic_set_ringparam,
.get_channels = ionic_get_channels,
.set_channels = ionic_set_channels,
+ .get_strings = ionic_get_strings,
+ .get_ethtool_stats = ionic_get_stats,
+ .get_sset_count = ionic_get_sset_count,
+ .get_priv_flags = ionic_get_priv_flags,
+ .set_priv_flags = ionic_set_priv_flags,
.get_module_info = ionic_get_module_info,
.get_module_eeprom = ionic_get_module_eeprom,
.get_pauseparam = ionic_get_pauseparam,
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index 88d5bf8f58a1..f93bfa2b4393 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -108,8 +108,22 @@ struct ionic_deferred {
struct work_struct work;
};
+struct lif_sw_stats {
+ u64 tx_packets;
+ u64 tx_bytes;
+ u64 rx_packets;
+ u64 rx_bytes;
+ u64 tx_tso;
+ u64 tx_no_csum;
+ u64 tx_csum;
+ u64 rx_csum_none;
+ u64 rx_csum_complete;
+ u64 rx_csum_error;
+};
+
enum lif_state_flags {
LIF_INITED,
+ LIF_SW_DEBUG_STATS,
LIF_UP,
LIF_LINK_CHECK_NEEDED,
LIF_QUEUE_RESET,
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_stats.c b/drivers/net/ethernet/pensando/ionic/ionic_stats.c
new file mode 100644
index 000000000000..978a9f89804a
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_stats.c
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/netdevice.h>
+
+#include "ionic.h"
+#include "ionic_lif.h"
+#include "ionic_stats.h"
+
+static const struct ionic_stat_desc ionic_lif_stats_desc[] = {
+ IONIC_LIF_STAT_DESC(tx_packets),
+ IONIC_LIF_STAT_DESC(tx_bytes),
+ IONIC_LIF_STAT_DESC(rx_packets),
+ IONIC_LIF_STAT_DESC(rx_bytes),
+ IONIC_LIF_STAT_DESC(tx_tso),
+ IONIC_LIF_STAT_DESC(tx_no_csum),
+ IONIC_LIF_STAT_DESC(tx_csum),
+ IONIC_LIF_STAT_DESC(rx_csum_none),
+ IONIC_LIF_STAT_DESC(rx_csum_complete),
+ IONIC_LIF_STAT_DESC(rx_csum_error),
+};
+
+static const struct ionic_stat_desc ionic_tx_stats_desc[] = {
+ IONIC_TX_STAT_DESC(pkts),
+ IONIC_TX_STAT_DESC(bytes),
+ IONIC_TX_STAT_DESC(clean),
+ IONIC_TX_STAT_DESC(dma_map_err),
+ IONIC_TX_STAT_DESC(linearize),
+ IONIC_TX_STAT_DESC(frags),
+};
+
+static const struct ionic_stat_desc ionic_rx_stats_desc[] = {
+ IONIC_RX_STAT_DESC(pkts),
+ IONIC_RX_STAT_DESC(bytes),
+ IONIC_RX_STAT_DESC(dma_map_err),
+ IONIC_RX_STAT_DESC(alloc_err),
+ IONIC_RX_STAT_DESC(csum_none),
+ IONIC_RX_STAT_DESC(csum_complete),
+ IONIC_RX_STAT_DESC(csum_error),
+};
+
+static const struct ionic_stat_desc ionic_txq_stats_desc[] = {
+ IONIC_TX_Q_STAT_DESC(stop),
+ IONIC_TX_Q_STAT_DESC(wake),
+ IONIC_TX_Q_STAT_DESC(drop),
+ IONIC_TX_Q_STAT_DESC(dbell_count),
+};
+
+static const struct ionic_stat_desc ionic_dbg_cq_stats_desc[] = {
+ IONIC_CQ_STAT_DESC(compl_count),
+};
+
+static const struct ionic_stat_desc ionic_dbg_intr_stats_desc[] = {
+ IONIC_INTR_STAT_DESC(rearm_count),
+};
+
+static const struct ionic_stat_desc ionic_dbg_napi_stats_desc[] = {
+ IONIC_NAPI_STAT_DESC(poll_count),
+};
+
+#define IONIC_NUM_LIF_STATS ARRAY_SIZE(ionic_lif_stats_desc)
+#define IONIC_NUM_TX_STATS ARRAY_SIZE(ionic_tx_stats_desc)
+#define IONIC_NUM_RX_STATS ARRAY_SIZE(ionic_rx_stats_desc)
+#define IONIC_NUM_TX_Q_STATS ARRAY_SIZE(ionic_txq_stats_desc)
+#define IONIC_NUM_DBG_CQ_STATS ARRAY_SIZE(ionic_dbg_cq_stats_desc)
+#define IONIC_NUM_DBG_INTR_STATS ARRAY_SIZE(ionic_dbg_intr_stats_desc)
+#define IONIC_NUM_DBG_NAPI_STATS ARRAY_SIZE(ionic_dbg_napi_stats_desc)
+
+#define MAX_Q(lif) ((lif)->netdev->real_num_tx_queues)
+
+static void ionic_get_lif_stats(struct lif *lif, struct lif_sw_stats *stats)
+{
+ struct tx_stats *tstats;
+ struct rx_stats *rstats;
+ struct qcq *txqcq;
+ struct qcq *rxqcq;
+ int q_num;
+
+ memset(stats, 0, sizeof(*stats));
+
+ for (q_num = 0; q_num < MAX_Q(lif); q_num++) {
+ txqcq = lif_to_txqcq(lif, q_num);
+ if (txqcq && txqcq->stats) {
+ tstats = &txqcq->stats->tx;
+ stats->tx_packets += tstats->pkts;
+ stats->tx_bytes += tstats->bytes;
+ stats->tx_tso += tstats->tso;
+ stats->tx_no_csum += tstats->no_csum;
+ stats->tx_csum += tstats->csum;
+ }
+
+ rxqcq = lif_to_rxqcq(lif, q_num);
+ if (rxqcq && rxqcq->stats) {
+ rstats = &rxqcq->stats->rx;
+ stats->rx_packets += rstats->pkts;
+ stats->rx_bytes += rstats->bytes;
+ stats->rx_csum_none += rstats->csum_none;
+ stats->rx_csum_complete += rstats->csum_complete;
+ stats->rx_csum_error += rstats->csum_error;
+ }
+ }
+}
+
+static u64 ionic_sw_stats_get_count(struct lif *lif)
+{
+ u64 total = 0;
+
+ /* lif stats */
+ total += IONIC_NUM_LIF_STATS;
+
+ /* tx stats */
+ total += MAX_Q(lif) * IONIC_NUM_TX_STATS;
+
+ /* rx stats */
+ total += MAX_Q(lif) * IONIC_NUM_RX_STATS;
+
+ if (test_bit(LIF_SW_DEBUG_STATS, lif->state)) {
+ /* tx debug stats */
+ total += MAX_Q(lif) * (IONIC_NUM_DBG_CQ_STATS +
+ IONIC_NUM_TX_Q_STATS +
+ IONIC_NUM_DBG_INTR_STATS +
+ IONIC_NUM_DBG_NAPI_STATS +
+ MAX_NUM_NAPI_CNTR +
+ MAX_NUM_SG_CNTR);
+
+ /* rx debug stats */
+ total += MAX_Q(lif) * (IONIC_NUM_DBG_CQ_STATS +
+ IONIC_NUM_DBG_INTR_STATS +
+ IONIC_NUM_DBG_NAPI_STATS +
+ MAX_NUM_NAPI_CNTR);
+ }
+
+ return total;
+}
+
+static void ionic_sw_stats_get_strings(struct lif *lif, u8 **buf)
+{
+ int i, q_num;
+
+ for (i = 0; i < IONIC_NUM_LIF_STATS; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN, ionic_lif_stats_desc[i].name);
+ *buf += ETH_GSTRING_LEN;
+ }
+ for (q_num = 0; q_num < MAX_Q(lif); q_num++) {
+ for (i = 0; i < IONIC_NUM_TX_STATS; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN, "tx_%d_%s",
+ q_num, ionic_tx_stats_desc[i].name);
+ *buf += ETH_GSTRING_LEN;
+ }
+
+ if (test_bit(LIF_SW_DEBUG_STATS, lif->state)) {
+ for (i = 0; i < IONIC_NUM_TX_Q_STATS; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "txq_%d_%s",
+ q_num,
+ ionic_txq_stats_desc[i].name);
+ *buf += ETH_GSTRING_LEN;
+ }
+ for (i = 0; i < IONIC_NUM_DBG_CQ_STATS; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "txq_%d_cq_%s",
+ q_num,
+ ionic_dbg_cq_stats_desc[i].name);
+ *buf += ETH_GSTRING_LEN;
+ }
+ for (i = 0; i < IONIC_NUM_DBG_INTR_STATS; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "txq_%d_intr_%s",
+ q_num,
+ ionic_dbg_intr_stats_desc[i].name);
+ *buf += ETH_GSTRING_LEN;
+ }
+ for (i = 0; i < IONIC_NUM_DBG_NAPI_STATS; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "txq_%d_napi_%s",
+ q_num,
+ ionic_dbg_napi_stats_desc[i].name);
+ *buf += ETH_GSTRING_LEN;
+ }
+ for (i = 0; i < MAX_NUM_NAPI_CNTR; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "txq_%d_napi_work_done_%d",
+ q_num, i);
+ *buf += ETH_GSTRING_LEN;
+ }
+ for (i = 0; i < MAX_NUM_SG_CNTR; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "txq_%d_sg_cntr_%d",
+ q_num, i);
+ *buf += ETH_GSTRING_LEN;
+ }
+ }
+ }
+ for (q_num = 0; q_num < MAX_Q(lif); q_num++) {
+ for (i = 0; i < IONIC_NUM_RX_STATS; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "rx_%d_%s",
+ q_num, ionic_rx_stats_desc[i].name);
+ *buf += ETH_GSTRING_LEN;
+ }
+
+ if (test_bit(LIF_SW_DEBUG_STATS, lif->state)) {
+ for (i = 0; i < IONIC_NUM_DBG_CQ_STATS; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "rxq_%d_cq_%s",
+ q_num,
+ ionic_dbg_cq_stats_desc[i].name);
+ *buf += ETH_GSTRING_LEN;
+ }
+ for (i = 0; i < IONIC_NUM_DBG_INTR_STATS; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "rxq_%d_intr_%s",
+ q_num,
+ ionic_dbg_intr_stats_desc[i].name);
+ *buf += ETH_GSTRING_LEN;
+ }
+ for (i = 0; i < IONIC_NUM_DBG_NAPI_STATS; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "rxq_%d_napi_%s",
+ q_num,
+ ionic_dbg_napi_stats_desc[i].name);
+ *buf += ETH_GSTRING_LEN;
+ }
+ for (i = 0; i < MAX_NUM_NAPI_CNTR; i++) {
+ snprintf(*buf, ETH_GSTRING_LEN,
+ "rxq_%d_napi_work_done_%d",
+ q_num, i);
+ *buf += ETH_GSTRING_LEN;
+ }
+ }
+ }
+}
+
+static void ionic_sw_stats_get_values(struct lif *lif, u64 **buf)
+{
+ struct lif_sw_stats lif_stats;
+ struct qcq *txqcq, *rxqcq;
+ int i, q_num;
+
+ ionic_get_lif_stats(lif, &lif_stats);
+
+ for (i = 0; i < IONIC_NUM_LIF_STATS; i++) {
+ **buf = IONIC_READ_STAT64(&lif_stats, &ionic_lif_stats_desc[i]);
+ (*buf)++;
+ }
+
+ for (q_num = 0; q_num < MAX_Q(lif); q_num++) {
+ txqcq = lif_to_txqcq(lif, q_num);
+
+ for (i = 0; i < IONIC_NUM_TX_STATS; i++) {
+ **buf = IONIC_READ_STAT64(&txqcq->stats->tx,
+ &ionic_tx_stats_desc[i]);
+ (*buf)++;
+ }
+
+ if (test_bit(LIF_SW_DEBUG_STATS, lif->state)) {
+ for (i = 0; i < IONIC_NUM_TX_Q_STATS; i++) {
+ **buf = IONIC_READ_STAT64(&txqcq->q,
+ &ionic_txq_stats_desc[i]);
+ (*buf)++;
+ }
+ for (i = 0; i < IONIC_NUM_DBG_CQ_STATS; i++) {
+ **buf = IONIC_READ_STAT64(&txqcq->cq,
+ &ionic_dbg_cq_stats_desc[i]);
+ (*buf)++;
+ }
+ for (i = 0; i < IONIC_NUM_DBG_INTR_STATS; i++) {
+ **buf = IONIC_READ_STAT64(&txqcq->intr,
+ &ionic_dbg_intr_stats_desc[i]);
+ (*buf)++;
+ }
+ for (i = 0; i < IONIC_NUM_DBG_NAPI_STATS; i++) {
+ **buf = IONIC_READ_STAT64(&txqcq->napi_stats,
+ &ionic_dbg_napi_stats_desc[i]);
+ (*buf)++;
+ }
+ for (i = 0; i < MAX_NUM_NAPI_CNTR; i++) {
+ **buf = txqcq->napi_stats.work_done_cntr[i];
+ (*buf)++;
+ }
+ for (i = 0; i < MAX_NUM_SG_CNTR; i++) {
+ **buf = txqcq->stats->tx.sg_cntr[i];
+ (*buf)++;
+ }
+ }
+ }
+
+ for (q_num = 0; q_num < MAX_Q(lif); q_num++) {
+ rxqcq = lif_to_rxqcq(lif, q_num);
+
+ for (i = 0; i < IONIC_NUM_RX_STATS; i++) {
+ **buf = IONIC_READ_STAT64(&rxqcq->stats->rx,
+ &ionic_rx_stats_desc[i]);
+ (*buf)++;
+ }
+
+ if (test_bit(LIF_SW_DEBUG_STATS, lif->state)) {
+ for (i = 0; i < IONIC_NUM_DBG_CQ_STATS; i++) {
+ **buf = IONIC_READ_STAT64(&rxqcq->cq,
+ &ionic_dbg_cq_stats_desc[i]);
+ (*buf)++;
+ }
+ for (i = 0; i < IONIC_NUM_DBG_INTR_STATS; i++) {
+ **buf = IONIC_READ_STAT64(&rxqcq->intr,
+ &ionic_dbg_intr_stats_desc[i]);
+ (*buf)++;
+ }
+ for (i = 0; i < IONIC_NUM_DBG_NAPI_STATS; i++) {
+ **buf = IONIC_READ_STAT64(&rxqcq->napi_stats,
+ &ionic_dbg_napi_stats_desc[i]);
+ (*buf)++;
+ }
+ for (i = 0; i < MAX_NUM_NAPI_CNTR; i++) {
+ **buf = rxqcq->napi_stats.work_done_cntr[i];
+ (*buf)++;
+ }
+ }
+ }
+}
+
+const struct ionic_stats_group_intf ionic_stats_groups[] = {
+ /* SW Stats group */
+ {
+ .get_strings = ionic_sw_stats_get_strings,
+ .get_values = ionic_sw_stats_get_values,
+ .get_count = ionic_sw_stats_get_count,
+ },
+ /* Add more stat groups here */
+};
+
+const int ionic_num_stats_grps = ARRAY_SIZE(ionic_stats_groups);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_stats.h b/drivers/net/ethernet/pensando/ionic/ionic_stats.h
new file mode 100644
index 000000000000..efa76694634e
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_stats.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#ifndef _IONIC_STATS_H_
+#define _IONIC_STATS_H_
+
+#define IONIC_STAT_TO_OFFSET(type, stat_name) (offsetof(type, stat_name))
+
+#define IONIC_STAT_DESC(type, stat_name) { \
+ .name = #stat_name, \
+ .offset = IONIC_STAT_TO_OFFSET(type, stat_name) \
+}
+
+#define IONIC_LIF_STAT_DESC(stat_name) \
+ IONIC_STAT_DESC(struct lif_sw_stats, stat_name)
+
+#define IONIC_TX_STAT_DESC(stat_name) \
+ IONIC_STAT_DESC(struct tx_stats, stat_name)
+
+#define IONIC_RX_STAT_DESC(stat_name) \
+ IONIC_STAT_DESC(struct rx_stats, stat_name)
+
+#define IONIC_TX_Q_STAT_DESC(stat_name) \
+ IONIC_STAT_DESC(struct queue, stat_name)
+
+#define IONIC_CQ_STAT_DESC(stat_name) \
+ IONIC_STAT_DESC(struct cq, stat_name)
+
+#define IONIC_INTR_STAT_DESC(stat_name) \
+ IONIC_STAT_DESC(struct intr, stat_name)
+
+#define IONIC_NAPI_STAT_DESC(stat_name) \
+ IONIC_STAT_DESC(struct napi_stats, stat_name)
+
+/* Interface structure for a particalar stats group */
+struct ionic_stats_group_intf {
+ void (*get_strings)(struct lif *lif, u8 **buf);
+ void (*get_values)(struct lif *lif, u64 **buf);
+ u64 (*get_count)(struct lif *lif);
+};
+
+extern const struct ionic_stats_group_intf ionic_stats_groups[];
+extern const int ionic_num_stats_grps;
+
+#define IONIC_READ_STAT64(base_ptr, desc_ptr) \
+ (*((u64 *)(((u8 *)(base_ptr)) + (desc_ptr)->offset)))
+
+struct ionic_stat_desc {
+ char name[ETH_GSTRING_LEN];
+ u64 offset;
+};
+
+#endif /* _IONIC_STATS_H_ */
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* [PATCH v4 net-next 17/19] ionic: Add RSS support
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (15 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 16/19] ionic: Add driver stats Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-22 21:40 ` [PATCH v4 net-next 18/19] ionic: Add coalesce and other features Shannon Nelson
2019-07-22 21:40 ` [PATCH v4 net-next 19/19] ionic: Add basic devlink interface Shannon Nelson
18 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Add code to manipulate through ethtool the RSS configuration
used by the NIC.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
.../ethernet/pensando/ionic/ionic_ethtool.c | 73 ++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_lif.c | 87 +++++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_lif.h | 8 ++
3 files changed, 168 insertions(+)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
index d7503a3dafb7..742d7d47f4d8 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
@@ -468,6 +468,74 @@ static int ionic_set_channels(struct net_device *netdev,
return 0;
}
+static int ionic_get_rxnfc(struct net_device *netdev,
+ struct ethtool_rxnfc *info, u32 *rules)
+{
+ struct lif *lif = netdev_priv(netdev);
+ int err = 0;
+
+ switch (info->cmd) {
+ case ETHTOOL_GRXRINGS:
+ info->data = lif->nxqs;
+ break;
+ default:
+ netdev_err(netdev, "Command parameter %d is not supported\n",
+ info->cmd);
+ err = -EOPNOTSUPP;
+ }
+
+ return err;
+}
+
+static u32 ionic_get_rxfh_indir_size(struct net_device *netdev)
+{
+ struct lif *lif = netdev_priv(netdev);
+
+ return le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
+}
+
+static u32 ionic_get_rxfh_key_size(struct net_device *netdev)
+{
+ return IONIC_RSS_HASH_KEY_SIZE;
+}
+
+static int ionic_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
+ u8 *hfunc)
+{
+ struct lif *lif = netdev_priv(netdev);
+ unsigned int i, tbl_sz;
+
+ if (indir) {
+ tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
+ for (i = 0; i < tbl_sz; i++)
+ indir[i] = lif->rss_ind_tbl[i];
+ }
+
+ if (key)
+ memcpy(key, lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE);
+
+ if (hfunc)
+ *hfunc = ETH_RSS_HASH_TOP;
+
+ return 0;
+}
+
+static int ionic_set_rxfh(struct net_device *netdev, const u32 *indir,
+ const u8 *key, const u8 hfunc)
+{
+ struct lif *lif = netdev_priv(netdev);
+ int err;
+
+ if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)
+ return -EOPNOTSUPP;
+
+ err = ionic_lif_rss_config(lif, lif->rss_types, key, indir);
+ if (err)
+ return err;
+
+ return 0;
+}
+
static u32 ionic_get_priv_flags(struct net_device *netdev)
{
struct lif *lif = netdev_priv(netdev);
@@ -580,6 +648,11 @@ static const struct ethtool_ops ionic_ethtool_ops = {
.get_strings = ionic_get_strings,
.get_ethtool_stats = ionic_get_stats,
.get_sset_count = ionic_get_sset_count,
+ .get_rxnfc = ionic_get_rxnfc,
+ .get_rxfh_indir_size = ionic_get_rxfh_indir_size,
+ .get_rxfh_key_size = ionic_get_rxfh_key_size,
+ .get_rxfh = ionic_get_rxfh,
+ .set_rxfh = ionic_set_rxfh,
.get_priv_flags = ionic_get_priv_flags,
.set_priv_flags = ionic_set_priv_flags,
.get_module_info = ionic_get_module_info,
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index 9e032d813269..68a9975e34c6 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -26,6 +26,8 @@ static void ionic_qcq_free(struct lif *lif, struct qcq *qcq);
static int ionic_lif_txqs_init(struct lif *lif);
static int ionic_lif_rxqs_init(struct lif *lif);
static void ionic_lif_qcq_deinit(struct lif *lif, struct qcq *qcq);
+static int ionic_lif_rss_init(struct lif *lif);
+static int ionic_lif_rss_deinit(struct lif *lif);
static int ionic_set_nic_features(struct lif *lif, netdev_features_t features);
static int ionic_notifyq_clean(struct lif *lif, int budget);
@@ -1082,6 +1084,9 @@ static int ionic_txrx_init(struct lif *lif)
if (err)
goto err_out;
+ if (lif->netdev->features & NETIF_F_RXHASH)
+ ionic_lif_rss_init(lif);
+
ionic_set_rx_mode(lif->netdev);
return 0;
@@ -1206,6 +1211,7 @@ static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
struct device *dev = ionic->dev;
struct net_device *netdev;
struct lif *lif;
+ int tbl_sz;
int err;
netdev = alloc_etherdev_mqs(sizeof(*lif),
@@ -1260,10 +1266,24 @@ static struct lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index)
if (err)
goto err_out_free_lif_info;
+ /* allocate rss indirection table */
+ tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
+ lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz;
+ lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz,
+ &lif->rss_ind_tbl_pa,
+ GFP_KERNEL);
+
+ if (!lif->rss_ind_tbl) {
+ dev_err(dev, "Failed to allocate rss indirection table, aborting\n");
+ goto err_out_free_qcqs;
+ }
+
list_add_tail(&lif->list, &ionic->lifs);
return lif;
+err_out_free_qcqs:
+ ionic_qcqs_free(lif);
err_out_free_lif_info:
dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa);
lif->info = NULL;
@@ -1302,6 +1322,12 @@ static void ionic_lif_free(struct lif *lif)
{
struct device *dev = lif->ionic->dev;
+ /* free rss indirection table */
+ dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl,
+ lif->rss_ind_tbl_pa);
+ lif->rss_ind_tbl = NULL;
+ lif->rss_ind_tbl_pa = 0;
+
/* free queues */
ionic_qcqs_free(lif);
ionic_lif_reset(lif);
@@ -1337,6 +1363,66 @@ void ionic_lifs_free(struct ionic *ionic)
}
}
+int ionic_lif_rss_config(struct lif *lif, const u16 types,
+ const u8 *key, const u32 *indir)
+{
+ struct ionic_admin_ctx ctx = {
+ .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
+ .cmd.lif_setattr = {
+ .opcode = CMD_OPCODE_LIF_SETATTR,
+ .attr = IONIC_LIF_ATTR_RSS,
+ .rss.types = cpu_to_le16(types),
+ .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa),
+ },
+ };
+ unsigned int i, tbl_sz;
+
+ lif->rss_types = types;
+
+ if (key)
+ memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);
+
+ if (indir) {
+ tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
+ for (i = 0; i < tbl_sz; i++)
+ lif->rss_ind_tbl[i] = indir[i];
+ }
+
+ memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
+ IONIC_RSS_HASH_KEY_SIZE);
+
+ return ionic_adminq_post_wait(lif, &ctx);
+}
+
+static int ionic_lif_rss_init(struct lif *lif)
+{
+ u8 rss_key[IONIC_RSS_HASH_KEY_SIZE];
+ unsigned int tbl_sz;
+ unsigned int i;
+
+ netdev_rss_key_fill(rss_key, IONIC_RSS_HASH_KEY_SIZE);
+
+ lif->rss_types = IONIC_RSS_TYPE_IPV4 |
+ IONIC_RSS_TYPE_IPV4_TCP |
+ IONIC_RSS_TYPE_IPV4_UDP |
+ IONIC_RSS_TYPE_IPV6 |
+ IONIC_RSS_TYPE_IPV6_TCP |
+ IONIC_RSS_TYPE_IPV6_UDP;
+
+ /* Fill indirection table with 'default' values */
+ tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
+ for (i = 0; i < tbl_sz; i++)
+ lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs);
+
+ return ionic_lif_rss_config(lif, lif->rss_types, rss_key, NULL);
+}
+
+static int ionic_lif_rss_deinit(struct lif *lif)
+{
+ /* Disable RSS on the NIC */
+ return ionic_lif_rss_config(lif, 0x0, NULL, NULL);
+}
+
static void ionic_lif_qcq_deinit(struct lif *lif, struct qcq *qcq)
{
struct ionic_dev *idev = &lif->ionic->idev;
@@ -1369,6 +1455,7 @@ static void ionic_lif_deinit(struct lif *lif)
clear_bit(LIF_INITED, lif->state);
ionic_rx_filters_deinit(lif);
+ ionic_lif_rss_deinit(lif);
napi_disable(&lif->adminqcq->napi);
ionic_lif_qcq_deinit(lif, lif->notifyqcq);
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index f93bfa2b4393..0e6908f959f2 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -166,6 +166,12 @@ struct lif {
dma_addr_t info_pa;
u32 info_sz;
+ u16 rss_types;
+ u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE];
+ u8 *rss_ind_tbl;
+ dma_addr_t rss_ind_tbl_pa;
+ u32 rss_ind_tbl_sz;
+
struct rx_filters rx_filters;
struct ionic_deferred deferred;
u32 tx_coalesce_usecs;
@@ -215,6 +221,8 @@ void ionic_lifs_unregister(struct ionic *ionic);
int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
union lif_identity *lif_ident);
int ionic_lifs_size(struct ionic *ionic);
+int ionic_lif_rss_config(struct lif *lif, u16 types,
+ const u8 *key, const u32 *indir);
int ionic_open(struct net_device *netdev);
int ionic_stop(struct net_device *netdev);
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* [PATCH v4 net-next 18/19] ionic: Add coalesce and other features
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (16 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 17/19] ionic: Add RSS support Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-23 21:40 ` David Miller
2019-07-26 0:13 ` Saeed Mahameed
2019-07-22 21:40 ` [PATCH v4 net-next 19/19] ionic: Add basic devlink interface Shannon Nelson
18 siblings, 2 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Interrupt coalescing, tunable copybreak value, and
tx timeout.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/ionic.h | 2 +-
.../ethernet/pensando/ionic/ionic_ethtool.c | 105 ++++++++++++++++++
.../net/ethernet/pensando/ionic/ionic_lif.c | 13 ++-
.../net/ethernet/pensando/ionic/ionic_lif.h | 1 +
4 files changed, 119 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
index 9b720187b549..cd08166f73a9 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -11,7 +11,7 @@ struct lif;
#define DRV_NAME "ionic"
#define DRV_DESCRIPTION "Pensando Ethernet NIC Driver"
-#define DRV_VERSION "0.11.0-k"
+#define DRV_VERSION "0.11.0-44-k"
#define PCI_VENDOR_ID_PENSANDO 0x1dd8
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
index 742d7d47f4d8..e6b579a40b70 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
@@ -377,6 +377,75 @@ static int ionic_get_coalesce(struct net_device *netdev,
return 0;
}
+static int ionic_set_coalesce(struct net_device *netdev,
+ struct ethtool_coalesce *coalesce)
+{
+ struct lif *lif = netdev_priv(netdev);
+ struct identity *ident = &lif->ionic->ident;
+ struct ionic_dev *idev = &lif->ionic->idev;
+ u32 tx_coal, rx_coal;
+ struct qcq *qcq;
+ unsigned int i;
+
+ if (coalesce->rx_max_coalesced_frames ||
+ coalesce->rx_coalesce_usecs_irq ||
+ coalesce->rx_max_coalesced_frames_irq ||
+ coalesce->tx_max_coalesced_frames ||
+ coalesce->tx_coalesce_usecs_irq ||
+ coalesce->tx_max_coalesced_frames_irq ||
+ coalesce->stats_block_coalesce_usecs ||
+ coalesce->use_adaptive_rx_coalesce ||
+ coalesce->use_adaptive_tx_coalesce ||
+ coalesce->pkt_rate_low ||
+ coalesce->rx_coalesce_usecs_low ||
+ coalesce->rx_max_coalesced_frames_low ||
+ coalesce->tx_coalesce_usecs_low ||
+ coalesce->tx_max_coalesced_frames_low ||
+ coalesce->pkt_rate_high ||
+ coalesce->rx_coalesce_usecs_high ||
+ coalesce->rx_max_coalesced_frames_high ||
+ coalesce->tx_coalesce_usecs_high ||
+ coalesce->tx_max_coalesced_frames_high ||
+ coalesce->rate_sample_interval)
+ return -EINVAL;
+
+ if (ident->dev.intr_coal_div == 0)
+ return -EIO;
+
+ /* Convert from usecs to device units */
+ tx_coal = coalesce->tx_coalesce_usecs *
+ le32_to_cpu(ident->dev.intr_coal_mult) /
+ le32_to_cpu(ident->dev.intr_coal_div);
+ rx_coal = coalesce->rx_coalesce_usecs *
+ le32_to_cpu(ident->dev.intr_coal_mult) /
+ le32_to_cpu(ident->dev.intr_coal_div);
+
+ if (tx_coal > INTR_CTRL_COAL_MAX || rx_coal > INTR_CTRL_COAL_MAX)
+ return -ERANGE;
+
+ if (coalesce->tx_coalesce_usecs != lif->tx_coalesce_usecs) {
+ for (i = 0; i < lif->nxqs; i++) {
+ qcq = lif->txqcqs[i].qcq;
+ ionic_intr_coal_init(idev->intr_ctrl,
+ qcq->intr.index,
+ tx_coal);
+ }
+ lif->tx_coalesce_usecs = coalesce->tx_coalesce_usecs;
+ }
+
+ if (coalesce->rx_coalesce_usecs != lif->rx_coalesce_usecs) {
+ for (i = 0; i < lif->nxqs; i++) {
+ qcq = lif->rxqcqs[i].qcq;
+ ionic_intr_coal_init(idev->intr_ctrl,
+ qcq->intr.index,
+ rx_coal);
+ }
+ lif->rx_coalesce_usecs = coalesce->rx_coalesce_usecs;
+ }
+
+ return 0;
+}
+
static void ionic_get_ringparam(struct net_device *netdev,
struct ethtool_ringparam *ring)
{
@@ -562,6 +631,39 @@ static int ionic_set_priv_flags(struct net_device *netdev, u32 priv_flags)
return 0;
}
+static int ionic_set_tunable(struct net_device *dev,
+ const struct ethtool_tunable *tuna,
+ const void *data)
+{
+ struct lif *lif = netdev_priv(dev);
+
+ switch (tuna->id) {
+ case ETHTOOL_RX_COPYBREAK:
+ lif->rx_copybreak = *(u32 *)data;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
+static int ionic_get_tunable(struct net_device *netdev,
+ const struct ethtool_tunable *tuna, void *data)
+{
+ struct lif *lif = netdev_priv(netdev);
+
+ switch (tuna->id) {
+ case ETHTOOL_RX_COPYBREAK:
+ *(u32 *)data = lif->rx_copybreak;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
static int ionic_get_module_info(struct net_device *netdev,
struct ethtool_modinfo *modinfo)
@@ -641,6 +743,7 @@ static const struct ethtool_ops ionic_ethtool_ops = {
.get_link = ethtool_op_get_link,
.get_link_ksettings = ionic_get_link_ksettings,
.get_coalesce = ionic_get_coalesce,
+ .set_coalesce = ionic_set_coalesce,
.get_ringparam = ionic_get_ringparam,
.set_ringparam = ionic_set_ringparam,
.get_channels = ionic_get_channels,
@@ -655,6 +758,8 @@ static const struct ethtool_ops ionic_ethtool_ops = {
.set_rxfh = ionic_set_rxfh,
.get_priv_flags = ionic_get_priv_flags,
.set_priv_flags = ionic_set_priv_flags,
+ .get_tunable = ionic_get_tunable,
+ .set_tunable = ionic_set_tunable,
.get_module_info = ionic_get_module_info,
.get_module_eeprom = ionic_get_module_eeprom,
.get_pauseparam = ionic_get_pauseparam,
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
index 68a9975e34c6..8473b065763b 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
@@ -744,9 +744,19 @@ static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
return err;
}
+static void ionic_tx_timeout_work(struct work_struct *ws)
+{
+ struct lif *lif = container_of(ws, struct lif, tx_timeout_work);
+
+ netdev_info(lif->netdev, "Tx Timeout recovery\n");
+ ionic_reset_queues(lif);
+}
+
static void ionic_tx_timeout(struct net_device *netdev)
{
- netdev_info(netdev, "%s: stubbed\n", __func__);
+ struct lif *lif = netdev_priv(netdev);
+
+ schedule_work(&lif->tx_timeout_work);
}
static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
@@ -2009,6 +2019,7 @@ static int ionic_lif_init(struct lif *lif)
ionic_link_status_check(lif);
+ INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work);
return 0;
err_out_notifyq_deinit:
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
index 0e6908f959f2..76cc519acd5a 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
@@ -180,6 +180,7 @@ struct lif {
unsigned int dbid_count;
struct dentry *dentry;
u32 flags;
+ struct work_struct tx_timeout_work;
};
#define lif_to_txqcq(lif, i) ((lif)->txqcqs[i].qcq)
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 18/19] ionic: Add coalesce and other features
2019-07-22 21:40 ` [PATCH v4 net-next 18/19] ionic: Add coalesce and other features Shannon Nelson
@ 2019-07-23 21:40 ` David Miller
2019-07-26 0:13 ` Saeed Mahameed
1 sibling, 0 replies; 69+ messages in thread
From: David Miller @ 2019-07-23 21:40 UTC (permalink / raw)
To: snelson; +Cc: netdev
From: Shannon Nelson <snelson@pensando.io>
Date: Mon, 22 Jul 2019 14:40:22 -0700
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> index 742d7d47f4d8..e6b579a40b70 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> @@ -377,6 +377,75 @@ static int ionic_get_coalesce(struct net_device *netdev,
> return 0;
> }
>
> +static int ionic_set_coalesce(struct net_device *netdev,
> + struct ethtool_coalesce *coalesce)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct identity *ident = &lif->ionic->ident;
> + struct ionic_dev *idev = &lif->ionic->idev;
> + u32 tx_coal, rx_coal;
> + struct qcq *qcq;
> + unsigned int i;
Reverse christmas tree please.
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 18/19] ionic: Add coalesce and other features
2019-07-22 21:40 ` [PATCH v4 net-next 18/19] ionic: Add coalesce and other features Shannon Nelson
2019-07-23 21:40 ` David Miller
@ 2019-07-26 0:13 ` Saeed Mahameed
2019-08-02 21:48 ` Shannon Nelson
1 sibling, 1 reply; 69+ messages in thread
From: Saeed Mahameed @ 2019-07-26 0:13 UTC (permalink / raw)
To: snelson, netdev, davem
On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
> Interrupt coalescing, tunable copybreak value, and
> tx timeout.
>
> Signed-off-by: Shannon Nelson <snelson@pensando.io>
> ---
> drivers/net/ethernet/pensando/ionic/ionic.h | 2 +-
> .../ethernet/pensando/ionic/ionic_ethtool.c | 105
> ++++++++++++++++++
> .../net/ethernet/pensando/ionic/ionic_lif.c | 13 ++-
> .../net/ethernet/pensando/ionic/ionic_lif.h | 1 +
> 4 files changed, 119 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h
> b/drivers/net/ethernet/pensando/ionic/ionic.h
> index 9b720187b549..cd08166f73a9 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic.h
> @@ -11,7 +11,7 @@ struct lif;
>
> #define DRV_NAME "ionic"
> #define DRV_DESCRIPTION "Pensando Ethernet NIC Driver"
> -#define DRV_VERSION "0.11.0-k"
> +#define DRV_VERSION "0.11.0-44-k"
>
> #define PCI_VENDOR_ID_PENSANDO 0x1dd8
>
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> index 742d7d47f4d8..e6b579a40b70 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_ethtool.c
> @@ -377,6 +377,75 @@ static int ionic_get_coalesce(struct net_device
> *netdev,
> return 0;
> }
>
> +static int ionic_set_coalesce(struct net_device *netdev,
> + struct ethtool_coalesce *coalesce)
> +{
> + struct lif *lif = netdev_priv(netdev);
> + struct identity *ident = &lif->ionic->ident;
> + struct ionic_dev *idev = &lif->ionic->idev;
> + u32 tx_coal, rx_coal;
> + struct qcq *qcq;
> + unsigned int i;
> +
> + if (coalesce->rx_max_coalesced_frames ||
> + coalesce->rx_coalesce_usecs_irq ||
> + coalesce->rx_max_coalesced_frames_irq ||
> + coalesce->tx_max_coalesced_frames ||
> + coalesce->tx_coalesce_usecs_irq ||
> + coalesce->tx_max_coalesced_frames_irq ||
> + coalesce->stats_block_coalesce_usecs ||
> + coalesce->use_adaptive_rx_coalesce ||
> + coalesce->use_adaptive_tx_coalesce ||
> + coalesce->pkt_rate_low ||
> + coalesce->rx_coalesce_usecs_low ||
> + coalesce->rx_max_coalesced_frames_low ||
> + coalesce->tx_coalesce_usecs_low ||
> + coalesce->tx_max_coalesced_frames_low ||
> + coalesce->pkt_rate_high ||
> + coalesce->rx_coalesce_usecs_high ||
> + coalesce->rx_max_coalesced_frames_high ||
> + coalesce->tx_coalesce_usecs_high ||
> + coalesce->tx_max_coalesced_frames_high ||
> + coalesce->rate_sample_interval)
> + return -EINVAL;
> +
> + if (ident->dev.intr_coal_div == 0)
> + return -EIO;
> +
> + /* Convert from usecs to device units */
> + tx_coal = coalesce->tx_coalesce_usecs *
> + le32_to_cpu(ident->dev.intr_coal_mult) /
> + le32_to_cpu(ident->dev.intr_coal_div);
> + rx_coal = coalesce->rx_coalesce_usecs *
> + le32_to_cpu(ident->dev.intr_coal_mult) /
> + le32_to_cpu(ident->dev.intr_coal_div);
> +
> + if (tx_coal > INTR_CTRL_COAL_MAX || rx_coal >
> INTR_CTRL_COAL_MAX)
> + return -ERANGE;
> +
> + if (coalesce->tx_coalesce_usecs != lif->tx_coalesce_usecs) {
> + for (i = 0; i < lif->nxqs; i++) {
> + qcq = lif->txqcqs[i].qcq;
> + ionic_intr_coal_init(idev->intr_ctrl,
> + qcq->intr.index,
> + tx_coal);
> + }
> + lif->tx_coalesce_usecs = coalesce->tx_coalesce_usecs;
> + }
> +
> + if (coalesce->rx_coalesce_usecs != lif->rx_coalesce_usecs) {
> + for (i = 0; i < lif->nxqs; i++) {
> + qcq = lif->rxqcqs[i].qcq;
> + ionic_intr_coal_init(idev->intr_ctrl,
> + qcq->intr.index,
> + rx_coal);
> + }
> + lif->rx_coalesce_usecs = coalesce->rx_coalesce_usecs;
> + }
> +
> + return 0;
> +}
> +
> static void ionic_get_ringparam(struct net_device *netdev,
> struct ethtool_ringparam *ring)
> {
> @@ -562,6 +631,39 @@ static int ionic_set_priv_flags(struct
> net_device *netdev, u32 priv_flags)
> return 0;
> }
>
> +static int ionic_set_tunable(struct net_device *dev,
> + const struct ethtool_tunable *tuna,
> + const void *data)
> +{
> + struct lif *lif = netdev_priv(dev);
> +
> + switch (tuna->id) {
> + case ETHTOOL_RX_COPYBREAK:
> + lif->rx_copybreak = *(u32 *)data;
> + break;
> + default:
> + return -EOPNOTSUPP;
> + }
> +
> + return 0;
> +}
> +
> +static int ionic_get_tunable(struct net_device *netdev,
> + const struct ethtool_tunable *tuna, void
> *data)
> +{
> + struct lif *lif = netdev_priv(netdev);
> +
> + switch (tuna->id) {
> + case ETHTOOL_RX_COPYBREAK:
> + *(u32 *)data = lif->rx_copybreak;
> + break;
> + default:
> + return -EOPNOTSUPP;
> + }
> +
> + return 0;
> +}
> +
> static int ionic_get_module_info(struct net_device *netdev,
> struct ethtool_modinfo *modinfo)
>
> @@ -641,6 +743,7 @@ static const struct ethtool_ops ionic_ethtool_ops
> = {
> .get_link = ethtool_op_get_link,
> .get_link_ksettings = ionic_get_link_ksettings,
> .get_coalesce = ionic_get_coalesce,
> + .set_coalesce = ionic_set_coalesce,
> .get_ringparam = ionic_get_ringparam,
> .set_ringparam = ionic_set_ringparam,
> .get_channels = ionic_get_channels,
> @@ -655,6 +758,8 @@ static const struct ethtool_ops ionic_ethtool_ops
> = {
> .set_rxfh = ionic_set_rxfh,
> .get_priv_flags = ionic_get_priv_flags,
> .set_priv_flags = ionic_set_priv_flags,
> + .get_tunable = ionic_get_tunable,
> + .set_tunable = ionic_set_tunable,
> .get_module_info = ionic_get_module_info,
> .get_module_eeprom = ionic_get_module_eeprom,
> .get_pauseparam = ionic_get_pauseparam,
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> index 68a9975e34c6..8473b065763b 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.c
> @@ -744,9 +744,19 @@ static int ionic_change_mtu(struct net_device
> *netdev, int new_mtu)
> return err;
> }
>
> +static void ionic_tx_timeout_work(struct work_struct *ws)
> +{
> + struct lif *lif = container_of(ws, struct lif,
> tx_timeout_work);
> +
> + netdev_info(lif->netdev, "Tx Timeout recovery\n");
> + ionic_reset_queues(lif);
missing rtnl_lock ?
> +}
> +
> static void ionic_tx_timeout(struct net_device *netdev)
> {
> - netdev_info(netdev, "%s: stubbed\n", __func__);
> + struct lif *lif = netdev_priv(netdev);
> +
> + schedule_work(&lif->tx_timeout_work);
> }
missing cancel work ? be careful when combined with the rtnl_lockthough ..
>
> static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16
> proto,
> @@ -2009,6 +2019,7 @@ static int ionic_lif_init(struct lif *lif)
>
> ionic_link_status_check(lif);
>
> + INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work);
> return 0;
>
> err_out_notifyq_deinit:
> diff --git a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> index 0e6908f959f2..76cc519acd5a 100644
> --- a/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> +++ b/drivers/net/ethernet/pensando/ionic/ionic_lif.h
> @@ -180,6 +180,7 @@ struct lif {
> unsigned int dbid_count;
> struct dentry *dentry;
> u32 flags;
> + struct work_struct tx_timeout_work;
> };
>
> #define lif_to_txqcq(lif, i) ((lif)->txqcqs[i].qcq)
^ permalink raw reply [flat|nested] 69+ messages in thread* Re: [PATCH v4 net-next 18/19] ionic: Add coalesce and other features
2019-07-26 0:13 ` Saeed Mahameed
@ 2019-08-02 21:48 ` Shannon Nelson
0 siblings, 0 replies; 69+ messages in thread
From: Shannon Nelson @ 2019-08-02 21:48 UTC (permalink / raw)
To: Saeed Mahameed, netdev, davem
On 7/25/19 5:13 PM, Saeed Mahameed wrote:
> On Mon, 2019-07-22 at 14:40 -0700, Shannon Nelson wrote:
>> +static void ionic_tx_timeout_work(struct work_struct *ws)
>> +{
>> + struct lif *lif = container_of(ws, struct lif,
>> tx_timeout_work);
>> +
>> + netdev_info(lif->netdev, "Tx Timeout recovery\n");
>> + ionic_reset_queues(lif);
> missing rtnl_lock ?
>
>> +}
>> +
>> static void ionic_tx_timeout(struct net_device *netdev)
>> {
>> - netdev_info(netdev, "%s: stubbed\n", __func__);
>> + struct lif *lif = netdev_priv(netdev);
>> +
>> + schedule_work(&lif->tx_timeout_work);
>> }
> missing cancel work ? be careful when combined with the rtnl_lockthough ..
>
>
Yep, good catch on both. I'll take care of those.
sln
^ permalink raw reply [flat|nested] 69+ messages in thread
* [PATCH v4 net-next 19/19] ionic: Add basic devlink interface
2019-07-22 21:40 [PATCH v4 net-next 00/19] Add ionic driver Shannon Nelson
` (17 preceding siblings ...)
2019-07-22 21:40 ` [PATCH v4 net-next 18/19] ionic: Add coalesce and other features Shannon Nelson
@ 2019-07-22 21:40 ` Shannon Nelson
2019-07-23 21:40 ` David Miller
18 siblings, 1 reply; 69+ messages in thread
From: Shannon Nelson @ 2019-07-22 21:40 UTC (permalink / raw)
To: snelson, netdev, davem
Add a devlink interface for access to information that isn't
normally available through ethtool or the iplink interface.
Signed-off-by: Shannon Nelson <snelson@pensando.io>
---
drivers/net/ethernet/pensando/ionic/Makefile | 2 +-
drivers/net/ethernet/pensando/ionic/ionic.h | 3 +
.../ethernet/pensando/ionic/ionic_bus_pci.c | 12 ++-
.../ethernet/pensando/ionic/ionic_devlink.c | 93 +++++++++++++++++++
.../ethernet/pensando/ionic/ionic_devlink.h | 14 +++
5 files changed, 120 insertions(+), 4 deletions(-)
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_devlink.c
create mode 100644 drivers/net/ethernet/pensando/ionic/ionic_devlink.h
diff --git a/drivers/net/ethernet/pensando/ionic/Makefile b/drivers/net/ethernet/pensando/ionic/Makefile
index 4f3cfbf36c23..ce187c7b33a8 100644
--- a/drivers/net/ethernet/pensando/ionic/Makefile
+++ b/drivers/net/ethernet/pensando/ionic/Makefile
@@ -5,4 +5,4 @@ obj-$(CONFIG_IONIC) := ionic.o
ionic-y := ionic_main.o ionic_bus_pci.o ionic_dev.o ionic_ethtool.o \
ionic_lif.o ionic_rx_filter.o ionic_txrx.o ionic_debugfs.o \
- ionic_stats.o
+ ionic_stats.o ionic_devlink.o
diff --git a/drivers/net/ethernet/pensando/ionic/ionic.h b/drivers/net/ethernet/pensando/ionic/ionic.h
index cd08166f73a9..728dfb42a52a 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic.h
+++ b/drivers/net/ethernet/pensando/ionic/ionic.h
@@ -8,6 +8,7 @@ struct lif;
#include "ionic_if.h"
#include "ionic_dev.h"
+#include "ionic_devlink.h"
#define DRV_NAME "ionic"
#define DRV_DESCRIPTION "Pensando Ethernet NIC Driver"
@@ -44,6 +45,8 @@ struct ionic {
DECLARE_BITMAP(intrs, INTR_CTRL_REGS_MAX);
struct work_struct nb_work;
struct notifier_block nb;
+ struct devlink *dl;
+ struct devlink_port dl_port;
};
struct ionic_admin_ctx {
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
index 98c12b770c7f..dfc0df2c8c8f 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -10,6 +10,7 @@
#include "ionic_bus.h"
#include "ionic_lif.h"
#include "ionic_debugfs.h"
+#include "ionic_devlink.h"
/* Supported devices */
static const struct pci_device_id ionic_id_table[] = {
@@ -110,7 +111,7 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
struct ionic *ionic;
int err;
- ionic = devm_kzalloc(dev, sizeof(*ionic), GFP_KERNEL);
+ ionic = ionic_devlink_alloc(dev);
if (!ionic)
return -ENOMEM;
@@ -212,6 +213,10 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
goto err_out_deinit_lifs;
}
+ err = ionic_devlink_register(ionic);
+ if (err)
+ dev_err(dev, "Cannot register devlink: %d\n", err);
+
return 0;
err_out_deinit_lifs:
@@ -237,6 +242,7 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
ionic_debugfs_del_dev(ionic);
err_out_clear_drvdata:
mutex_destroy(&ionic->dev_cmd_lock);
+ ionic_devlink_free(ionic);
pci_set_drvdata(pdev, NULL);
return err;
@@ -247,6 +253,7 @@ static void ionic_remove(struct pci_dev *pdev)
struct ionic *ionic = pci_get_drvdata(pdev);
if (ionic) {
+ ionic_devlink_unregister(ionic);
ionic_lifs_unregister(ionic);
ionic_lifs_deinit(ionic);
ionic_lifs_free(ionic);
@@ -261,8 +268,7 @@ static void ionic_remove(struct pci_dev *pdev)
pci_disable_device(pdev);
ionic_debugfs_del_dev(ionic);
mutex_destroy(&ionic->dev_cmd_lock);
-
- devm_kfree(&pdev->dev, ionic);
+ ionic_devlink_free(ionic);
}
}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_devlink.c b/drivers/net/ethernet/pensando/ionic/ionic_devlink.c
new file mode 100644
index 000000000000..a30a61e51c71
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_devlink.c
@@ -0,0 +1,93 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#include <linux/module.h>
+#include <linux/netdevice.h>
+
+#include "ionic.h"
+#include "ionic_bus.h"
+#include "ionic_lif.h"
+#include "ionic_devlink.h"
+
+static int ionic_dl_info_get(struct devlink *dl, struct devlink_info_req *req,
+ struct netlink_ext_ack *extack)
+{
+ struct ionic *ionic = devlink_priv(dl);
+ struct ionic_dev *idev = &ionic->idev;
+ char buf[16];
+
+ devlink_info_driver_name_put(req, DRV_NAME);
+
+ devlink_info_version_running_put(req,
+ DEVLINK_INFO_VERSION_GENERIC_FW_MGMT,
+ idev->dev_info.fw_version);
+
+ snprintf(buf, sizeof(buf), "0x%x", idev->dev_info.asic_type);
+ devlink_info_version_fixed_put(req,
+ DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
+ buf);
+
+ snprintf(buf, sizeof(buf), "0x%x", idev->dev_info.asic_rev);
+ devlink_info_version_fixed_put(req,
+ DEVLINK_INFO_VERSION_GENERIC_BOARD_REV,
+ buf);
+
+ devlink_info_serial_number_put(req, idev->dev_info.serial_num);
+
+ return 0;
+}
+
+static const struct devlink_ops ionic_dl_ops = {
+ .info_get = ionic_dl_info_get,
+};
+
+struct ionic *ionic_devlink_alloc(struct device *dev)
+{
+ struct devlink *dl;
+ struct ionic *ionic;
+
+ dl = devlink_alloc(&ionic_dl_ops, sizeof(struct ionic));
+ if (!dl) {
+ dev_warn(dev, "devlink_alloc failed");
+ return NULL;
+ }
+
+ ionic = devlink_priv(dl);
+ ionic->dl = dl;
+
+ return ionic;
+}
+
+void ionic_devlink_free(struct ionic *ionic)
+{
+ devlink_free(ionic->dl);
+}
+
+int ionic_devlink_register(struct ionic *ionic)
+{
+ int err;
+
+ err = devlink_register(ionic->dl, ionic->dev);
+ if (err)
+ dev_warn(ionic->dev, "devlink_register failed: %d\n", err);
+
+ devlink_port_attrs_set(&ionic->dl_port, DEVLINK_PORT_FLAVOUR_PHYSICAL,
+ 0, false, 0, NULL, 0);
+ err = devlink_port_register(ionic->dl, &ionic->dl_port, 0);
+ if (err)
+ dev_err(ionic->dev, "devlink_port_register failed: %d\n", err);
+ else
+ devlink_port_type_eth_set(&ionic->dl_port,
+ ionic->master_lif->netdev);
+
+ return err;
+}
+
+void ionic_devlink_unregister(struct ionic *ionic)
+{
+ if (!ionic || !ionic->dl)
+ return;
+
+ devlink_port_unregister(&ionic->dl_port);
+ devlink_unregister(ionic->dl);
+}
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_devlink.h b/drivers/net/ethernet/pensando/ionic/ionic_devlink.h
new file mode 100644
index 000000000000..0690172fc57a
--- /dev/null
+++ b/drivers/net/ethernet/pensando/ionic/ionic_devlink.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
+
+#ifndef _IONIC_DEVLINK_H_
+#define _IONIC_DEVLINK_H_
+
+#include <net/devlink.h>
+
+struct ionic *ionic_devlink_alloc(struct device *dev);
+void ionic_devlink_free(struct ionic *ionic);
+int ionic_devlink_register(struct ionic *ionic);
+void ionic_devlink_unregister(struct ionic *ionic);
+
+#endif /* _IONIC_DEVLINK_H_ */
--
2.17.1
^ permalink raw reply related [flat|nested] 69+ messages in thread