* drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]
@ 2022-11-21 15:36 kernel test robot
0 siblings, 0 replies; 4+ messages in thread
From: kernel test robot @ 2022-11-21 15:36 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "low confidence static check warning: drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
CC: linux-kernel@vger.kernel.org
TO: Dan Williams <dan.j.williams@intel.com>
CC: Jonathan Cameron <Jonathan.Cameron@huawei.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: eb7081409f94a9a8608593d0fb63a1aa3d6f95d8
commit: 391785859e7e6521f622ad8c965c9792767023bc cxl/port: Move dport tracking to an xarray
date: 4 months ago
:::::: branch date: 16 hours ago
:::::: commit date: 4 months ago
compiler: ia64-linux-gcc (GCC) 12.1.0
reproduce (cppcheck warning):
# apt-get install cppcheck
git checkout 391785859e7e6521f622ad8c965c9792767023bc
cppcheck --quiet --enable=style,performance,portability --template=gcc FILE
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
cppcheck possible warnings: (new ones prefixed by >>, may not real problems)
>> drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]
single_port_map[0] = dport->port_id;
^
vim +65 drivers/cxl/core/hdm.c
d17d0540a0dbf1 Dan Williams 2022-02-01 42
d17d0540a0dbf1 Dan Williams 2022-02-01 43 /*
d17d0540a0dbf1 Dan Williams 2022-02-01 44 * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
d17d0540a0dbf1 Dan Williams 2022-02-01 45 * single ported host-bridges need not publish a decoder capability when a
d17d0540a0dbf1 Dan Williams 2022-02-01 46 * passthrough decode can be assumed, i.e. all transactions that the uport sees
d17d0540a0dbf1 Dan Williams 2022-02-01 47 * are claimed and passed to the single dport. Disable the range until the first
d17d0540a0dbf1 Dan Williams 2022-02-01 48 * CXL region is enumerated / activated.
d17d0540a0dbf1 Dan Williams 2022-02-01 49 */
664bf115833c2d Dan Williams 2022-02-01 50 int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
d17d0540a0dbf1 Dan Williams 2022-02-01 51 {
e636479e2f1b61 Dan Williams 2022-05-18 52 struct cxl_switch_decoder *cxlsd;
391785859e7e65 Dan Williams 2022-05-27 53 struct cxl_dport *dport = NULL;
d17d0540a0dbf1 Dan Williams 2022-02-01 54 int single_port_map[1];
391785859e7e65 Dan Williams 2022-05-27 55 unsigned long index;
d17d0540a0dbf1 Dan Williams 2022-02-01 56
e636479e2f1b61 Dan Williams 2022-05-18 57 cxlsd = cxl_switch_decoder_alloc(port, 1);
e636479e2f1b61 Dan Williams 2022-05-18 58 if (IS_ERR(cxlsd))
e636479e2f1b61 Dan Williams 2022-05-18 59 return PTR_ERR(cxlsd);
d17d0540a0dbf1 Dan Williams 2022-02-01 60
d17d0540a0dbf1 Dan Williams 2022-02-01 61 device_lock_assert(&port->dev);
d17d0540a0dbf1 Dan Williams 2022-02-01 62
391785859e7e65 Dan Williams 2022-05-27 63 xa_for_each(&port->dports, index, dport)
391785859e7e65 Dan Williams 2022-05-27 64 break;
d17d0540a0dbf1 Dan Williams 2022-02-01 @65 single_port_map[0] = dport->port_id;
d17d0540a0dbf1 Dan Williams 2022-02-01 66
e636479e2f1b61 Dan Williams 2022-05-18 67 return add_hdm_decoder(port, &cxlsd->cxld, single_port_map);
d17d0540a0dbf1 Dan Williams 2022-02-01 68 }
d17d0540a0dbf1 Dan Williams 2022-02-01 69 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_passthrough_decoder, CXL);
d17d0540a0dbf1 Dan Williams 2022-02-01 70
:::::: The code at line 65 was first introduced by commit
:::::: d17d0540a0dbf109210f7b57a37571e2978da0fa cxl/core/hdm: Add CXL standard decoder enumeration to the core
:::::: TO: Dan Williams <dan.j.williams@intel.com>
:::::: CC: Dan Williams <dan.j.williams@intel.com>
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 4+ messages in thread
* drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]
@ 2023-02-14 22:12 kernel test robot
0 siblings, 0 replies; 4+ messages in thread
From: kernel test robot @ 2023-02-14 22:12 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "low confidence static check warning: drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
CC: linux-kernel@vger.kernel.org
TO: Dan Williams <dan.j.williams@intel.com>
CC: Jonathan Cameron <Jonathan.Cameron@huawei.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: e1c04510f521e853019afeca2a5991a5ef8d6a5b
commit: 391785859e7e6521f622ad8c965c9792767023bc cxl/port: Move dport tracking to an xarray
date: 7 months ago
:::::: branch date: 5 hours ago
:::::: commit date: 7 months ago
compiler: arm-linux-gnueabi-gcc (GCC) 12.1.0
reproduce (cppcheck warning):
# apt-get install cppcheck
git checkout 391785859e7e6521f622ad8c965c9792767023bc
cppcheck --quiet --enable=style,performance,portability --template=gcc FILE
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/r/202302150603.GYl9T8vq-lkp@intel.com/
cppcheck possible warnings: (new ones prefixed by >>, may not real problems)
>> drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]
single_port_map[0] = dport->port_id;
^
vim +65 drivers/cxl/core/hdm.c
d17d0540a0dbf1 Dan Williams 2022-02-01 42
d17d0540a0dbf1 Dan Williams 2022-02-01 43 /*
d17d0540a0dbf1 Dan Williams 2022-02-01 44 * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
d17d0540a0dbf1 Dan Williams 2022-02-01 45 * single ported host-bridges need not publish a decoder capability when a
d17d0540a0dbf1 Dan Williams 2022-02-01 46 * passthrough decode can be assumed, i.e. all transactions that the uport sees
d17d0540a0dbf1 Dan Williams 2022-02-01 47 * are claimed and passed to the single dport. Disable the range until the first
d17d0540a0dbf1 Dan Williams 2022-02-01 48 * CXL region is enumerated / activated.
d17d0540a0dbf1 Dan Williams 2022-02-01 49 */
664bf115833c2d Dan Williams 2022-02-01 50 int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
d17d0540a0dbf1 Dan Williams 2022-02-01 51 {
e636479e2f1b61 Dan Williams 2022-05-18 52 struct cxl_switch_decoder *cxlsd;
391785859e7e65 Dan Williams 2022-05-27 53 struct cxl_dport *dport = NULL;
d17d0540a0dbf1 Dan Williams 2022-02-01 54 int single_port_map[1];
391785859e7e65 Dan Williams 2022-05-27 55 unsigned long index;
d17d0540a0dbf1 Dan Williams 2022-02-01 56
e636479e2f1b61 Dan Williams 2022-05-18 57 cxlsd = cxl_switch_decoder_alloc(port, 1);
e636479e2f1b61 Dan Williams 2022-05-18 58 if (IS_ERR(cxlsd))
e636479e2f1b61 Dan Williams 2022-05-18 59 return PTR_ERR(cxlsd);
d17d0540a0dbf1 Dan Williams 2022-02-01 60
d17d0540a0dbf1 Dan Williams 2022-02-01 61 device_lock_assert(&port->dev);
d17d0540a0dbf1 Dan Williams 2022-02-01 62
391785859e7e65 Dan Williams 2022-05-27 63 xa_for_each(&port->dports, index, dport)
391785859e7e65 Dan Williams 2022-05-27 64 break;
d17d0540a0dbf1 Dan Williams 2022-02-01 @65 single_port_map[0] = dport->port_id;
d17d0540a0dbf1 Dan Williams 2022-02-01 66
e636479e2f1b61 Dan Williams 2022-05-18 67 return add_hdm_decoder(port, &cxlsd->cxld, single_port_map);
d17d0540a0dbf1 Dan Williams 2022-02-01 68 }
d17d0540a0dbf1 Dan Williams 2022-02-01 69 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_passthrough_decoder, CXL);
d17d0540a0dbf1 Dan Williams 2022-02-01 70
:::::: The code at line 65 was first introduced by commit
:::::: d17d0540a0dbf109210f7b57a37571e2978da0fa cxl/core/hdm: Add CXL standard decoder enumeration to the core
:::::: TO: Dan Williams <dan.j.williams@intel.com>
:::::: CC: Dan Williams <dan.j.williams@intel.com>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 4+ messages in thread
* drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]
@ 2023-02-05 4:15 kernel test robot
0 siblings, 0 replies; 4+ messages in thread
From: kernel test robot @ 2023-02-05 4:15 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "low confidence static check warning: drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
CC: linux-kernel@vger.kernel.org
TO: Dan Williams <dan.j.williams@intel.com>
CC: Jonathan Cameron <Jonathan.Cameron@huawei.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 837c07cf68fec9cad455d5fc86aab5350cc06c53
commit: 391785859e7e6521f622ad8c965c9792767023bc cxl/port: Move dport tracking to an xarray
date: 7 months ago
:::::: branch date: 2 hours ago
:::::: commit date: 7 months ago
compiler: s390-linux-gcc (GCC) 12.1.0
reproduce (cppcheck warning):
# apt-get install cppcheck
git checkout 391785859e7e6521f622ad8c965c9792767023bc
cppcheck --quiet --enable=style,performance,portability --template=gcc FILE
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
cppcheck possible warnings: (new ones prefixed by >>, may not real problems)
>> drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]
single_port_map[0] = dport->port_id;
^
vim +65 drivers/cxl/core/hdm.c
d17d0540a0dbf1 Dan Williams 2022-02-01 42
d17d0540a0dbf1 Dan Williams 2022-02-01 43 /*
d17d0540a0dbf1 Dan Williams 2022-02-01 44 * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
d17d0540a0dbf1 Dan Williams 2022-02-01 45 * single ported host-bridges need not publish a decoder capability when a
d17d0540a0dbf1 Dan Williams 2022-02-01 46 * passthrough decode can be assumed, i.e. all transactions that the uport sees
d17d0540a0dbf1 Dan Williams 2022-02-01 47 * are claimed and passed to the single dport. Disable the range until the first
d17d0540a0dbf1 Dan Williams 2022-02-01 48 * CXL region is enumerated / activated.
d17d0540a0dbf1 Dan Williams 2022-02-01 49 */
664bf115833c2d Dan Williams 2022-02-01 50 int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
d17d0540a0dbf1 Dan Williams 2022-02-01 51 {
e636479e2f1b61 Dan Williams 2022-05-18 52 struct cxl_switch_decoder *cxlsd;
391785859e7e65 Dan Williams 2022-05-27 53 struct cxl_dport *dport = NULL;
d17d0540a0dbf1 Dan Williams 2022-02-01 54 int single_port_map[1];
391785859e7e65 Dan Williams 2022-05-27 55 unsigned long index;
d17d0540a0dbf1 Dan Williams 2022-02-01 56
e636479e2f1b61 Dan Williams 2022-05-18 57 cxlsd = cxl_switch_decoder_alloc(port, 1);
e636479e2f1b61 Dan Williams 2022-05-18 58 if (IS_ERR(cxlsd))
e636479e2f1b61 Dan Williams 2022-05-18 59 return PTR_ERR(cxlsd);
d17d0540a0dbf1 Dan Williams 2022-02-01 60
d17d0540a0dbf1 Dan Williams 2022-02-01 61 device_lock_assert(&port->dev);
d17d0540a0dbf1 Dan Williams 2022-02-01 62
391785859e7e65 Dan Williams 2022-05-27 63 xa_for_each(&port->dports, index, dport)
391785859e7e65 Dan Williams 2022-05-27 64 break;
d17d0540a0dbf1 Dan Williams 2022-02-01 @65 single_port_map[0] = dport->port_id;
d17d0540a0dbf1 Dan Williams 2022-02-01 66
e636479e2f1b61 Dan Williams 2022-05-18 67 return add_hdm_decoder(port, &cxlsd->cxld, single_port_map);
d17d0540a0dbf1 Dan Williams 2022-02-01 68 }
d17d0540a0dbf1 Dan Williams 2022-02-01 69 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_passthrough_decoder, CXL);
d17d0540a0dbf1 Dan Williams 2022-02-01 70
:::::: The code at line 65 was first introduced by commit
:::::: d17d0540a0dbf109210f7b57a37571e2978da0fa cxl/core/hdm: Add CXL standard decoder enumeration to the core
:::::: TO: Dan Williams <dan.j.williams@intel.com>
:::::: CC: Dan Williams <dan.j.williams@intel.com>
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 4+ messages in thread
* drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]
@ 2022-11-02 3:47 kernel test robot
0 siblings, 0 replies; 4+ messages in thread
From: kernel test robot @ 2022-11-02 3:47 UTC (permalink / raw)
To: oe-kbuild; +Cc: lkp
::::::
:::::: Manual check reason: "low confidence static check warning: drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]"
::::::
BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
CC: linux-kernel@vger.kernel.org
TO: Dan Williams <dan.j.williams@intel.com>
CC: Jonathan Cameron <Jonathan.Cameron@huawei.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 8f71a2b3f435f29b787537d1abedaa7d8ebe6647
commit: 391785859e7e6521f622ad8c965c9792767023bc cxl/port: Move dport tracking to an xarray
date: 3 months ago
:::::: branch date: 5 hours ago
:::::: commit date: 3 months ago
compiler: sparc64-linux-gcc (GCC) 12.1.0
reproduce (cppcheck warning):
# apt-get install cppcheck
git checkout 391785859e7e6521f622ad8c965c9792767023bc
cppcheck --quiet --enable=style,performance,portability --template=gcc FILE
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
cppcheck possible warnings: (new ones prefixed by >>, may not real problems)
>> drivers/cxl/core/hdm.c:65:2: warning: Statements following return, break, continue, goto or throw will never be executed. [unreachableCode]
single_port_map[0] = dport->port_id;
^
vim +65 drivers/cxl/core/hdm.c
d17d0540a0dbf1 Dan Williams 2022-02-01 42
d17d0540a0dbf1 Dan Williams 2022-02-01 43 /*
d17d0540a0dbf1 Dan Williams 2022-02-01 44 * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
d17d0540a0dbf1 Dan Williams 2022-02-01 45 * single ported host-bridges need not publish a decoder capability when a
d17d0540a0dbf1 Dan Williams 2022-02-01 46 * passthrough decode can be assumed, i.e. all transactions that the uport sees
d17d0540a0dbf1 Dan Williams 2022-02-01 47 * are claimed and passed to the single dport. Disable the range until the first
d17d0540a0dbf1 Dan Williams 2022-02-01 48 * CXL region is enumerated / activated.
d17d0540a0dbf1 Dan Williams 2022-02-01 49 */
664bf115833c2d Dan Williams 2022-02-01 50 int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
d17d0540a0dbf1 Dan Williams 2022-02-01 51 {
e636479e2f1b61 Dan Williams 2022-05-18 52 struct cxl_switch_decoder *cxlsd;
391785859e7e65 Dan Williams 2022-05-27 53 struct cxl_dport *dport = NULL;
d17d0540a0dbf1 Dan Williams 2022-02-01 54 int single_port_map[1];
391785859e7e65 Dan Williams 2022-05-27 55 unsigned long index;
d17d0540a0dbf1 Dan Williams 2022-02-01 56
e636479e2f1b61 Dan Williams 2022-05-18 57 cxlsd = cxl_switch_decoder_alloc(port, 1);
e636479e2f1b61 Dan Williams 2022-05-18 58 if (IS_ERR(cxlsd))
e636479e2f1b61 Dan Williams 2022-05-18 59 return PTR_ERR(cxlsd);
d17d0540a0dbf1 Dan Williams 2022-02-01 60
d17d0540a0dbf1 Dan Williams 2022-02-01 61 device_lock_assert(&port->dev);
d17d0540a0dbf1 Dan Williams 2022-02-01 62
391785859e7e65 Dan Williams 2022-05-27 63 xa_for_each(&port->dports, index, dport)
391785859e7e65 Dan Williams 2022-05-27 64 break;
d17d0540a0dbf1 Dan Williams 2022-02-01 @65 single_port_map[0] = dport->port_id;
d17d0540a0dbf1 Dan Williams 2022-02-01 66
e636479e2f1b61 Dan Williams 2022-05-18 67 return add_hdm_decoder(port, &cxlsd->cxld, single_port_map);
d17d0540a0dbf1 Dan Williams 2022-02-01 68 }
d17d0540a0dbf1 Dan Williams 2022-02-01 69 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_passthrough_decoder, CXL);
d17d0540a0dbf1 Dan Williams 2022-02-01 70
:::::: The code at line 65 was first introduced by commit
:::::: d17d0540a0dbf109210f7b57a37571e2978da0fa cxl/core/hdm: Add CXL standard decoder enumeration to the core
:::::: TO: Dan Williams <dan.j.williams@intel.com>
:::::: CC: Dan Williams <dan.j.williams@intel.com>
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-02-14 22:13 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
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-- strict thread matches above, loose matches on Subject: below --
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