From: Joel Stanley <joel@jms.id.au>
To: Quan Nguyen <quan@os.amperecomputing.com>
Cc: devicetree <devicetree@vger.kernel.org>,
linux-aspeed <linux-aspeed@lists.ozlabs.org>,
Andrew Jeffery <andrew@aj.id.au>,
OpenBMC Maillist <openbmc@lists.ozlabs.org>,
"Thang Q . Nguyen" <thang@os.amperecomputing.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Phong Vo <phong@os.amperecomputing.com>,
Rob Herring <robh+dt@kernel.org>,
Open Source Submission <patches@amperecomputing.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios
Date: Tue, 19 Oct 2021 06:46:14 +0000 [thread overview]
Message-ID: <CACPK8Xcp0ruL-7p3AA+yvba3Drrwm-=-hMnMpd=a1aHwQHnE1A@mail.gmail.com> (raw)
In-Reply-To: <20211019060155.945-2-quan@os.amperecomputing.com>
On Tue, 19 Oct 2021 at 06:02, Quan Nguyen <quan@os.amperecomputing.com> wrote:
>
> Add S0_SCP_AUTH_FAIL, S1_SCP_AUTH_FAIL gpios to indicates firmware
> authentication fail on each socket.
These use the gpio-keys API to expose the GPIOs. I think OpenBMC is
moving away from this abstraction, and instead reading the GPIOs with
the gpio chardev interface.
>
> Add gpio RTC_BAT_SEN_EN to enable RTC battery adc sensor.
>
> Add BMC_I2C4_O_EN gpio to go high at boot to enable access to I2C4 bus.
OpenBMC has started a process to document GPIOs that are exposed to
userspace, initially so a common userspace can be used across
machines. I like doing it for the additional reason that it provides
consistency in the naming.
https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md
If you could take a look at that document and add your GPIOs where
possible, and then update the device tree.
>
> Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
> Signed-off-by: Thang Nguyen <thang@os.amperecomputing.com>
> ---
> v2:
> - None
>
> .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 21 ++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
> index 57b0c45a2298..3515d55bd312 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
> @@ -86,6 +86,18 @@ S0_cpu_fault {
> linux,code = <ASPEED_GPIO(J, 1)>;
> };
>
> + S0_scp_auth_fail {
> + label = "S0_SCP_AUTH_FAIL";
> + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
> + linux,code = <ASPEED_GPIO(J, 2)>;
> + };
> +
> + S1_scp_auth_fail {
> + label = "S1_SCP_AUTH_FAIL";
> + gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
> + linux,code = <ASPEED_GPIO(Z, 5)>;
> + };
> +
> S1_overtemp {
> label = "S1_OVERTEMP";
> gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
> @@ -590,7 +602,7 @@ &gpio {
> /*Q0-Q7*/ "","","","","","UID_BUTTON","","",
> /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN",
> "OCP_MAIN_PWREN","RESET_BUTTON","","",
> - /*S0-S7*/ "","","","","","","","",
> + /*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","",
I suggest you create a proposal to call this one
battery-voltage-read-enable. I know that some of the IBM machines
intend to have this same GPIO.
> /*T0-T7*/ "","","","","","","","",
> /*U0-U7*/ "","","","","","","","",
> /*V0-V7*/ "","","","","","","","",
> @@ -604,4 +616,11 @@ &gpio {
> "S1_BMC_DDR_ADR","","","","",
> /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L",
> "BMC_OCP_PG";
> +
> + i2c4_o_en {
> + gpio-hog;
> + gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>;
> + output-high;
> + line-name = "BMC_I2C4_O_EN";
> + };
> };
> --
> 2.28.0
>
next prev parent reply other threads:[~2021-10-19 6:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 6:01 [PATCH v2 0/3] Update gpios, nvme i2c busses and uefi partition Quan Nguyen
2021-10-19 6:01 ` [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios Quan Nguyen
2021-10-19 6:46 ` Joel Stanley [this message]
2021-10-19 10:37 ` Thang Nguyen
2021-10-25 4:44 ` Quan Nguyen
2021-11-01 9:25 ` Quan Nguyen
2021-11-16 5:24 ` Joel Stanley
2021-10-19 6:01 ` [PATCH v2 2/3] ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices Quan Nguyen
2021-10-19 6:46 ` Joel Stanley
2021-10-19 6:01 ` [PATCH v2 3/3] ARM: dts: aspeed: mtjade: Add uefi partition Quan Nguyen
2021-10-19 6:46 ` Joel Stanley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CACPK8Xcp0ruL-7p3AA+yvba3Drrwm-=-hMnMpd=a1aHwQHnE1A@mail.gmail.com' \
--to=joel@jms.id.au \
--cc=andrew@aj.id.au \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-aspeed@lists.ozlabs.org \
--cc=linux-kernel@vger.kernel.org \
--cc=openbmc@lists.ozlabs.org \
--cc=patches@amperecomputing.com \
--cc=phong@os.amperecomputing.com \
--cc=quan@os.amperecomputing.com \
--cc=robh+dt@kernel.org \
--cc=thang@os.amperecomputing.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).