From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: paulburton@kernel.org, tsbogend@alpha.franken.de, paul@crapouillou.net
Cc: linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
jiaxun.yang@flygoat.com, rppt@kernel.org,
Sergey.Semin@baikalelectronics.ru,
Alexey.Malahov@baikalelectronics.ru, akpm@linux-foundation.org,
dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com,
rick.tyliu@ingenic.com, yanfei.li@ingenic.com,
sernia.zhou@foxmail.com, zhenwenjin@gmail.com
Subject: [PATCH 2/2] MIPS: Ingenic: Fix bugs when detecting X1000E's L2 cache.
Date: Sat, 19 Sep 2020 20:44:37 +0800 [thread overview]
Message-ID: <20200919124437.89576-3-zhouyanjie@wanyeetech.com> (raw)
In-Reply-To: <20200919124437.89576-1-zhouyanjie@wanyeetech.com>
Fix bugs when detecting L2 cache sets value and ways value.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
arch/mips/mm/sc-mips.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 97dc0511e63f..145b39ecb246 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -235,6 +235,7 @@ static inline int __init mips_sc_probe(void)
* According to config2 it would be 5-ways and 512-sets,
* but that is contradicted by all documentation.
*/
+ case MACH_INGENIC_X1000E:
case MACH_INGENIC_X1000:
c->scache.sets = 256;
c->scache.ways = 4;
--
2.11.0
prev parent reply other threads:[~2020-09-19 12:45 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-19 12:44 [PATCH 0/2] Repair X1000E SoC L2 cache capacity detection 周琰杰 (Zhou Yanjie)
2020-09-19 12:44 ` [PATCH 1/2] MIPS: X1000E: Add X1000E system type 周琰杰 (Zhou Yanjie)
2020-09-21 12:31 ` Paul Cercueil
2020-09-19 12:44 ` 周琰杰 (Zhou Yanjie) [this message]
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