From: Sunil V L <sunilvl@ventanamicro.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
linux-crypto@vger.kernel.org,
platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev,
Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Len Brown <lenb@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Weili Qian <qianweili@huawei.com>,
Zhou Wang <wangzhou1@hisilicon.com>,
Herbert Xu <herbert@gondor.apana.org.au>,
Marc Zyngier <maz@kernel.org>,
Maximilian Luz <luzmaximilian@gmail.com>,
Hans de Goede <hdegoede@redhat.com>,
Mark Gross <markgross@kernel.org>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Tom Rix <trix@redhat.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"David S . Miller" <davem@davemloft.net>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>
Subject: Re: [PATCH V4 08/23] RISC-V: ACPI: Cache and retrieve the RINTC structure
Date: Thu, 6 Apr 2023 09:16:31 +0530 [thread overview]
Message-ID: <ZC5Al3swBGK1WP0g@sunil-laptop> (raw)
In-Reply-To: <h4wgl5pc4bptxsmlmf7ggohq2y2uwk6ecaoytyywbwhf2ubnzj@ojanwytq5lrk>
On Wed, Apr 05, 2023 at 05:17:48PM +0200, Andrew Jones wrote:
> On Tue, Apr 04, 2023 at 11:50:22PM +0530, Sunil V L wrote:
> > RINTC structures in the MADT provide mapping between the hartid
> > and the CPU. This is required many times even at run time like
> > cpuinfo. So, instead of parsing the ACPI table every time, cache
> > the RINTC structures and provide a function to get the correct
> > RINTC structure for a given cpu.
> >
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> > ---
> > arch/riscv/include/asm/acpi.h | 2 ++
> > arch/riscv/kernel/acpi.c | 60 +++++++++++++++++++++++++++++++++++
> > 2 files changed, 62 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
> > index 9be52b6ffae1..1606dce8992e 100644
> > --- a/arch/riscv/include/asm/acpi.h
> > +++ b/arch/riscv/include/asm/acpi.h
> > @@ -59,6 +59,8 @@ static inline bool acpi_has_cpu_in_madt(void)
> >
> > static inline void arch_fix_phys_package_id(int num, u32 slot) { }
> >
> > +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu);
> > +u32 get_acpi_id_for_cpu(int cpu);
> > #endif /* CONFIG_ACPI */
> >
> > #endif /*_ASM_ACPI_H*/
> > diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
> > index 81d448c41714..40ab55309c70 100644
> > --- a/arch/riscv/kernel/acpi.c
> > +++ b/arch/riscv/kernel/acpi.c
> > @@ -24,6 +24,66 @@ EXPORT_SYMBOL(acpi_disabled);
> > int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */
> > EXPORT_SYMBOL(acpi_pci_disabled);
> >
> > +static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS];
> > +
> > +static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end)
> > +{
> > + struct acpi_madt_rintc *rintc = (struct acpi_madt_rintc *)header;
> > + int cpuid;
> > +
> > + if (!(rintc->flags & ACPI_MADT_ENABLED))
> > + return 0;
> > +
> > + cpuid = riscv_hartid_to_cpuid(rintc->hart_id);
> > + /*
> > + * When CONFIG_SMP is disabled, mapping won't be created for
> > + * all cpus.
> > + * CPUs more than NR_CPUS, will be ignored.
> > + */
> > + if (cpuid >= 0 && cpuid < NR_CPUS)
> > + cpu_madt_rintc[cpuid] = *rintc;
> > +
> > + return 0;
> > +}
> > +
> > +static int acpi_init_rintc_array(void)
> > +{
> > + if (acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_madt_rintc, 0) > 0)
> > + return 0;
> > +
> > + return -ENODEV;
>
> As Conor pointed out, the errors could be propagated from
> acpi_table_parse_madt(), which could reduce this function to
>
> return acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_madt_rintc, 0);
>
> where the '< 0' check would be in the caller below. That sounds good to
> me, but then I'd take that a step further and just drop this helper
> altogether.
>
Thanks, Conor, Drew. I used similar to how others have used
acpi_table_parse_madt(). But your suggestion makes sense. Will remove
the wrapper function also.
Thanks,
Sunil
next prev parent reply other threads:[~2023-04-06 3:46 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 18:20 [PATCH V4 00/23] Add basic ACPI support for RISC-V Sunil V L
2023-04-04 18:20 ` [PATCH V4 01/23] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-04-04 18:20 ` [PATCH V4 02/23] ACPICA: MADT: Add RISC-V INTC interrupt controller Sunil V L
2023-04-04 18:20 ` [PATCH V4 03/23] ACPICA: Add structure definitions for RISC-V RHCT Sunil V L
2023-04-04 18:20 ` [PATCH V4 04/23] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-04-04 18:20 ` [PATCH V4 05/23] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-04-26 16:47 ` Björn Töpel
2023-04-27 9:27 ` Sunil V L
2023-04-27 11:24 ` Björn Töpel
2023-04-04 18:20 ` [PATCH V4 06/23] RISC-V: Add support to build the ACPI core Sunil V L
2023-04-26 18:44 ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 07/23] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-04-04 18:20 ` [PATCH V4 08/23] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-04-04 20:14 ` Conor Dooley
2023-04-05 15:17 ` Andrew Jones
2023-04-06 3:46 ` Sunil V L [this message]
2023-04-26 18:45 ` Palmer Dabbelt
2023-04-27 9:22 ` Sunil V L
2023-04-27 10:25 ` Andrew Jones
2023-04-27 10:52 ` Sunil V L
2023-04-27 13:13 ` Andrew Jones
2023-04-04 18:20 ` [PATCH V4 09/23] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-04-26 18:45 ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 10/23] RISC-V: smpboot: Create wrapper smp_setup() Sunil V L
2023-04-26 18:45 ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 11/23] RISC-V: smpboot: Add ACPI support in smp_setup() Sunil V L
2023-04-05 14:58 ` Andrew Jones
2023-04-04 18:20 ` [PATCH V4 12/23] RISC-V: cpufeature: Avoid calling riscv_of_processor_hartid() Sunil V L
2023-04-04 20:46 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 13/23] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-04-04 20:57 ` Conor Dooley
2023-04-05 13:35 ` Sunil V L
2023-04-05 14:31 ` Conor Dooley
2023-04-05 15:37 ` Andrew Jones
2023-04-29 10:31 ` Conor Dooley
2023-05-02 1:28 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 14/23] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-04-04 21:04 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 15/23] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-04-05 15:48 ` Andrew Jones
2023-04-06 3:47 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 16/23] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-04-04 21:25 ` Conor Dooley
2023-04-05 10:55 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 17/23] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-04-04 21:27 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 18/23] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-04-04 18:20 ` [PATCH V4 19/23] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-04-04 21:38 ` Conor Dooley
2023-04-05 15:11 ` Sunil V L
2023-04-05 15:30 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 20/23] RISC-V: Enable ACPI in defconfig Sunil V L
2023-04-04 21:43 ` Conor Dooley
2023-04-05 10:58 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 21/23] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-04-04 18:20 ` [PATCH V4 22/23] platform/surface: Disable for RISC-V Sunil V L
2023-04-05 4:19 ` Jessica Clarke
2023-04-05 11:29 ` Sunil V L
2023-04-05 9:33 ` Maximilian Luz
2023-04-05 11:11 ` Sunil V L
2023-04-05 11:35 ` Maximilian Luz
2023-04-04 18:20 ` [PATCH V4 23/23] crypto: hisilicon/qm: Workaround to enable build with RISC-V clang Sunil V L
2023-04-04 21:59 ` Conor Dooley
2023-04-05 10:46 ` Sunil V L
2023-04-05 8:16 ` Arnd Bergmann
2023-04-11 11:42 ` Weili Qian
2023-04-19 14:34 ` Arnd Bergmann
2023-04-04 18:42 ` [PATCH V4 00/23] Add basic ACPI support for RISC-V Conor Dooley
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