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From: Sunil V L <sunilvl@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
	linux-crypto@vger.kernel.org,
	platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev,
	corbet@lwn.net, Paul Walmsley <paul.walmsley@sifive.com>,
	aou@eecs.berkeley.edu, lenb@kernel.org,
	daniel.lezcano@linaro.org, tglx@linutronix.de,
	qianweili@huawei.com, wangzhou1@hisilicon.com,
	herbert@gondor.apana.org.au, Marc Zyngier <maz@kernel.org>,
	luzmaximilian@gmail.com, hdegoede@redhat.com,
	markgross@kernel.org, nathan@kernel.org, ndesaulniers@google.com,
	trix@redhat.com, rafael@kernel.org, davem@davemloft.net,
	rafael.j.wysocki@intel.com
Subject: Re: [PATCH V4 08/23] RISC-V: ACPI: Cache and retrieve the RINTC structure
Date: Thu, 27 Apr 2023 14:52:50 +0530	[thread overview]
Message-ID: <ZEo+6rwM+c6DvlMM@sunil-laptop> (raw)
In-Reply-To: <mhng-fd6c3622-ce6c-4895-8dc9-7dbaa2ab14f4@palmer-ri-x1c9a>

Hi Palmer,

On Wed, Apr 26, 2023 at 11:45:00AM -0700, Palmer Dabbelt wrote:
> On Tue, 04 Apr 2023 11:20:22 PDT (-0700), sunilvl@ventanamicro.com wrote:
> > RINTC structures in the MADT provide mapping between the hartid
> > and the CPU. This is required many times even at run time like
> > cpuinfo. So, instead of parsing the ACPI table every time, cache
> > the RINTC structures and provide a function to get the correct
> > RINTC structure for a given cpu.
> > 
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> > ---
> >  arch/riscv/include/asm/acpi.h |  2 ++
> >  arch/riscv/kernel/acpi.c      | 60 +++++++++++++++++++++++++++++++++++
> >  2 files changed, 62 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
> > index 9be52b6ffae1..1606dce8992e 100644
> > --- a/arch/riscv/include/asm/acpi.h
> > +++ b/arch/riscv/include/asm/acpi.h
> > @@ -59,6 +59,8 @@ static inline bool acpi_has_cpu_in_madt(void)
> > 
> >  static inline void arch_fix_phys_package_id(int num, u32 slot) { }
> > 
> > +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu);
> > +u32 get_acpi_id_for_cpu(int cpu);
> >  #endif /* CONFIG_ACPI */
> > 
> >  #endif /*_ASM_ACPI_H*/
> > diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c
> > index 81d448c41714..40ab55309c70 100644
> > --- a/arch/riscv/kernel/acpi.c
> > +++ b/arch/riscv/kernel/acpi.c
> > @@ -24,6 +24,66 @@ EXPORT_SYMBOL(acpi_disabled);
> >  int acpi_pci_disabled = 1;	/* skip ACPI PCI scan and IRQ initialization */
> >  EXPORT_SYMBOL(acpi_pci_disabled);
> > 
> > +static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS];
> > +
> > +static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end)
> > +{
> > +	struct acpi_madt_rintc *rintc = (struct acpi_madt_rintc *)header;
> > +	int cpuid;
> > +
> > +	if (!(rintc->flags & ACPI_MADT_ENABLED))
> > +		return 0;
> > +
> > +	cpuid = riscv_hartid_to_cpuid(rintc->hart_id);
> 
> Unless I'm missing something, this races with CPUs coming online.  Maybe
> that's a rare enough case we don't care, but I think we'd also just have
> simpler logic if we fixed it...
> 
This depend only on cpuid_to_hartid_map filled up. I wish I could
initialize this RINTC mapping in setup_smp() itself like ARM64. But in
RISC-V, this file smpboot.c gets built only when CONFIG_SMP is enabled.
Hence, we need to initialize this array outside of setup_smp().

I can update the code to initialize this from setup_arch() immediately
after setup_smp() if ACPI is enabled. That should avoid the global
variable check also. Let me know if you prefer this.

> > +	/*
> > +	 * When CONFIG_SMP is disabled, mapping won't be created for
> > +	 * all cpus.
> > +	 * CPUs more than NR_CPUS, will be ignored.
> > +	 */
> > +	if (cpuid >= 0 && cpuid < NR_CPUS)
> > +		cpu_madt_rintc[cpuid] = *rintc;
> > +
> > +	return 0;
> > +}
> > +
> > +static int acpi_init_rintc_array(void)
> > +{
> > +	if (acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_madt_rintc, 0) > 0)
> > +		return 0;
> > +
> > +	return -ENODEV;
> > +}
> > +
> > +/*
> > + * Instead of parsing (and freeing) the ACPI table, cache
> > + * the RINTC structures since they are frequently used
> > + * like in  cpuinfo.
> > + */
> > +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu)
> > +{
> > +	static bool rintc_init_done;
> 
> ... basically just get rid of this global variable, and instead have a
> 
>    if (!&cpu_madt_rintc[cpu])
>        ... parse ...
>    return &cpu_madt_rintc[cpu];
> 
> that'd probably let us get rid of a handful of these helpers too, as now
> it's just a call to the parsing bits.
> 
I am afraid this (!&cpu_madt_rintc[cpu]) check won't work since we are
not caching the RINTC pointers but actual contents itself. So, the
address is always valid. However, as per Drew's earlier feedback I am
going to reduce one helper. I am planning to send the next version of
this patch once 6.4 rc1 is available since the ACPICA patches are merged
now.

> > +
> > +	if (!rintc_init_done) {
> > +		if (acpi_init_rintc_array()) {
> > +			pr_err("No valid RINTC entries exist\n");
> > +			return NULL;
> > +		}
> > +
> > +		rintc_init_done = true;
> > +	}
> > +
> > +	return &cpu_madt_rintc[cpu];
> > +}
> > +
> > +u32 get_acpi_id_for_cpu(int cpu)
> > +{
> > +	struct acpi_madt_rintc *rintc = acpi_cpu_get_madt_rintc(cpu);
> > +
> > +	BUG_ON(!rintc);
> 
> We should have some better error reporting here.  It looks like all the
> callerss of get_acpi_id_for_cpu() are tolerant of a nonsense ID being
> returned, so maybe we just pr_warn() something users can understand and then
> return -1 or something?
> 

RINTC is mandatory for ACPI systems. Also, all 32bit values are valid
for UID. So, there is no bogus value we can return. 

Actually, I just realized this check is redundant. It will never be NULL
since it is a static array. So, we can just get rid of the BUG.

Thanks!
Sunil

  reply	other threads:[~2023-04-27  9:23 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-04 18:20 [PATCH V4 00/23] Add basic ACPI support for RISC-V Sunil V L
2023-04-04 18:20 ` [PATCH V4 01/23] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-04-04 18:20 ` [PATCH V4 02/23] ACPICA: MADT: Add RISC-V INTC interrupt controller Sunil V L
2023-04-04 18:20 ` [PATCH V4 03/23] ACPICA: Add structure definitions for RISC-V RHCT Sunil V L
2023-04-04 18:20 ` [PATCH V4 04/23] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-04-04 18:20 ` [PATCH V4 05/23] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-04-26 16:47   ` Björn Töpel
2023-04-27  9:27     ` Sunil V L
2023-04-27 11:24       ` Björn Töpel
2023-04-04 18:20 ` [PATCH V4 06/23] RISC-V: Add support to build the ACPI core Sunil V L
2023-04-26 18:44   ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 07/23] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-04-04 18:20 ` [PATCH V4 08/23] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-04-04 20:14   ` Conor Dooley
2023-04-05 15:17   ` Andrew Jones
2023-04-06  3:46     ` Sunil V L
2023-04-26 18:45   ` Palmer Dabbelt
2023-04-27  9:22     ` Sunil V L [this message]
2023-04-27 10:25       ` Andrew Jones
2023-04-27 10:52         ` Sunil V L
2023-04-27 13:13           ` Andrew Jones
2023-04-04 18:20 ` [PATCH V4 09/23] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-04-26 18:45   ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 10/23] RISC-V: smpboot: Create wrapper smp_setup() Sunil V L
2023-04-26 18:45   ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 11/23] RISC-V: smpboot: Add ACPI support in smp_setup() Sunil V L
2023-04-05 14:58   ` Andrew Jones
2023-04-04 18:20 ` [PATCH V4 12/23] RISC-V: cpufeature: Avoid calling riscv_of_processor_hartid() Sunil V L
2023-04-04 20:46   ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 13/23] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-04-04 20:57   ` Conor Dooley
2023-04-05 13:35     ` Sunil V L
2023-04-05 14:31       ` Conor Dooley
2023-04-05 15:37         ` Andrew Jones
2023-04-29 10:31   ` Conor Dooley
2023-05-02  1:28     ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 14/23] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-04-04 21:04   ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 15/23] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-04-05 15:48   ` Andrew Jones
2023-04-06  3:47     ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 16/23] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-04-04 21:25   ` Conor Dooley
2023-04-05 10:55     ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 17/23] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-04-04 21:27   ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 18/23] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-04-04 18:20 ` [PATCH V4 19/23] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-04-04 21:38   ` Conor Dooley
2023-04-05 15:11     ` Sunil V L
2023-04-05 15:30       ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 20/23] RISC-V: Enable ACPI in defconfig Sunil V L
2023-04-04 21:43   ` Conor Dooley
2023-04-05 10:58     ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 21/23] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-04-04 18:20 ` [PATCH V4 22/23] platform/surface: Disable for RISC-V Sunil V L
2023-04-05  4:19   ` Jessica Clarke
2023-04-05 11:29     ` Sunil V L
2023-04-05  9:33   ` Maximilian Luz
2023-04-05 11:11     ` Sunil V L
2023-04-05 11:35       ` Maximilian Luz
2023-04-04 18:20 ` [PATCH V4 23/23] crypto: hisilicon/qm: Workaround to enable build with RISC-V clang Sunil V L
2023-04-04 21:59   ` Conor Dooley
2023-04-05 10:46     ` Sunil V L
2023-04-05  8:16   ` Arnd Bergmann
2023-04-11 11:42     ` Weili Qian
2023-04-19 14:34       ` Arnd Bergmann
2023-04-04 18:42 ` [PATCH V4 00/23] Add basic ACPI support for RISC-V Conor Dooley

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