From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Sagar Karandikar <sagark@eecs.berkeley.edu>, QEMU devel <qemu-devel@nongnu.org>, QEMU riscv <qemu-riscv@nongnu.org> Subject: [Qemu-devel] [PATCH] riscv: rv32: Root page table address can be larger than 32-bit Date: Wed, 31 Jul 2019 05:45:01 -0700 Message-ID: <1564577101-29020-1-git-send-email-bmeng.cn@gmail.com> (raw) For RV32, the root page table's PPN has 22 bits hence its address bits could be larger than the maximum bits that target_ulong is able to represent. Use hwaddr instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- target/riscv/cpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e32b612..3150a6a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -176,7 +176,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, *prot = 0; - target_ulong base; + hwaddr base; int levels, ptidxbits, ptesize, vm, sum; int mxr = get_field(env->mstatus, MSTATUS_MXR); @@ -239,7 +239,7 @@ restart: ((1 << ptidxbits) - 1); /* check that physical address of PTE is legal */ - target_ulong pte_addr = base + idx * ptesize; + hwaddr pte_addr = base + idx * ptesize; if (riscv_feature(env, RISCV_FEATURE_PMP) && !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), -- 2.7.4
next reply index Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-31 12:45 Bin Meng [this message] 2019-07-31 17:35 ` Richard Henderson 2019-08-01 1:53 ` Bin Meng 2019-08-01 14:16 ` Richard Henderson 2019-08-01 14:57 ` Bin Meng 2019-08-07 20:55 ` Palmer Dabbelt 2019-08-08 1:49 ` Bin Meng 2019-08-08 2:49 ` [Qemu-devel] [PATCH v2] " Bin Meng 2019-08-10 1:49 ` Alistair Francis 2019-08-14 9:46 ` Bin Meng 2019-08-19 6:00 ` Bin Meng 2019-08-27 23:37 ` Palmer Dabbelt
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