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From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmer@sifive.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [Qemu-devel] [PATCH v2] riscv: rv32: Root page table address can be larger than 32-bit
Date: Fri, 9 Aug 2019 18:49:05 -0700
Message-ID: <CAKmqyKPQ0z-VtiebdtBqhBocgGkgeLLbtcawhwss0YpoYZyH2A@mail.gmail.com> (raw)
In-Reply-To: <1565232570-29296-1-git-send-email-bmeng.cn@gmail.com>

On Wed, Aug 7, 2019 at 7:50 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> For RV32, the root page table's PPN has 22 bits hence its address
> bits could be larger than the maximum bits that target_ulong is
> able to represent. Use hwaddr instead.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
> Changes in v2:
> - promote ppn, env->satp/env->sptbl to hwaddr otherwise the page
>   table base will not be correctly calculated
>
>  target/riscv/cpu_helper.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e32b612..b2b4f3a 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -176,12 +176,12 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>
>      *prot = 0;
>
> -    target_ulong base;
> +    hwaddr base;
>      int levels, ptidxbits, ptesize, vm, sum;
>      int mxr = get_field(env->mstatus, MSTATUS_MXR);
>
>      if (env->priv_ver >= PRIV_VERSION_1_10_0) {
> -        base = get_field(env->satp, SATP_PPN) << PGSHIFT;
> +        base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
>          sum = get_field(env->mstatus, MSTATUS_SUM);
>          vm = get_field(env->satp, SATP_MODE);
>          switch (vm) {
> @@ -201,7 +201,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>            g_assert_not_reached();
>          }
>      } else {
> -        base = env->sptbr << PGSHIFT;
> +        base = (hwaddr)(env->sptbr) << PGSHIFT;
>          sum = !get_field(env->mstatus, MSTATUS_PUM);
>          vm = get_field(env->mstatus, MSTATUS_VM);
>          switch (vm) {
> @@ -239,7 +239,7 @@ restart:
>                             ((1 << ptidxbits) - 1);
>
>          /* check that physical address of PTE is legal */
> -        target_ulong pte_addr = base + idx * ptesize;
> +        hwaddr pte_addr = base + idx * ptesize;
>
>          if (riscv_feature(env, RISCV_FEATURE_PMP) &&
>              !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
> @@ -251,7 +251,7 @@ restart:
>  #elif defined(TARGET_RISCV64)
>          target_ulong pte = ldq_phys(cs->as, pte_addr);
>  #endif
> -        target_ulong ppn = pte >> PTE_PPN_SHIFT;
> +        hwaddr ppn = pte >> PTE_PPN_SHIFT;
>
>          if (!(pte & PTE_V)) {
>              /* Invalid PTE */
> --
> 2.7.4
>
>


  reply index

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-31 12:45 [Qemu-devel] [PATCH] " Bin Meng
2019-07-31 17:35 ` Richard Henderson
2019-08-01  1:53   ` Bin Meng
2019-08-01 14:16     ` Richard Henderson
2019-08-01 14:57       ` Bin Meng
2019-08-07 20:55         ` Palmer Dabbelt
2019-08-08  1:49           ` Bin Meng
2019-08-08  2:49 ` [Qemu-devel] [PATCH v2] " Bin Meng
2019-08-10  1:49   ` Alistair Francis [this message]
2019-08-14  9:46     ` Bin Meng
2019-08-19  6:00       ` Bin Meng
2019-08-27 23:37         ` Palmer Dabbelt

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