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From: <tony.nguyen@bt.com>
To: <qemu-devel@nongnu.org>
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Subject: [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness
Date: Fri, 16 Aug 2019 07:38:04 +0000
Message-ID: <1565941083234.39909@bt.com> (raw)
In-Reply-To: <43bc5e07ac614d0e8e740bf6007ff77b@tpw09926dag18e.domain1.systemhost.net>

Preparation for collapsing the two byte swaps adjust_endianness and
handle_bswap into the former.

Call memory_region_dispatch_{read|write} with endianness encoded into
the "MemOp op" operand.

This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.

Once it does handle endianness, callers with byte swaps can collapse
them into adjust_endianness.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c       |  6 ++++--
 exec.c                   |  5 +++--
 hw/intc/armv7m_nvic.c    | 15 ++++++++-------
 hw/s390x/s390-pci-inst.c |  6 ++++--
 hw/vfio/pci-quirks.c     |  5 +++--
 hw/virtio/virtio-pci.c   |  6 ++++--
 memory_ldst.inc.c        | 18 ++++++++++++------
 7 files changed, 38 insertions(+), 23 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 6c83878..0aff6a3 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked = true;
     }
-    r = memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size),
+    r = memory_region_dispatch_read(mr, mr_offset, &val,
+                                    size_memop(size) | MO_TE,
                                     iotlbentry->attrs);
     if (r != MEMTX_OK) {
         hwaddr physaddr = mr_offset +
@@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked = true;
     }
-    r = memory_region_dispatch_write(mr, mr_offset, val, size_memop(size),
+    r = memory_region_dispatch_write(mr, mr_offset, val,
+                                     size_memop(size) | MO_TE,
                                      iotlbentry->attrs);
     if (r != MEMTX_OK) {
         hwaddr physaddr = mr_offset +
diff --git a/exec.c b/exec.c
index 303f9a7..562fb5b 100644
--- a/exec.c
+++ b/exec.c
@@ -3335,7 +3335,8 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
                potential bugs */
             val = ldn_p(buf, l);
             result |= memory_region_dispatch_write(mr, addr1, val,
-                                                   size_memop(l), attrs);
+                                                   size_memop(l) | MO_TE,
+                                                   attrs);
         } else {
             /* RAM case */
             ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false);
@@ -3397,7 +3398,7 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
             release_lock |= prepare_mmio_access(mr);
             l = memory_access_size(mr, l, addr1);
             result |= memory_region_dispatch_read(mr, addr1, &val,
-                                                  size_memop(l), attrs);
+                                                  size_memop(l) | MO_TE, attrs);
             stn_p(buf, l, val);
         } else {
             /* RAM case */
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 975d7cc..e150f9a 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2346,8 +2346,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr,
     if (attrs.secure) {
         /* S accesses to the alias act like NS accesses to the real region */
         attrs.secure = 0;
-        return memory_region_dispatch_write(mr, addr, value, size_memop(size),
-                                            attrs);
+        return memory_region_dispatch_write(mr, addr, value,
+                                            size_memop(size) | MO_TE, attrs);
     } else {
         /* NS attrs are RAZ/WI for privileged, and BusFault for user */
         if (attrs.user) {
@@ -2366,8 +2366,8 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr,
     if (attrs.secure) {
         /* S accesses to the alias act like NS accesses to the real region */
         attrs.secure = 0;
-        return memory_region_dispatch_read(mr, addr, data, size_memop(size),
-                                           attrs);
+        return memory_region_dispatch_read(mr, addr, data,
+                                           size_memop(size) | MO_TE, attrs);
     } else {
         /* NS attrs are RAZ/WI for privileged, and BusFault for user */
         if (attrs.user) {
@@ -2393,8 +2393,8 @@ static MemTxResult nvic_systick_write(void *opaque, hwaddr addr,

     /* Direct the access to the correct systick */
     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
-    return memory_region_dispatch_write(mr, addr, value, size_memop(size),
-                                        attrs);
+    return memory_region_dispatch_write(mr, addr, value,
+                                        size_memop(size) | MO_TE, attrs);
 }

 static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,
@@ -2406,7 +2406,8 @@ static MemTxResult nvic_systick_read(void *opaque, hwaddr addr,

     /* Direct the access to the correct systick */
     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]), 0);
-    return memory_region_dispatch_read(mr, addr, data, size_memop(size), attrs);
+    return memory_region_dispatch_read(mr, addr, data, size_memop(size) | MO_TE,
+                                       attrs);
 }

 static const MemoryRegionOps nvic_systick_ops = {
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 0e92a37..272cb28 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -373,7 +373,8 @@ static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
     mr = pbdev->pdev->io_regions[pcias].memory;
     mr = s390_get_subregion(mr, offset, len);
     offset -= mr->addr;
-    return memory_region_dispatch_read(mr, offset, data, size_memop(len),
+    return memory_region_dispatch_read(mr, offset, data,
+                                       size_memop(len) | MO_LE,
                                        MEMTXATTRS_UNSPECIFIED);
 }

@@ -472,7 +473,8 @@ static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias,
     mr = pbdev->pdev->io_regions[pcias].memory;
     mr = s390_get_subregion(mr, offset, len);
     offset -= mr->addr;
-    return memory_region_dispatch_write(mr, offset, data, size_memop(len),
+    return memory_region_dispatch_write(mr, offset, data,
+                                        size_memop(len) | MO_LE,
                                         MEMTXATTRS_UNSPECIFIED);
 }

diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c
index d5c0268..53db1c3 100644
--- a/hw/vfio/pci-quirks.c
+++ b/hw/vfio/pci-quirks.c
@@ -1072,7 +1072,8 @@ static void vfio_rtl8168_quirk_address_write(void *opaque, hwaddr addr,

                 /* Write to the proper guest MSI-X table instead */
                 memory_region_dispatch_write(&vdev->pdev.msix_table_mmio,
-                                             offset, val, size_memop(size),
+                                             offset, val,
+                                             size_memop(size) | MO_LE,
                                              MEMTXATTRS_UNSPECIFIED);
             }
             return; /* Do not write guest MSI-X data to hardware */
@@ -1103,7 +1104,7 @@ static uint64_t vfio_rtl8168_quirk_data_read(void *opaque,
     if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) {
         hwaddr offset = rtl->addr & 0xfff;
         memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset,
-                                    &data, size_memop(size),
+                                    &data, size_memop(size) | MO_LE,
                                     MEMTXATTRS_UNSPECIFIED);
         trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, data);
     }
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index b929e44..ad06c12 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -551,7 +551,8 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, hwaddr addr,
         /* As length is under guest control, handle illegal values. */
         return;
     }
-    memory_region_dispatch_write(mr, addr, val, size_memop(len),
+    /* FIXME: memory_region_dispatch_write ignores MO_BSWAP.  */
+    memory_region_dispatch_write(mr, addr, val, size_memop(len) | MO_LE,
                                  MEMTXATTRS_UNSPECIFIED);
 }

@@ -575,7 +576,8 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr addr,
     /* Make sure caller aligned buf properly */
     assert(!(((uintptr_t)buf) & (len - 1)));

-    memory_region_dispatch_read(mr, addr, &val, size_memop(len),
+    /* FIXME: memory_region_dispatch_read ignores MO_BSWAP.  */
+    memory_region_dispatch_read(mr, addr, &val, size_memop(len) | MO_LE,
                                 MEMTXATTRS_UNSPECIFIED);
     switch (len) {
     case 1:
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index d08fc79..482e4b3 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
         release_lock |= prepare_mmio_access(mr);

         /* I/O case */
-        r = memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_read ignores MO_BSWAP.  */
+        r = memory_region_dispatch_read(mr, addr1, &val, MO_32 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian == MO_LE) {
             val = bswap32(val);
@@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
         release_lock |= prepare_mmio_access(mr);

         /* I/O case */
-        r = memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_read ignores MO_BSWAP.  */
+        r = memory_region_dispatch_read(mr, addr1, &val, MO_64 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian == MO_LE) {
             val = bswap64(val);
@@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
         release_lock |= prepare_mmio_access(mr);

         /* I/O case */
-        r = memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_read ignores MO_BSWAP.  */
+        r = memory_region_dispatch_read(mr, addr1, &val, MO_16 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian == MO_LE) {
             val = bswap16(val);
@@ -342,7 +345,8 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
             val = bswap32(val);
         }
 #endif
-        r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_write ignores MO_BSWAP.  */
+        r = memory_region_dispatch_write(mr, addr1, val, MO_32 | endian, attrs);
     } else {
         /* RAM case */
         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -447,7 +451,8 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
             val = bswap16(val);
         }
 #endif
-        r = memory_region_dispatch_write(mr, addr1, val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_write ignores MO_BSWAP.  */
+        r = memory_region_dispatch_write(mr, addr1, val, MO_16 | endian, attrs);
     } else {
         /* RAM case */
         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
@@ -520,7 +525,8 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
             val = bswap64(val);
         }
 #endif
-        r = memory_region_dispatch_write(mr, addr1, val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_write ignores MO_BSWAP.  */
+        r = memory_region_dispatch_write(mr, addr1, val, MO_64 | endian, attrs);
     } else {
         /* RAM case */
         ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
--
1.8.3.1

?


  parent reply index

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-16  6:28 [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
2019-08-16  7:08 ` [Qemu-devel] [PATCH v7 01/42] configure: Define TARGET_ALIGNED_ONLY tony.nguyen
2019-08-16  7:26 ` [Qemu-devel] [PATCH v7 02/42] tcg: TCGMemOp is now accelerator independent MemOp tony.nguyen
2019-08-16  7:27 ` [Qemu-devel] [PATCH v7 03/42] memory: Introduce size_memop tony.nguyen
2019-08-16  7:27 ` [Qemu-devel] [PATCH v7 04/42] target/mips: Access MemoryRegion with MemOp tony.nguyen
2019-08-16  7:28 ` [Qemu-devel] [PATCH v7 05/42] hw/s390x: " tony.nguyen
2019-08-16  7:28 ` [Qemu-devel] [PATCH v7 06/42] hw/intc/armv7m_nic: " tony.nguyen
2019-08-16  7:28 ` [Qemu-devel] [PATCH v7 07/42] hw/virtio: " tony.nguyen
2019-08-16  7:29 ` [Qemu-devel] [PATCH v7 08/42] hw/vfio: " tony.nguyen
2019-08-16  7:29 ` [Qemu-devel] [PATCH v7 09/42] exec: " tony.nguyen
2019-08-16  7:30 ` [Qemu-devel] [PATCH v7 10/42] cputlb: " tony.nguyen
2019-08-16  7:30 ` [Qemu-devel] [PATCH v7 11/42] memory: " tony.nguyen
2019-08-18 21:44   ` Philippe Mathieu-Daudé
2019-08-16  7:30 ` [Qemu-devel] [PATCH v7 12/42] hw/s390x: Hard code size with MO_{8|16|32|64} tony.nguyen
2019-08-16  7:31 ` [Qemu-devel] [PATCH v7 13/42] target/mips: " tony.nguyen
2019-08-16  7:31 ` [Qemu-devel] [PATCH v7 14/42] exec: " tony.nguyen
2019-08-16  7:31 ` [Qemu-devel] [PATCH v7 15/42] hw/audio: Declare device little or big endian tony.nguyen
2019-08-16  7:32 ` [Qemu-devel] [PATCH v7 16/42] hw/block: " tony.nguyen
2019-08-16  7:32 ` [Qemu-devel] [PATCH v7 17/42] hw/char: " tony.nguyen
2019-08-16  7:32 ` [Qemu-devel] [PATCH v7 18/42] hw/display: " tony.nguyen
2019-08-16  7:33 ` [Qemu-devel] [PATCH v7 19/42] hw/dma: " tony.nguyen
2019-08-16  7:33 ` [Qemu-devel] [PATCH v7 20/42] hw/gpio: " tony.nguyen
2019-08-16  7:33 ` [Qemu-devel] [PATCH v7 21/42] hw/i2c: " tony.nguyen
2019-08-16  7:33 ` [Qemu-devel] [PATCH v7 22/42] hw/input: " tony.nguyen
2019-08-16  7:34 ` [Qemu-devel] [PATCH v7 23/42] hw/intc: " tony.nguyen
2019-08-16  7:34 ` [Qemu-devel] [PATCH v7 24/42] hw/isa: " tony.nguyen
2019-08-16 10:01   ` Philippe Mathieu-Daudé
2019-08-16  7:34 ` [Qemu-devel] [PATCH v7 25/42] hw/misc: " tony.nguyen
2019-08-16 10:04   ` Philippe Mathieu-Daudé
2019-08-19 18:26     ` Paolo Bonzini
2019-08-16  7:35 ` [Qemu-devel] [PATCH v7 26/42] hw/net: " tony.nguyen
2019-08-16  7:35 ` [Qemu-devel] [PATCH v7 27/42] hw/pci-host: " tony.nguyen
2019-08-16 10:06   ` Philippe Mathieu-Daudé
2019-08-16  7:35 ` [Qemu-devel] [PATCH v7 28/42] hw/sd: " tony.nguyen
2019-08-16  7:35 ` [Qemu-devel] [PATCH v7 29/42] hw/ssi: " tony.nguyen
2019-08-16  7:36 ` [Qemu-devel] [PATCH v7 30/42] hw/timer: " tony.nguyen
2019-08-16  7:36 ` [Qemu-devel] [PATCH v7 31/42] build: Correct non-common common-obj-* to obj-* tony.nguyen
2019-08-16  7:36 ` [Qemu-devel] [PATCH v7 32/42] exec: Map device_endian onto MemOp tony.nguyen
2019-08-16  7:37 ` [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp tony.nguyen
2019-08-16 10:12   ` [Qemu-devel] [qemu-s390x] " Thomas Huth
2019-08-19 18:28     ` Paolo Bonzini
2019-08-19 18:29       ` Paolo Bonzini
2019-08-19 21:01         ` Richard Henderson
2019-08-20  3:11           ` Edgar E. Iglesias
2019-08-16  7:37 ` [Qemu-devel] [PATCH v7 34/42] exec: Delete device_endian tony.nguyen
2019-08-16  7:37 ` [Qemu-devel] [PATCH v7 35/42] exec: Delete DEVICE_HOST_ENDIAN tony.nguyen
2019-08-16  7:38 ` tony.nguyen [this message]
2019-08-18 12:22   ` [Qemu-devel] [PATCH v7 36/42] memory: Access MemoryRegion with endianness Richard Henderson
2019-08-16  7:38 ` [Qemu-devel] [PATCH v7 37/42] cputlb: Replace size and endian operands for MemOp tony.nguyen
2019-08-18 12:37   ` Richard Henderson
2019-08-16  7:38 ` [Qemu-devel] [PATCH v7 38/42] memory: Single byte swap along the I/O path tony.nguyen
2019-08-18 12:46   ` Richard Henderson
2019-08-16  7:39 ` [Qemu-devel] [PATCH v7 39/42] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen
2019-08-16  7:39 ` [Qemu-devel] [PATCH v7 40/42] cputlb: Byte swap memory transaction attribute tony.nguyen
2019-08-16  7:39 ` [Qemu-devel] [PATCH v7 41/42] target/sparc: Add TLB entry with attributes tony.nguyen
2019-08-16  7:39 ` [Qemu-devel] [PATCH v7 42/42] target/sparc: sun4u Invert Endian TTE bit tony.nguyen
2019-08-16  8:03 ` [Qemu-devel] [PATCH v7 33/42] exec: Replace device_endian with MemOp tony.nguyen
2019-08-16  9:33 ` tony.nguyen
2019-08-16  9:58 ` [Qemu-devel] [PATCH v7 00/42] Invert Endian bit in SPARCv9 MMU TTE Philippe Mathieu-Daudé
2019-08-16 11:37   ` tony.nguyen
2019-08-16 12:02     ` Peter Maydell
2019-08-16 11:43   ` David Gibson
2019-08-18  9:13 ` Richard Henderson

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