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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PATCH v8 20/37] target/mips: Clean up handling of CP0 register 5
Date: Mon, 19 Aug 2019 14:07:59 +0200	[thread overview]
Message-ID: <1566216496-17375-21-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com>

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Clean up handling of CP0 register 5.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/cpu.h       |  6 +++++
 target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
 2 files changed, 38 insertions(+), 32 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index eebdc9f..2ab388b 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -312,6 +312,12 @@ typedef struct mips_def_t mips_def_t;
 /* CP0 Register 05 */
 #define CP0_REG05__PAGEMASK        0
 #define CP0_REG05__PAGEGRAIN       1
+#define CP0_REG05__SEGCTL0         2
+#define CP0_REG05__SEGCTL1         3
+#define CP0_REG05__SEGCTL2         4
+#define CP0_REG05__PWBASE          5
+#define CP0_REG05__PWFIELD         6
+#define CP0_REG05__PWSIZE          7
 /* CP0 Register 06 */
 #define CP0_REG06__WIRED           0
 /* CP0 Register 07 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6e65312..9d1e315 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7042,44 +7042,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_05:
         switch (sel) {
-        case 0:
+        case CP0_REG05__PAGEMASK:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
             register_name = "PageMask";
             break;
-        case 1:
+        case CP0_REG05__PAGEGRAIN:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
             register_name = "PageGrain";
             break;
-        case 2:
+        case CP0_REG05__SEGCTL0:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
             tcg_gen_ext32s_tl(arg, arg);
             register_name = "SegCtl0";
             break;
-        case 3:
+        case CP0_REG05__SEGCTL1:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
             tcg_gen_ext32s_tl(arg, arg);
             register_name = "SegCtl1";
             break;
-        case 4:
+        case CP0_REG05__SEGCTL2:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
             tcg_gen_ext32s_tl(arg, arg);
             register_name = "SegCtl2";
             break;
-        case 5:
+        case CP0_REG05__PWBASE:
             check_pw(ctx);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
             register_name = "PWBase";
             break;
-        case 6:
+        case CP0_REG05__PWFIELD:
             check_pw(ctx);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
             register_name = "PWField";
             break;
-        case 7:
+        case CP0_REG05__PWSIZE:
             check_pw(ctx);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
             register_name = "PWSize";
@@ -7783,42 +7783,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_05:
         switch (sel) {
-        case 0:
+        case CP0_REG05__PAGEMASK:
             gen_helper_mtc0_pagemask(cpu_env, arg);
             register_name = "PageMask";
             break;
-        case 1:
+        case CP0_REG05__PAGEGRAIN:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_pagegrain(cpu_env, arg);
             register_name = "PageGrain";
             ctx->base.is_jmp = DISAS_STOP;
             break;
-        case 2:
+        case CP0_REG05__SEGCTL0:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl0(cpu_env, arg);
             register_name = "SegCtl0";
             break;
-        case 3:
+        case CP0_REG05__SEGCTL1:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl1(cpu_env, arg);
             register_name = "SegCtl1";
             break;
-        case 4:
+        case CP0_REG05__SEGCTL2:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl2(cpu_env, arg);
             register_name = "SegCtl2";
             break;
-        case 5:
+        case CP0_REG05__PWBASE:
             check_pw(ctx);
             gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
             register_name = "PWBase";
             break;
-        case 6:
+        case CP0_REG05__PWFIELD:
             check_pw(ctx);
             gen_helper_mtc0_pwfield(cpu_env, arg);
             register_name = "PWField";
             break;
-        case 7:
+        case CP0_REG05__PWSIZE:
             check_pw(ctx);
             gen_helper_mtc0_pwsize(cpu_env, arg);
             register_name = "PWSize";
@@ -8534,41 +8534,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_05:
         switch (sel) {
-        case 0:
+        case CP0_REG05__PAGEMASK:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
             register_name = "PageMask";
             break;
-        case 1:
+        case CP0_REG05__PAGEGRAIN:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
             register_name = "PageGrain";
             break;
-        case 2:
+        case CP0_REG05__SEGCTL0:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
             register_name = "SegCtl0";
             break;
-        case 3:
+        case CP0_REG05__SEGCTL1:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
             register_name = "SegCtl1";
             break;
-        case 4:
+        case CP0_REG05__SEGCTL2:
             CP0_CHECK(ctx->sc);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
             register_name = "SegCtl2";
             break;
-        case 5:
+        case CP0_REG05__PWBASE:
             check_pw(ctx);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
             register_name = "PWBase";
             break;
-        case 6:
+        case CP0_REG05__PWFIELD:
             check_pw(ctx);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
             register_name = "PWField";
             break;
-        case 7:
+        case CP0_REG05__PWSIZE:
             check_pw(ctx);
             tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
             register_name = "PWSize";
@@ -9255,41 +9255,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_05:
         switch (sel) {
-        case 0:
+        case CP0_REG05__PAGEMASK:
             gen_helper_mtc0_pagemask(cpu_env, arg);
             register_name = "PageMask";
             break;
-        case 1:
+        case CP0_REG05__PAGEGRAIN:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_pagegrain(cpu_env, arg);
             register_name = "PageGrain";
             break;
-        case 2:
+        case CP0_REG05__SEGCTL0:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl0(cpu_env, arg);
             register_name = "SegCtl0";
             break;
-        case 3:
+        case CP0_REG05__SEGCTL1:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl1(cpu_env, arg);
             register_name = "SegCtl1";
             break;
-        case 4:
+        case CP0_REG05__SEGCTL2:
             CP0_CHECK(ctx->sc);
             gen_helper_mtc0_segctl2(cpu_env, arg);
             register_name = "SegCtl2";
             break;
-        case 5:
+        case CP0_REG05__PWBASE:
             check_pw(ctx);
             tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
             register_name = "PWBase";
             break;
-        case 6:
+        case CP0_REG05__PWFIELD:
             check_pw(ctx);
             gen_helper_mtc0_pwfield(cpu_env, arg);
             register_name = "PWField";
             break;
-        case 7:
+        case CP0_REG05__PWSIZE:
             check_pw(ctx);
             gen_helper_mtc0_pwsize(cpu_env, arg);
             register_name = "PWSize";
-- 
2.7.4



  parent reply	other threads:[~2019-08-19 12:21 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-19 12:07 [Qemu-devel] [PATCH v8 00/37] target/mips: Misc patches for 4.2 Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 01/37] target/mips: Add support for DSPRAM Aleksandar Markovic
2019-08-29 11:27   ` Philippe Mathieu-Daudé
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 02/37] target/mips: Amend CP0 WatchHi register implementation Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 03/37] target/mips: Amend CP0 MemoryMapID " Aleksandar Markovic
2019-08-19 14:39   ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 04/37] target/mips: Add support for emulation of GINVT instruction Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 05/37] target/mips: Add support for emulation of CRC32 group of instructions Aleksandar Markovic
2019-10-22  9:16   ` Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 06/37] target/mips: Style improvements in cp0_timer.c Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 07/37] target/mips: Style improvements in cpu.c Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 08/37] target/mips: Style improvements in internal.h Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 09/37] target/mips: Style improvements in machine.c Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 10/37] target/mips: Style improvements in helper.c Aleksandar Markovic
2019-08-19 13:33   ` Thomas Huth
2019-08-19 13:56     ` [Qemu-devel] [EXTERNAL]Re: " Aleksandar Markovic
2019-08-19 14:40   ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 11/37] target/mips: Style improvements in translate.c Aleksandar Markovic
2019-08-19 14:41   ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 12/37] target/mips: Style improvements in cps.c Aleksandar Markovic
2019-08-19 14:44   ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 13/37] target/mips: Style improvements in mips_fulong2e.c Aleksandar Markovic
2019-08-19 14:45   ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 14/37] target/mips: Style improvements in mips_int.c Aleksandar Markovic
2019-08-19 14:46   ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 15/37] target/mips: Style improvements in mips_malta.c Aleksandar Markovic
2019-08-19 14:47   ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-12-06 17:46     ` [PATCH " Philippe Mathieu-Daudé
2019-12-06 19:45       ` [Qemu-devel] " Aleksandar Markovic
2019-12-07  6:20         ` Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 16/37] target/mips: Style improvements in mips_mipssim.c Aleksandar Markovic
2019-08-19 14:48   ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 17/37] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 18/37] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 19/37] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-19 12:07 ` Aleksandar Markovic [this message]
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 21/37] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 22/37] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 23/37] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 24/37] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 25/37] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 26/37] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 27/37] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 28/37] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 29/37] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 30/37] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 31/37] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 32/37] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 33/37] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 34/37] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 35/37] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 36/37] target/mips: tests/tcg: Add optional printing of more detailed failure info Aleksandar Markovic
2019-08-19 14:49   ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 37/37] target/mips: tests/tcg: Fix target configurations for MSA tests Aleksandar Markovic
2019-08-19 14:50   ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo

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