From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PATCH v8 08/37] target/mips: Style improvements in internal.h
Date: Mon, 19 Aug 2019 14:07:47 +0200 [thread overview]
Message-ID: <1566216496-17375-9-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1566216496-17375-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/mips/internal.h | 57 +++++++++++++++++++++++++++++++-------------------
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index d9216fb..836de7a 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -1,4 +1,5 @@
-/* mips internal definitions and helpers
+/*
+ * MIPS internal definitions and helpers
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@@ -8,8 +9,10 @@
#define MIPS_INTERNAL_H
-/* MMU types, the first four entries have the same layout as the
- CP0C0_MT field. */
+/*
+ * MMU types, the first four entries have the same layout as the
+ * CP0C0_MT field.
+ */
enum mips_mmu_types {
MMU_TYPE_NONE,
MMU_TYPE_R4000,
@@ -159,9 +162,11 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM) &&
- /* Note that the TCStatus IXMT field is initialized to zero,
- and only MT capable cores can set it to one. So we don't
- need to check for MT capabilities here. */
+ /*
+ * Note that the TCStatus IXMT field is initialized to zero,
+ * and only MT capable cores can set it to one. So we don't
+ * need to check for MT capabilities here.
+ */
!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
}
@@ -176,14 +181,18 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
status = env->CP0_Status & CP0Ca_IP_mask;
if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
- /* A MIPS configured with a vectorizing external interrupt controller
- will feed a vector into the Cause pending lines. The core treats
- the status lines as a vector level, not as indiviual masks. */
+ /*
+ * A MIPS configured with a vectorizing external interrupt controller
+ * will feed a vector into the Cause pending lines. The core treats
+ * the status lines as a vector level, not as indiviual masks.
+ */
r = pending > status;
} else {
- /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
- treats the pending lines as individual interrupt lines, the status
- lines are individual masks. */
+ /*
+ * A MIPS configured with compatibility or VInt (Vectored Interrupts)
+ * treats the pending lines as individual interrupt lines, the status
+ * lines are individual masks.
+ */
r = (pending & status) != 0;
}
return r;
@@ -268,12 +277,14 @@ static inline int mips_vpe_active(CPUMIPSState *env)
active = 0;
}
- /* Now verify that there are active thread contexts in the VPE.
-
- This assumes the CPU model will internally reschedule threads
- if the active one goes to sleep. If there are no threads available
- the active one will be in a sleeping state, and we can turn off
- the entire VPE. */
+ /*
+ * Now verify that there are active thread contexts in the VPE.
+ *
+ * This assumes the CPU model will internally reschedule threads
+ * if the active one goes to sleep. If there are no threads available
+ * the active one will be in a sleeping state, and we can turn off
+ * the entire VPE.
+ */
if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
/* TC is not activated. */
active = 0;
@@ -396,10 +407,12 @@ static inline void compute_hflags(CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_COP1X;
}
} else if (env->insn_flags & ISA_MIPS4) {
- /* All supported MIPS IV CPUs use the XX (CU3) to enable
- and disable the MIPS IV extensions to the MIPS III ISA.
- Some other MIPS IV CPUs ignore the bit, so the check here
- would be too restrictive for them. */
+ /*
+ * All supported MIPS IV CPUs use the XX (CU3) to enable
+ * and disable the MIPS IV extensions to the MIPS III ISA.
+ * Some other MIPS IV CPUs ignore the bit, so the check here
+ * would be too restrictive for them.
+ */
if (env->CP0_Status & (1U << CP0St_CU3)) {
env->hflags |= MIPS_HFLAG_COP1X;
}
--
2.7.4
next prev parent reply other threads:[~2019-08-19 12:14 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-19 12:07 [Qemu-devel] [PATCH v8 00/37] target/mips: Misc patches for 4.2 Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 01/37] target/mips: Add support for DSPRAM Aleksandar Markovic
2019-08-29 11:27 ` Philippe Mathieu-Daudé
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 02/37] target/mips: Amend CP0 WatchHi register implementation Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 03/37] target/mips: Amend CP0 MemoryMapID " Aleksandar Markovic
2019-08-19 14:39 ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 04/37] target/mips: Add support for emulation of GINVT instruction Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 05/37] target/mips: Add support for emulation of CRC32 group of instructions Aleksandar Markovic
2019-10-22 9:16 ` Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 06/37] target/mips: Style improvements in cp0_timer.c Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 07/37] target/mips: Style improvements in cpu.c Aleksandar Markovic
2019-08-19 12:07 ` Aleksandar Markovic [this message]
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 09/37] target/mips: Style improvements in machine.c Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 10/37] target/mips: Style improvements in helper.c Aleksandar Markovic
2019-08-19 13:33 ` Thomas Huth
2019-08-19 13:56 ` [Qemu-devel] [EXTERNAL]Re: " Aleksandar Markovic
2019-08-19 14:40 ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 11/37] target/mips: Style improvements in translate.c Aleksandar Markovic
2019-08-19 14:41 ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 12/37] target/mips: Style improvements in cps.c Aleksandar Markovic
2019-08-19 14:44 ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 13/37] target/mips: Style improvements in mips_fulong2e.c Aleksandar Markovic
2019-08-19 14:45 ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 14/37] target/mips: Style improvements in mips_int.c Aleksandar Markovic
2019-08-19 14:46 ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 15/37] target/mips: Style improvements in mips_malta.c Aleksandar Markovic
2019-08-19 14:47 ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-12-06 17:46 ` [PATCH " Philippe Mathieu-Daudé
2019-12-06 19:45 ` [Qemu-devel] " Aleksandar Markovic
2019-12-07 6:20 ` Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 16/37] target/mips: Style improvements in mips_mipssim.c Aleksandar Markovic
2019-08-19 14:48 ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 17/37] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 18/37] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 19/37] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-19 12:07 ` [Qemu-devel] [PATCH v8 20/37] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 21/37] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 22/37] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 23/37] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 24/37] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 25/37] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 26/37] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 27/37] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 28/37] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 29/37] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 30/37] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 31/37] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 32/37] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 33/37] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 34/37] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 35/37] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 36/37] target/mips: tests/tcg: Add optional printing of more detailed failure info Aleksandar Markovic
2019-08-19 14:49 ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
2019-08-19 12:08 ` [Qemu-devel] [PATCH v8 37/37] target/mips: tests/tcg: Fix target configurations for MSA tests Aleksandar Markovic
2019-08-19 14:50 ` [Qemu-devel] [EXTERNAL][PATCH " Aleksandar Rikalo
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