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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PATCH 13/26] target/mips: Clean up handling of CP0 register 16
Date: Thu, 22 Aug 2019 13:35:37 +0200	[thread overview]
Message-ID: <1566473750-17743-14-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com>

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Clean up handling of CP0 register 16.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/cpu.h       |  3 ++-
 target/mips/translate.c | 60 ++++++++++++++++++++++++-------------------------
 2 files changed, 32 insertions(+), 31 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3a8c560..625d364 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -371,7 +371,8 @@ typedef struct mips_def_t mips_def_t;
 #define CP0_REG16__CONFIG3         3
 #define CP0_REG16__CONFIG4         4
 #define CP0_REG16__CONFIG5         5
-#define CP0_REG00__CONFIG7         7
+#define CP0_REG16__CONFIG6         6
+#define CP0_REG16__CONFIG7         7
 /* CP0 Register 17 */
 #define CP0_REG17__LLADDR          0
 #define CP0_REG17__MAAR            1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 97a274a..7878fcb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7293,36 +7293,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_16:
         switch (sel) {
-        case 0:
+        case CP0_REG16__CONFIG:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
             register_name = "Config";
             break;
-        case 1:
+        case CP0_REG16__CONFIG1:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
             register_name = "Config1";
             break;
-        case 2:
+        case CP0_REG16__CONFIG2:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
             register_name = "Config2";
             break;
-        case 3:
+        case CP0_REG16__CONFIG3:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
             register_name = "Config3";
             break;
-        case 4:
+        case CP0_REG16__CONFIG4:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
             register_name = "Config4";
             break;
-        case 5:
+        case CP0_REG16__CONFIG5:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
             register_name = "Config5";
             break;
         /* 6,7 are implementation dependent */
-        case 6:
+        case CP0_REG16__CONFIG6:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
             register_name = "Config6";
             break;
-        case 7:
+        case CP0_REG16__CONFIG7:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
             register_name = "Config7";
             break;
@@ -8022,45 +8022,45 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_16:
         switch (sel) {
-        case 0:
+        case CP0_REG16__CONFIG:
             gen_helper_mtc0_config0(cpu_env, arg);
             register_name = "Config";
             /* Stop translation as we may have switched the execution mode */
             ctx->base.is_jmp = DISAS_STOP;
             break;
-        case 1:
+        case CP0_REG16__CONFIG1:
             /* ignored, read only */
             register_name = "Config1";
             break;
-        case 2:
+        case CP0_REG16__CONFIG2:
             gen_helper_mtc0_config2(cpu_env, arg);
             register_name = "Config2";
             /* Stop translation as we may have switched the execution mode */
             ctx->base.is_jmp = DISAS_STOP;
             break;
-        case 3:
+        case CP0_REG16__CONFIG3:
             gen_helper_mtc0_config3(cpu_env, arg);
             register_name = "Config3";
             /* Stop translation as we may have switched the execution mode */
             ctx->base.is_jmp = DISAS_STOP;
             break;
-        case 4:
+        case CP0_REG16__CONFIG4:
             gen_helper_mtc0_config4(cpu_env, arg);
             register_name = "Config4";
             ctx->base.is_jmp = DISAS_STOP;
             break;
-        case 5:
+        case CP0_REG16__CONFIG5:
             gen_helper_mtc0_config5(cpu_env, arg);
             register_name = "Config5";
             /* Stop translation as we may have switched the execution mode */
             ctx->base.is_jmp = DISAS_STOP;
             break;
         /* 6,7 are implementation dependent */
-        case 6:
+        case CP0_REG16__CONFIG6:
             /* ignored */
             register_name = "Config6";
             break;
-        case 7:
+        case CP0_REG16__CONFIG7:
             /* ignored */
             register_name = "Config7";
             break;
@@ -8777,36 +8777,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_16:
         switch (sel) {
-        case 0:
+        case CP0_REG16__CONFIG:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
             register_name = "Config";
             break;
-        case 1:
+        case CP0_REG16__CONFIG1:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
             register_name = "Config1";
             break;
-        case 2:
+        case CP0_REG16__CONFIG2:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
             register_name = "Config2";
             break;
-        case 3:
+        case CP0_REG16__CONFIG3:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
             register_name = "Config3";
             break;
-        case 4:
+        case CP0_REG16__CONFIG4:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
             register_name = "Config4";
             break;
-        case 5:
+        case CP0_REG16__CONFIG5:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
             register_name = "Config5";
             break;
        /* 6,7 are implementation dependent */
-        case 6:
+        case CP0_REG16__CONFIG6:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
             register_name = "Config6";
             break;
-        case 7:
+        case CP0_REG16__CONFIG7:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
             register_name = "Config7";
             break;
@@ -9497,33 +9497,33 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_16:
         switch (sel) {
-        case 0:
+        case CP0_REG16__CONFIG:
             gen_helper_mtc0_config0(cpu_env, arg);
             register_name = "Config";
             /* Stop translation as we may have switched the execution mode */
             ctx->base.is_jmp = DISAS_STOP;
             break;
-        case 1:
+        case CP0_REG16__CONFIG1:
             /* ignored, read only */
             register_name = "Config1";
             break;
-        case 2:
+        case CP0_REG16__CONFIG2:
             gen_helper_mtc0_config2(cpu_env, arg);
             register_name = "Config2";
             /* Stop translation as we may have switched the execution mode */
             ctx->base.is_jmp = DISAS_STOP;
             break;
-        case 3:
+        case CP0_REG16__CONFIG3:
             gen_helper_mtc0_config3(cpu_env, arg);
             register_name = "Config3";
             /* Stop translation as we may have switched the execution mode */
             ctx->base.is_jmp = DISAS_STOP;
             break;
-        case 4:
+        case CP0_REG16__CONFIG4:
             /* currently ignored */
             register_name = "Config4";
             break;
-        case 5:
+        case CP0_REG16__CONFIG5:
             gen_helper_mtc0_config5(cpu_env, arg);
             register_name = "Config5";
             /* Stop translation as we may have switched the execution mode */
-- 
2.7.4



  parent reply	other threads:[~2019-08-22 11:53 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-22 11:35 [Qemu-devel] [PATCH 00/26] Clean up handling of configuration register CP0 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 01/26] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 02/26] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 03/26] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 04/26] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 05/26] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 06/26] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 07/26] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 08/26] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 09/26] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 10/26] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 11/26] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 12/26] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
2019-08-22 11:35 ` Aleksandar Markovic [this message]
2019-08-22 11:35 ` [Qemu-devel] [PATCH 14/26] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 15/26] target/mips: Clean up handling of CP0 register 18 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 16/26] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 17/26] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 18/26] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 19/26] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 20/26] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 21/26] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 22/26] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 23/26] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 24/26] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 25/26] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 26/26] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic

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