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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PATCH 05/26] target/mips: Clean up handling of CP0 register 6
Date: Thu, 22 Aug 2019 13:35:29 +0200	[thread overview]
Message-ID: <1566473750-17743-6-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com>

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Clean up handling of CP0 register 6.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/cpu.h       |  6 ++++++
 target/mips/translate.c | 56 ++++++++++++++++++++++++-------------------------
 2 files changed, 34 insertions(+), 28 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 2ab388b..c865b51 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -320,6 +320,12 @@ typedef struct mips_def_t mips_def_t;
 #define CP0_REG05__PWSIZE          7
 /* CP0 Register 06 */
 #define CP0_REG06__WIRED           0
+#define CP0_REG06__SRSCONF0        1
+#define CP0_REG06__SRSCONF1        2
+#define CP0_REG06__SRSCONF2        3
+#define CP0_REG06__SRSCONF3        4
+#define CP0_REG06__SRSCONF4        5
+#define CP0_REG06__PWCTL           6
 /* CP0 Register 07 */
 #define CP0_REG07__HWRENA          0
 /* CP0 Register 08 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9d1e315..cdcc1cc 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7090,36 +7090,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_06:
         switch (sel) {
-        case 0:
+        case CP0_REG06__WIRED:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
             register_name = "Wired";
             break;
-        case 1:
+        case CP0_REG06__SRSCONF0:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
             register_name = "SRSConf0";
             break;
-        case 2:
+        case CP0_REG06__SRSCONF1:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
             register_name = "SRSConf1";
             break;
-        case 3:
+        case CP0_REG06__SRSCONF2:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
             register_name = "SRSConf2";
             break;
-        case 4:
+        case CP0_REG06__SRSCONF3:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
             register_name = "SRSConf3";
             break;
-        case 5:
+        case CP0_REG06__SRSCONF4:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
             register_name = "SRSConf4";
             break;
-        case 6:
+        case CP0_REG06__PWCTL:
             check_pw(ctx);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
             register_name = "PWCtl";
@@ -7829,36 +7829,36 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_06:
         switch (sel) {
-        case 0:
+        case CP0_REG06__WIRED:
             gen_helper_mtc0_wired(cpu_env, arg);
             register_name = "Wired";
             break;
-        case 1:
+        case CP0_REG06__SRSCONF0:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf0(cpu_env, arg);
             register_name = "SRSConf0";
             break;
-        case 2:
+        case CP0_REG06__SRSCONF1:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf1(cpu_env, arg);
             register_name = "SRSConf1";
             break;
-        case 3:
+        case CP0_REG06__SRSCONF2:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf2(cpu_env, arg);
             register_name = "SRSConf2";
             break;
-        case 4:
+        case CP0_REG06__SRSCONF3:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf3(cpu_env, arg);
             register_name = "SRSConf3";
             break;
-        case 5:
+        case CP0_REG06__SRSCONF4:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf4(cpu_env, arg);
             register_name = "SRSConf4";
             break;
-        case 6:
+        case CP0_REG06__PWCTL:
             check_pw(ctx);
             gen_helper_mtc0_pwctl(cpu_env, arg);
             register_name = "PWCtl";
@@ -8579,36 +8579,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_06:
         switch (sel) {
-        case 0:
+        case CP0_REG06__WIRED:
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
             register_name = "Wired";
             break;
-        case 1:
+        case CP0_REG06__SRSCONF0:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
             register_name = "SRSConf0";
             break;
-        case 2:
+        case CP0_REG06__SRSCONF1:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
             register_name = "SRSConf1";
             break;
-        case 3:
+        case CP0_REG06__SRSCONF2:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
             register_name = "SRSConf2";
             break;
-        case 4:
+        case CP0_REG06__SRSCONF3:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
             register_name = "SRSConf3";
             break;
-        case 5:
+        case CP0_REG06__SRSCONF4:
             check_insn(ctx, ISA_MIPS32R2);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
             register_name = "SRSConf4";
             break;
-        case 6:
+        case CP0_REG06__PWCTL:
             check_pw(ctx);
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
             register_name = "PWCtl";
@@ -9300,36 +9300,36 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_06:
         switch (sel) {
-        case 0:
+        case CP0_REG06__WIRED:
             gen_helper_mtc0_wired(cpu_env, arg);
             register_name = "Wired";
             break;
-        case 1:
+        case CP0_REG06__SRSCONF0:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf0(cpu_env, arg);
             register_name = "SRSConf0";
             break;
-        case 2:
+        case CP0_REG06__SRSCONF1:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf1(cpu_env, arg);
             register_name = "SRSConf1";
             break;
-        case 3:
+        case CP0_REG06__SRSCONF2:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf2(cpu_env, arg);
             register_name = "SRSConf2";
             break;
-        case 4:
+        case CP0_REG06__SRSCONF3:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf3(cpu_env, arg);
             register_name = "SRSConf3";
             break;
-        case 5:
+        case CP0_REG06__SRSCONF4:
             check_insn(ctx, ISA_MIPS32R2);
             gen_helper_mtc0_srsconf4(cpu_env, arg);
             register_name = "SRSConf4";
             break;
-        case 6:
+        case CP0_REG06__PWCTL:
             check_pw(ctx);
             gen_helper_mtc0_pwctl(cpu_env, arg);
             register_name = "PWCtl";
-- 
2.7.4



  parent reply	other threads:[~2019-08-22 11:49 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-22 11:35 [Qemu-devel] [PATCH 00/26] Clean up handling of configuration register CP0 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 01/26] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 02/26] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 03/26] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 04/26] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
2019-08-22 11:35 ` Aleksandar Markovic [this message]
2019-08-22 11:35 ` [Qemu-devel] [PATCH 06/26] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 07/26] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 08/26] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 09/26] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 10/26] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 11/26] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 12/26] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 13/26] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 14/26] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 15/26] target/mips: Clean up handling of CP0 register 18 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 16/26] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 17/26] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 18/26] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 19/26] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 20/26] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 21/26] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 22/26] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 23/26] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 24/26] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 25/26] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 26/26] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic

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