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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PATCH 15/26] target/mips: Clean up handling of CP0 register 18
Date: Thu, 22 Aug 2019 13:35:39 +0200	[thread overview]
Message-ID: <1566473750-17743-16-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1566473750-17743-1-git-send-email-aleksandar.markovic@rt-rk.com>

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Clean up handling of CP0 register 18.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/cpu.h       | 20 +++++++++-------
 target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
 2 files changed, 44 insertions(+), 40 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 625d364..b18c87b 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -194,14 +194,14 @@ typedef struct mips_def_t mips_def_t;
  *     Register 16       Register 17       Register 18       Register 19
  *     -----------       -----------       -----------       -----------
  *
- * 0   Config            LLAddr            WatchLo           WatchHi
- * 1   Config1           MAAR              WatchLo           WatchHi
- * 2   Config2           MAARI             WatchLo           WatchHi
- * 3   Config3                             WatchLo           WatchHi
- * 4   Config4                             WatchLo           WatchHi
- * 5   Config5                             WatchLo           WatchHi
- * 6                                       WatchLo           WatchHi
- * 7                                       WatchLo           WatchHi
+ * 0   Config            LLAddr            WatchLo0          WatchHi
+ * 1   Config1           MAAR              WatchLo1          WatchHi
+ * 2   Config2           MAARI             WatchLo2          WatchHi
+ * 3   Config3                             WatchLo3          WatchHi
+ * 4   Config4                             WatchLo4          WatchHi
+ * 5   Config5                             WatchLo5          WatchHi
+ * 6                                       WatchLo6          WatchHi
+ * 7                                       WatchLo7          WatchHi
  *
  *
  *     Register 20       Register 21       Register 22       Register 23
@@ -382,6 +382,10 @@ typedef struct mips_def_t mips_def_t;
 #define CP0_REG18__WATCHLO1        1
 #define CP0_REG18__WATCHLO2        2
 #define CP0_REG18__WATCHLO3        3
+#define CP0_REG18__WATCHLO4        4
+#define CP0_REG18__WATCHLO5        5
+#define CP0_REG18__WATCHLO6        6
+#define CP0_REG18__WATCHLO7        7
 /* CP0 Register 19 */
 #define CP0_REG19__WATCHHI0        0
 #define CP0_REG19__WATCHHI1        1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 51c8d29..8c66db4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7352,14 +7352,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_18:
         switch (sel) {
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-        case 6:
-        case 7:
+        case CP0_REG18__WATCHLO0:
+        case CP0_REG18__WATCHLO1:
+        case CP0_REG18__WATCHLO2:
+        case CP0_REG18__WATCHLO3:
+        case CP0_REG18__WATCHLO4:
+        case CP0_REG18__WATCHLO5:
+        case CP0_REG18__WATCHLO6:
+        case CP0_REG18__WATCHLO7:
             CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
             gen_helper_1e0i(mfc0_watchlo, arg, sel);
             register_name = "WatchLo";
@@ -8091,14 +8091,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_18:
         switch (sel) {
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-        case 6:
-        case 7:
+        case CP0_REG18__WATCHLO0:
+        case CP0_REG18__WATCHLO1:
+        case CP0_REG18__WATCHLO2:
+        case CP0_REG18__WATCHLO3:
+        case CP0_REG18__WATCHLO4:
+        case CP0_REG18__WATCHLO5:
+        case CP0_REG18__WATCHLO6:
+        case CP0_REG18__WATCHLO7:
             CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
             gen_helper_0e1i(mtc0_watchlo, arg, sel);
             register_name = "WatchLo";
@@ -8836,14 +8836,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_18:
         switch (sel) {
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-        case 6:
-        case 7:
+        case CP0_REG18__WATCHLO0:
+        case CP0_REG18__WATCHLO1:
+        case CP0_REG18__WATCHLO2:
+        case CP0_REG18__WATCHLO3:
+        case CP0_REG18__WATCHLO4:
+        case CP0_REG18__WATCHLO5:
+        case CP0_REG18__WATCHLO6:
+        case CP0_REG18__WATCHLO7:
             CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
             gen_helper_1e0i(dmfc0_watchlo, arg, sel);
             register_name = "WatchLo";
@@ -9557,14 +9557,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_18:
         switch (sel) {
-        case 0:
-        case 1:
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-        case 6:
-        case 7:
+        case CP0_REG18__WATCHLO0:
+        case CP0_REG18__WATCHLO1:
+        case CP0_REG18__WATCHLO2:
+        case CP0_REG18__WATCHLO3:
+        case CP0_REG18__WATCHLO4:
+        case CP0_REG18__WATCHLO5:
+        case CP0_REG18__WATCHLO6:
+        case CP0_REG18__WATCHLO7:
             CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
             gen_helper_0e1i(mtc0_watchlo, arg, sel);
             register_name = "WatchLo";
-- 
2.7.4



  parent reply	other threads:[~2019-08-22 11:56 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-22 11:35 [Qemu-devel] [PATCH 00/26] Clean up handling of configuration register CP0 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 01/26] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 02/26] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 03/26] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 04/26] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 05/26] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 06/26] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 07/26] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 08/26] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 09/26] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 10/26] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 11/26] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 12/26] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 13/26] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 14/26] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
2019-08-22 11:35 ` Aleksandar Markovic [this message]
2019-08-22 11:35 ` [Qemu-devel] [PATCH 16/26] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 17/26] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 18/26] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 19/26] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 20/26] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 21/26] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 22/26] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 23/26] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 24/26] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 25/26] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-22 11:35 ` [Qemu-devel] [PATCH 26/26] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic

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