From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PULL 19/31] target/mips: Clean up handling of CP0 register 18
Date: Thu, 29 Aug 2019 12:25:01 +0200 [thread overview]
Message-ID: <1567074313-22998-20-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1567074313-22998-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 18.
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-20-git-send-email-aleksandar.markovic@rt-rk.com>
---
target/mips/cpu.h | 20 +++++++++-------
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 44 insertions(+), 40 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d6405ad..d6ea111 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -192,14 +192,14 @@ typedef struct mips_def_t mips_def_t;
* Register 16 Register 17 Register 18 Register 19
* ----------- ----------- ----------- -----------
*
- * 0 Config LLAddr WatchLo WatchHi
- * 1 Config1 MAAR WatchLo WatchHi
- * 2 Config2 MAARI WatchLo WatchHi
- * 3 Config3 WatchLo WatchHi
- * 4 Config4 WatchLo WatchHi
- * 5 Config5 WatchLo WatchHi
- * 6 WatchLo WatchHi
- * 7 WatchLo WatchHi
+ * 0 Config LLAddr WatchLo0 WatchHi
+ * 1 Config1 MAAR WatchLo1 WatchHi
+ * 2 Config2 MAARI WatchLo2 WatchHi
+ * 3 Config3 WatchLo3 WatchHi
+ * 4 Config4 WatchLo4 WatchHi
+ * 5 Config5 WatchLo5 WatchHi
+ * 6 WatchLo6 WatchHi
+ * 7 WatchLo7 WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
@@ -386,6 +386,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG18__WATCHLO1 1
#define CP0_REG18__WATCHLO2 2
#define CP0_REG18__WATCHLO3 3
+#define CP0_REG18__WATCHLO4 4
+#define CP0_REG18__WATCHLO5 5
+#define CP0_REG18__WATCHLO6 6
+#define CP0_REG18__WATCHLO7 7
/* CP0 Register 19 */
#define CP0_REG19__WATCHHI0 0
#define CP0_REG19__WATCHHI1 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index edeaaad..6a11e8d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7305,14 +7305,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8040,14 +8040,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8777,14 +8777,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -9494,14 +9494,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
--
2.7.4
next prev parent reply other threads:[~2019-08-29 10:39 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 02/31] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 04/31] target/mips: Clean up handling of CP0 register 3 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 14/31] target/mips: Clean up handling of CP0 register 13 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 17/31] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 18/31] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
2019-08-29 10:25 ` Aleksandar Markovic [this message]
2019-08-29 10:25 ` [Qemu-devel] [PULL 20/31] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 21/31] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 22/31] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 23/31] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 25/31] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 26/31] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 27/31] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 28/31] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 29/31] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 30/31] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 31/31] target/mips: Fix emulation of ST.W in system mode Aleksandar Markovic
2019-09-04 10:24 ` [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Peter Maydell
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