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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PULL 30/31] target/mips: Clean up handling of CP0 register 31
Date: Thu, 29 Aug 2019 12:25:12 +0200	[thread overview]
Message-ID: <1567074313-22998-31-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1567074313-22998-1-git-send-email-aleksandar.markovic@rt-rk.com>

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Clean up handling of CP0 register 31.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-31-git-send-email-aleksandar.markovic@rt-rk.com>
---
 target/mips/cpu.h       |  2 +-
 target/mips/translate.c | 56 ++++++++++++++++++++++++-------------------------
 2 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 6defbea..ca00f41 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -613,7 +613,6 @@ struct CPUMIPSState {
  * CP0 Register 4
  */
     target_ulong CP0_Context;
-    target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
     int32_t CP0_MemoryMapID;
 /*
  * CP0 Register 5
@@ -1024,6 +1023,7 @@ struct CPUMIPSState {
  * CP0 Register 31
  */
     int32_t CP0_DESAVE;
+    target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 
     /* We waste some space so we can handle shadow registers like TCs. */
     TCState tcs[MIPS_SHADOW_SET_MAX];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 93f7a20..f6d1424 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7532,17 +7532,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_31:
         switch (sel) {
-        case 0:
+        case CP0_REG31__DESAVE:
             /* EJTAG support */
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
             register_name = "DESAVE";
             break;
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-        case 6:
-        case 7:
+        case CP0_REG31__KSCRATCH1:
+        case CP0_REG31__KSCRATCH2:
+        case CP0_REG31__KSCRATCH3:
+        case CP0_REG31__KSCRATCH4:
+        case CP0_REG31__KSCRATCH5:
+        case CP0_REG31__KSCRATCH6:
             CP0_CHECK(ctx->kscrexist & (1 << sel));
             tcg_gen_ld_tl(arg, cpu_env,
                           offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -8282,17 +8282,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_31:
         switch (sel) {
-        case 0:
+        case CP0_REG31__DESAVE:
             /* EJTAG support */
             gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
             register_name = "DESAVE";
             break;
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-        case 6:
-        case 7:
+        case CP0_REG31__KSCRATCH1:
+        case CP0_REG31__KSCRATCH2:
+        case CP0_REG31__KSCRATCH3:
+        case CP0_REG31__KSCRATCH4:
+        case CP0_REG31__KSCRATCH5:
+        case CP0_REG31__KSCRATCH6:
             CP0_CHECK(ctx->kscrexist & (1 << sel));
             tcg_gen_st_tl(arg, cpu_env,
                           offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9009,17 +9009,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_31:
         switch (sel) {
-        case 0:
+        case CP0_REG31__DESAVE:
             /* EJTAG support */
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
             register_name = "DESAVE";
             break;
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-        case 6:
-        case 7:
+        case CP0_REG31__KSCRATCH1:
+        case CP0_REG31__KSCRATCH2:
+        case CP0_REG31__KSCRATCH3:
+        case CP0_REG31__KSCRATCH4:
+        case CP0_REG31__KSCRATCH5:
+        case CP0_REG31__KSCRATCH6:
             CP0_CHECK(ctx->kscrexist & (1 << sel));
             tcg_gen_ld_tl(arg, cpu_env,
                           offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9746,17 +9746,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         break;
     case CP0_REGISTER_31:
         switch (sel) {
-        case 0:
+        case CP0_REG31__DESAVE:
             /* EJTAG support */
             gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
             register_name = "DESAVE";
             break;
-        case 2:
-        case 3:
-        case 4:
-        case 5:
-        case 6:
-        case 7:
+        case CP0_REG31__KSCRATCH1:
+        case CP0_REG31__KSCRATCH2:
+        case CP0_REG31__KSCRATCH3:
+        case CP0_REG31__KSCRATCH4:
+        case CP0_REG31__KSCRATCH5:
+        case CP0_REG31__KSCRATCH6:
             CP0_CHECK(ctx->kscrexist & (1 << sel));
             tcg_gen_st_tl(arg, cpu_env,
                           offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
-- 
2.7.4



  parent reply	other threads:[~2019-08-29 10:59 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-29 10:24 [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 02/31] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 04/31] target/mips: Clean up handling of CP0 register 3 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 14/31] target/mips: Clean up handling of CP0 register 13 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15 Aleksandar Markovic
2019-08-29 10:24 ` [Qemu-devel] [PULL 17/31] target/mips: Clean up handling of CP0 register 16 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 18/31] target/mips: Clean up handling of CP0 register 17 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 19/31] target/mips: Clean up handling of CP0 register 18 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 20/31] target/mips: Clean up handling of CP0 register 19 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 21/31] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 22/31] target/mips: Clean up handling of CP0 register 23 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 23/31] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 25/31] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 26/31] target/mips: Clean up handling of CP0 register 27 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 27/31] target/mips: Clean up handling of CP0 register 28 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 28/31] target/mips: Clean up handling of CP0 register 29 Aleksandar Markovic
2019-08-29 10:25 ` [Qemu-devel] [PULL 29/31] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-29 10:25 ` Aleksandar Markovic [this message]
2019-08-29 10:25 ` [Qemu-devel] [PULL 31/31] target/mips: Fix emulation of ST.W in system mode Aleksandar Markovic
2019-09-04 10:24 ` [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019 Peter Maydell

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