* [PATCH] target/i386: add support for MSR_IA32_TSX_CTRL
@ 2019-11-20 12:19 Paolo Bonzini
2019-11-20 12:59 ` no-reply
2019-11-20 20:04 ` Eduardo Habkost
0 siblings, 2 replies; 3+ messages in thread
From: Paolo Bonzini @ 2019-11-20 12:19 UTC (permalink / raw)
To: qemu-devel; +Cc: ehabkost
The MSR_IA32_TSX_CTRL MSR can be used to hide TSX (also known as the
Trusty Side-channel Extension). By virtualizing the MSR, KVM guests
can disable TSX and avoid paying the price of mitigating TSX-based
attacks on microarchitectural side channels.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 2 +-
target/i386/cpu.h | 5 +++++
target/i386/kvm.c | 13 +++++++++++++
target/i386/machine.c | 20 ++++++++++++++++++++
4 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 296b491607..8447f4b82c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1204,7 +1204,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = MSR_FEATURE_WORD,
.feat_names = {
"rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
- "ssb-no", "mds-no", "pschange-mc-no", NULL,
+ "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
"taa-no", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 5352c9ff55..cde2a16b94 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -349,7 +349,11 @@ typedef enum X86Seg {
#define MSR_VIRT_SSBD 0xc001011f
#define MSR_IA32_PRED_CMD 0x49
#define MSR_IA32_CORE_CAPABILITY 0xcf
+
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
+#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
+
+#define MSR_IA32_TSX_CTRL 0x122
#define MSR_IA32_TSCDEADLINE 0x6e0
#define FEATURE_CONTROL_LOCKED (1<<0)
@@ -1449,6 +1453,7 @@ typedef struct CPUX86State {
uint64_t msr_smi_count;
uint32_t pkru;
+ uint32_t tsx_ctrl;
uint64_t spec_ctrl;
uint64_t virt_ssbd;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index bfd09bd441..bf1655645b 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -97,6 +97,7 @@ static bool has_msr_hv_reenlightenment;
static bool has_msr_xss;
static bool has_msr_umwait;
static bool has_msr_spec_ctrl;
+static bool has_msr_tsx_ctrl;
static bool has_msr_virt_ssbd;
static bool has_msr_smi_count;
static bool has_msr_arch_capabs;
@@ -2036,6 +2037,9 @@ static int kvm_get_supported_msrs(KVMState *s)
case MSR_IA32_SPEC_CTRL:
has_msr_spec_ctrl = true;
break;
+ case MSR_IA32_TSX_CTRL:
+ has_msr_tsx_ctrl = true;
+ break;
case MSR_VIRT_SSBD:
has_msr_virt_ssbd = true;
break;
@@ -2694,6 +2698,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
}
+ if (has_msr_tsx_ctrl) {
+ kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
+ }
if (has_msr_virt_ssbd) {
kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
}
@@ -3110,6 +3117,9 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
}
+ if (has_msr_tsx_ctrl) {
+ kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
+ }
if (has_msr_virt_ssbd) {
kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
}
@@ -3502,6 +3512,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_SPEC_CTRL:
env->spec_ctrl = msrs[i].data;
break;
+ case MSR_IA32_TSX_CTRL:
+ env->tsx_ctrl = msrs[i].data;
+ break;
case MSR_VIRT_SSBD:
env->virt_ssbd = msrs[i].data;
break;
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 7bdeb78157..2699eed94e 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -1293,6 +1293,25 @@ static const VMStateDescription vmstate_efer32 = {
};
#endif
+static bool msr_tsx_ctrl_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return env->features[FEAT_ARCH_CAPABILITIES] & ARCH_CAP_TSX_CTRL_MSR;
+}
+
+static const VMStateDescription vmstate_msr_tsx_ctrl = {
+ .name = "cpu/msr_tsx_ctrl",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = msr_tsx_ctrl_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(env.tsx_ctrl, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -1427,6 +1446,7 @@ VMStateDescription vmstate_x86_cpu = {
#ifdef CONFIG_KVM
&vmstate_nested_state,
#endif
+ &vmstate_msr_tsx_ctrl,
NULL
}
};
--
2.21.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] target/i386: add support for MSR_IA32_TSX_CTRL
2019-11-20 12:19 [PATCH] target/i386: add support for MSR_IA32_TSX_CTRL Paolo Bonzini
@ 2019-11-20 12:59 ` no-reply
2019-11-20 20:04 ` Eduardo Habkost
1 sibling, 0 replies; 3+ messages in thread
From: no-reply @ 2019-11-20 12:59 UTC (permalink / raw)
To: pbonzini; +Cc: qemu-devel, ehabkost
Patchew URL: https://patchew.org/QEMU/20191120121922.6082-1-pbonzini@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH] target/i386: add support for MSR_IA32_TSX_CTRL
Type: series
Message-id: 20191120121922.6082-1-pbonzini@redhat.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Switched to a new branch 'test'
995694e target/i386: add support for MSR_IA32_TSX_CTRL
=== OUTPUT BEGIN ===
ERROR: code indent should never use tabs
#38: FILE: target/i386/cpu.h:354:
+#define ARCH_CAP_TSX_CTRL_MSR^I^I(1<<7)$
ERROR: spaces required around that '<<' (ctx:VxV)
#38: FILE: target/i386/cpu.h:354:
+#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
^
ERROR: code indent should never use tabs
#40: FILE: target/i386/cpu.h:356:
+#define MSR_IA32_TSX_CTRL^I^I0x122$
total: 3 errors, 0 warnings, 101 lines checked
Commit 995694ea43f9 (target/i386: add support for MSR_IA32_TSX_CTRL) has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20191120121922.6082-1-pbonzini@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] target/i386: add support for MSR_IA32_TSX_CTRL
2019-11-20 12:19 [PATCH] target/i386: add support for MSR_IA32_TSX_CTRL Paolo Bonzini
2019-11-20 12:59 ` no-reply
@ 2019-11-20 20:04 ` Eduardo Habkost
1 sibling, 0 replies; 3+ messages in thread
From: Eduardo Habkost @ 2019-11-20 20:04 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel
On Wed, Nov 20, 2019 at 01:19:22PM +0100, Paolo Bonzini wrote:
> The MSR_IA32_TSX_CTRL MSR can be used to hide TSX (also known as the
> Trusty Side-channel Extension). By virtualizing the MSR, KVM guests
> can disable TSX and avoid paying the price of mitigating TSX-based
> attacks on microarchitectural side channels.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Minor suggestion, though: replacing the tabs below with spaces:
[...]
> +#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
[...]
> +#define MSR_IA32_TSX_CTRL 0x122
--
Eduardo
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-11-20 20:05 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-20 12:19 [PATCH] target/i386: add support for MSR_IA32_TSX_CTRL Paolo Bonzini
2019-11-20 12:59 ` no-reply
2019-11-20 20:04 ` Eduardo Habkost
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).