From: RTOS Pharos <1815721@bugs.launchpad.net>
To: qemu-devel@nongnu.org
Subject: [Bug 1815721] Re: RISC-V PLIC enable interrupt for multicore
Date: Wed, 25 Mar 2020 17:04:44 -0000 [thread overview]
Message-ID: <158515588475.8334.16690140737637770701.malone@wampee.canonical.com> (raw)
In-Reply-To: 155004342499.19242.14077661245921319117.malonedeb@soybean.canonical.com
Thank you for the explanation. I actually built it for "Virt" machine.
I'll try the "sifive_u" when I can.
But I guess your explanation is correct so this bug could be closed from
my part.
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https://bugs.launchpad.net/bugs/1815721
Title:
RISC-V PLIC enable interrupt for multicore
Status in QEMU:
New
Bug description:
Hello all,
There is a bug in Qemu related to the enabling of external interrupts
for multicores (Virt machine).
After correcting Qemu as described in #1815078
(https://bugs.launchpad.net/qemu/+bug/1815078), when we try to enable
interrupts for core 1 at address 0x0C00_2080 we don't seem to be able
to trigger an external interrupt (e.g. UART0).
This works perfectly for core 0, but fore core 1 it does not work at
all. I assume that given bug #1815078 does not enable any external
interrupt then this feature has not been tested. I tried to look at
the qemu source code but with no luck so far.
I guess the problem is related to function parse_hart_config (in
sfive_plic.c) that initializes incorrectly the
plic->addr_config[addrid].hartid, which is later on read in
sifive_plic_update. But this is a guess.
Best regards,
Pharos team
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next prev parent reply other threads:[~2020-03-25 17:17 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-13 7:37 [Qemu-devel] [Bug 1815721] [NEW] RISC-V PLIC enable interrupt for multicore RTOS Pharos
2020-03-24 8:14 ` [Bug 1815721] " RTOS Pharos
2020-03-24 10:35 ` Bin Meng
2020-03-24 10:35 ` Bin Meng
2020-03-25 17:04 ` RTOS Pharos [this message]
2020-09-28 7:15 ` Teodori Serge
2020-11-19 20:24 ` Alistair Francis
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