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* [Qemu-devel] [Bug 1815721] [NEW] RISC-V PLIC enable interrupt for multicore
@ 2019-02-13  7:37 RTOS Pharos
  2020-03-24  8:14 ` [Bug 1815721] " RTOS Pharos
  2020-03-25 17:04 ` RTOS Pharos
  0 siblings, 2 replies; 5+ messages in thread
From: RTOS Pharos @ 2019-02-13  7:37 UTC (permalink / raw)
  To: qemu-devel

Public bug reported:

Hello all,

There is a bug in Qemu related to the enabling of external interrupts
for multicores (Virt machine).

After correcting Qemu as described in #1815078
(https://bugs.launchpad.net/qemu/+bug/1815078), when we try to enable
interrupts for core 1 at address 0x0C00_2080 we don't seem to be able to
trigger an external interrupt  (e.g. UART0).

This works perfectly for core 0, but fore core 1 it does not work at
all. I assume that given bug #1815078 does not enable any external
interrupt then this feature has not been tested. I tried to look at the
qemu source code but with no luck so far.

I guess the problem is related to function parse_hart_config (in
sfive_plic.c) that initializes incorrectly the
plic->addr_config[addrid].hartid, which is later on read in
sifive_plic_update. But this is a guess.

Best regards,
Pharos team

** Affects: qemu
     Importance: Undecided
         Status: New

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1815721

Title:
  RISC-V PLIC enable interrupt for multicore

Status in QEMU:
  New

Bug description:
  Hello all,

  There is a bug in Qemu related to the enabling of external interrupts
  for multicores (Virt machine).

  After correcting Qemu as described in #1815078
  (https://bugs.launchpad.net/qemu/+bug/1815078), when we try to enable
  interrupts for core 1 at address 0x0C00_2080 we don't seem to be able
  to trigger an external interrupt  (e.g. UART0).

  This works perfectly for core 0, but fore core 1 it does not work at
  all. I assume that given bug #1815078 does not enable any external
  interrupt then this feature has not been tested. I tried to look at
  the qemu source code but with no luck so far.

  I guess the problem is related to function parse_hart_config (in
  sfive_plic.c) that initializes incorrectly the
  plic->addr_config[addrid].hartid, which is later on read in
  sifive_plic_update. But this is a guess.

  Best regards,
  Pharos team

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1815721/+subscriptions

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Bug 1815721] Re: RISC-V PLIC enable interrupt for multicore
  2019-02-13  7:37 [Qemu-devel] [Bug 1815721] [NEW] RISC-V PLIC enable interrupt for multicore RTOS Pharos
@ 2020-03-24  8:14 ` RTOS Pharos
  2020-03-24 10:35   ` Bin Meng
  2020-03-25 17:04 ` RTOS Pharos
  1 sibling, 1 reply; 5+ messages in thread
From: RTOS Pharos @ 2020-03-24  8:14 UTC (permalink / raw)
  To: qemu-devel

Hi,

After some debugging (and luck), the problem (at least in the Virt
board) was that the PLIC code inside QEMU addresses the core x 2 instead
of just the core (core=hart). That is why it worked for core 0 (0x2 = 0)
but for core 1 it has to address the PLIC memory area for core 2.

For example, the interrupt enable address for core 1 starts at offset
0x002080 (see https://github.com/riscv/riscv-plic-spec/blob/master
/riscv-plic.adoc) but we actually have to change the enable bit for core
2 (at 0x002100) to make to work for core 1.

The same is true for the priority threshold and claim complete registers
(we need to multiply the core by 2)

Either the documentation at https://github.com/riscv/riscv-plic-
spec/blob/master/riscv-plic.adoc does not have the correct memory
addresses for qemu virt board, or qemu appears to be wrong.

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1815721

Title:
  RISC-V PLIC enable interrupt for multicore

Status in QEMU:
  New

Bug description:
  Hello all,

  There is a bug in Qemu related to the enabling of external interrupts
  for multicores (Virt machine).

  After correcting Qemu as described in #1815078
  (https://bugs.launchpad.net/qemu/+bug/1815078), when we try to enable
  interrupts for core 1 at address 0x0C00_2080 we don't seem to be able
  to trigger an external interrupt  (e.g. UART0).

  This works perfectly for core 0, but fore core 1 it does not work at
  all. I assume that given bug #1815078 does not enable any external
  interrupt then this feature has not been tested. I tried to look at
  the qemu source code but with no luck so far.

  I guess the problem is related to function parse_hart_config (in
  sfive_plic.c) that initializes incorrectly the
  plic->addr_config[addrid].hartid, which is later on read in
  sifive_plic_update. But this is a guess.

  Best regards,
  Pharos team

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1815721/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Bug 1815721] Re: RISC-V PLIC enable interrupt for multicore
  2020-03-24  8:14 ` [Bug 1815721] " RTOS Pharos
@ 2020-03-24 10:35   ` Bin Meng
  2020-03-24 10:35     ` Bin Meng
  0 siblings, 1 reply; 5+ messages in thread
From: Bin Meng @ 2020-03-24 10:35 UTC (permalink / raw)
  To: Bug 1815721; +Cc: qemu-devel@nongnu.org Developers

On Tue, Mar 24, 2020 at 4:20 PM RTOS Pharos <1815721@bugs.launchpad.net> wrote:
>
> Hi,
>
> After some debugging (and luck), the problem (at least in the Virt
> board) was that the PLIC code inside QEMU addresses the core x 2 instead
> of just the core (core=hart). That is why it worked for core 0 (0x2 = 0)
> but for core 1 it has to address the PLIC memory area for core 2.
>
> For example, the interrupt enable address for core 1 starts at offset
> 0x002080 (see https://github.com/riscv/riscv-plic-spec/blob/master
> /riscv-plic.adoc) but we actually have to change the enable bit for core
> 2 (at 0x002100) to make to work for core 1.


https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc says:

"base + 0x002080: Enable bits for sources 0-31 on context 1"

This is context 1, not core 1.

It looks to me you were running an image built for SiFive FU540.
Please test your image against "sifive_u" machine instead.

>
> The same is true for the priority threshold and claim complete registers
> (we need to multiply the core by 2)
>
> Either the documentation at https://github.com/riscv/riscv-plic-
> spec/blob/master/riscv-plic.adoc does not have the correct memory
> addresses for qemu virt board, or qemu appears to be wrong.
>
> --

Regards,
Bin


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Bug 1815721] Re: RISC-V PLIC enable interrupt for multicore
  2020-03-24 10:35   ` Bin Meng
@ 2020-03-24 10:35     ` Bin Meng
  0 siblings, 0 replies; 5+ messages in thread
From: Bin Meng @ 2020-03-24 10:35 UTC (permalink / raw)
  To: qemu-devel

On Tue, Mar 24, 2020 at 4:20 PM RTOS Pharos <1815721@bugs.launchpad.net> wrote:
>
> Hi,
>
> After some debugging (and luck), the problem (at least in the Virt
> board) was that the PLIC code inside QEMU addresses the core x 2 instead
> of just the core (core=hart). That is why it worked for core 0 (0x2 = 0)
> but for core 1 it has to address the PLIC memory area for core 2.
>
> For example, the interrupt enable address for core 1 starts at offset
> 0x002080 (see https://github.com/riscv/riscv-plic-spec/blob/master
> /riscv-plic.adoc) but we actually have to change the enable bit for core
> 2 (at 0x002100) to make to work for core 1.


https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc says:

"base + 0x002080: Enable bits for sources 0-31 on context 1"

This is context 1, not core 1.

It looks to me you were running an image built for SiFive FU540.
Please test your image against "sifive_u" machine instead.

>
> The same is true for the priority threshold and claim complete registers
> (we need to multiply the core by 2)
>
> Either the documentation at https://github.com/riscv/riscv-plic-
> spec/blob/master/riscv-plic.adoc does not have the correct memory
> addresses for qemu virt board, or qemu appears to be wrong.
>
> --

Regards,
Bin

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1815721

Title:
  RISC-V PLIC enable interrupt for multicore

Status in QEMU:
  New

Bug description:
  Hello all,

  There is a bug in Qemu related to the enabling of external interrupts
  for multicores (Virt machine).

  After correcting Qemu as described in #1815078
  (https://bugs.launchpad.net/qemu/+bug/1815078), when we try to enable
  interrupts for core 1 at address 0x0C00_2080 we don't seem to be able
  to trigger an external interrupt  (e.g. UART0).

  This works perfectly for core 0, but fore core 1 it does not work at
  all. I assume that given bug #1815078 does not enable any external
  interrupt then this feature has not been tested. I tried to look at
  the qemu source code but with no luck so far.

  I guess the problem is related to function parse_hart_config (in
  sfive_plic.c) that initializes incorrectly the
  plic->addr_config[addrid].hartid, which is later on read in
  sifive_plic_update. But this is a guess.

  Best regards,
  Pharos team

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1815721/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Bug 1815721] Re: RISC-V PLIC enable interrupt for multicore
  2019-02-13  7:37 [Qemu-devel] [Bug 1815721] [NEW] RISC-V PLIC enable interrupt for multicore RTOS Pharos
  2020-03-24  8:14 ` [Bug 1815721] " RTOS Pharos
@ 2020-03-25 17:04 ` RTOS Pharos
  1 sibling, 0 replies; 5+ messages in thread
From: RTOS Pharos @ 2020-03-25 17:04 UTC (permalink / raw)
  To: qemu-devel

Thank you for the explanation. I actually built it for "Virt" machine.
I'll try the "sifive_u" when I can.

But I guess your explanation is correct so this bug could be closed from
my part.

-- 
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1815721

Title:
  RISC-V PLIC enable interrupt for multicore

Status in QEMU:
  New

Bug description:
  Hello all,

  There is a bug in Qemu related to the enabling of external interrupts
  for multicores (Virt machine).

  After correcting Qemu as described in #1815078
  (https://bugs.launchpad.net/qemu/+bug/1815078), when we try to enable
  interrupts for core 1 at address 0x0C00_2080 we don't seem to be able
  to trigger an external interrupt  (e.g. UART0).

  This works perfectly for core 0, but fore core 1 it does not work at
  all. I assume that given bug #1815078 does not enable any external
  interrupt then this feature has not been tested. I tried to look at
  the qemu source code but with no luck so far.

  I guess the problem is related to function parse_hart_config (in
  sfive_plic.c) that initializes incorrectly the
  plic->addr_config[addrid].hartid, which is later on read in
  sifive_plic_update. But this is a guess.

  Best regards,
  Pharos team

To manage notifications about this bug go to:
https://bugs.launchpad.net/qemu/+bug/1815721/+subscriptions


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, back to index

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-02-13  7:37 [Qemu-devel] [Bug 1815721] [NEW] RISC-V PLIC enable interrupt for multicore RTOS Pharos
2020-03-24  8:14 ` [Bug 1815721] " RTOS Pharos
2020-03-24 10:35   ` Bin Meng
2020-03-24 10:35     ` Bin Meng
2020-03-25 17:04 ` RTOS Pharos

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