* [PATCH v12 0/3] Add Versal usb model
@ 2020-10-22 12:17 Sai Pavan Boddu
2020-10-22 12:17 ` [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module Sai Pavan Boddu
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Sai Pavan Boddu @ 2020-10-22 12:17 UTC (permalink / raw)
To: Peter Maydell, Markus Armbruster,
'Marc-André Lureau',
Paolo Bonzini, Gerd Hoffmann, Edgar Iglesias,
Francisco Eduardo Iglesias
Cc: Eduardo Habkost, Vikram Garhwal, qemu-devel, Paul Zimmerman,
Sai Pavan Boddu, Alistair Francis, Ying Fang,
'Philippe Mathieu-Daudé'
This patch series attempts to make 'hcd-xhci' an independent model so it can be used by both pci and system-bus interface.
Changes for V2:
Make XHCIState non-qom
Use container_of functions for retriving pci device instance
Initialize the AddressSpace pointer in PATCH 1/3 itself Changes for V3:
Convert XHCIState to TYPE_DEVICE and register as a child of XHCIPciState.
Changes for V4:
Add DWC3 usb controller
Add versal, usb2-reg module
Connect sysbus xhci to versal virt board Changes for V5:
Add extra info about dwc3 and usb2_regs devices in commit messages
Use only one irq for versal usb controller
Mark the unimplemented registers in dwc3 controller
Rebase the patches over master.
Move few mispalced contents from patch 2/7 to 3/7.
Fix the author names in the header.
Move the inclusion of "sysemu/dma.h" from patch 1/7 to 3/7 Changes for V6:
Fixed style issue in patch 7/7
Renamed usb2_reg model to VersalUsb2CtrlReg
Fixed author in headers
Changes for V7:
Create a usb structure to keep things clean
Remove the repeated patch in the series i.e 5/7 Changes for V8:
Fix vmstate sturcts to support cross version migration.
Changes for V9:
Added recommended changes to fix vmstate migration.
Fixed commit message on 3/7.
Changes for V10:
use vmstate_post_load avaialble in VMStateDescription
tested vmstate cross migration.
Changes for V11:
Removed the patches which got accepted
Changed object name "USB2Reg" -> "ctrl"
Updated Subject line on cover letter.
Changes for V12:
Use reset class for usb2-ctrl-regs module
Move the few register update to realize
Marked registers which are unimplemented in regapi model
Sai Pavan Boddu (1):
misc: Add versal-usb2-ctrl-regs module
Vikram Garhwal (2):
usb: Add DWC3 model
Versal: Connect DWC3 controller with virt-versal
hw/arm/xlnx-versal-virt.c | 58 +++
hw/arm/xlnx-versal.c | 34 ++
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-usb2-ctrl-regs.c | 229 +++++++++
hw/usb/Kconfig | 6 +
hw/usb/hcd-dwc3.c | 666 +++++++++++++++++++++++++++
hw/usb/meson.build | 1 +
include/hw/arm/xlnx-versal.h | 14 +
include/hw/misc/xlnx-versal-usb2-ctrl-regs.h | 45 ++
include/hw/usb/hcd-dwc3.h | 55 +++
10 files changed, 1109 insertions(+)
create mode 100644 hw/misc/xlnx-versal-usb2-ctrl-regs.c
create mode 100644 hw/usb/hcd-dwc3.c
create mode 100644 include/hw/misc/xlnx-versal-usb2-ctrl-regs.h
create mode 100644 include/hw/usb/hcd-dwc3.h
--
2.7.4
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
2020-10-22 12:17 [PATCH v12 0/3] Add Versal usb model Sai Pavan Boddu
@ 2020-10-22 12:17 ` Sai Pavan Boddu
2020-10-26 16:02 ` Peter Maydell
2020-10-22 12:17 ` [PATCH v12 2/3] usb: Add DWC3 model Sai Pavan Boddu
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Sai Pavan Boddu @ 2020-10-22 12:17 UTC (permalink / raw)
To: Peter Maydell, Markus Armbruster,
'Marc-André Lureau',
Paolo Bonzini, Gerd Hoffmann, Edgar Iglesias,
Francisco Eduardo Iglesias
Cc: Eduardo Habkost, Vikram Garhwal, qemu-devel, Paul Zimmerman,
Sai Pavan Boddu, Alistair Francis, Ying Fang,
'Philippe Mathieu-Daudé'
This module emulates control registers of versal usb2 controller, this is added
just to make guest happy. In general this module would control the phy-reset
signal from usb controller, data coherency of the transactions, signals
the host system errors received from controller.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
---
hw/misc/meson.build | 1 +
hw/misc/xlnx-versal-usb2-ctrl-regs.c | 229 +++++++++++++++++++++++++++
include/hw/misc/xlnx-versal-usb2-ctrl-regs.h | 45 ++++++
3 files changed, 275 insertions(+)
create mode 100644 hw/misc/xlnx-versal-usb2-ctrl-regs.c
create mode 100644 include/hw/misc/xlnx-versal-usb2-ctrl-regs.h
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 793d45b..b336dd1 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -109,3 +109,4 @@ specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cp
specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c'))
specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
+specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-usb2-ctrl-regs.c'))
diff --git a/hw/misc/xlnx-versal-usb2-ctrl-regs.c b/hw/misc/xlnx-versal-usb2-ctrl-regs.c
new file mode 100644
index 0000000..0d09dd2
--- /dev/null
+++ b/hw/misc/xlnx-versal-usb2-ctrl-regs.c
@@ -0,0 +1,229 @@
+/*
+ * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for
+ * USB2.0 controller
+ *
+ * This module should control phy_reset, permanent device plugs, frame length
+ * time adjust & setting of coherency paths. None of which are emulated in
+ * present model.
+ *
+ * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal <fnu.vikram@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/register.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "migration/vmstate.h"
+#include "hw/misc/xlnx-versal-usb2-ctrl-regs.h"
+
+#ifndef XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG
+#define XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG 0
+#endif
+
+REG32(BUS_FILTER, 0x30)
+ FIELD(BUS_FILTER, BYPASS, 0, 4)
+REG32(PORT, 0x34)
+ FIELD(PORT, HOST_SMI_BAR_WR, 4, 1)
+ FIELD(PORT, HOST_SMI_PCI_CMD_REG_WR, 3, 1)
+ FIELD(PORT, HOST_MSI_ENABLE, 2, 1)
+ FIELD(PORT, PWR_CTRL_PRSNT, 1, 1)
+ FIELD(PORT, HUB_PERM_ATTACH, 0, 1)
+REG32(JITTER_ADJUST, 0x38)
+ FIELD(JITTER_ADJUST, FLADJ, 0, 6)
+REG32(BIGENDIAN, 0x40)
+ FIELD(BIGENDIAN, ENDIAN_GS, 0, 1)
+REG32(COHERENCY, 0x44)
+ FIELD(COHERENCY, USB_COHERENCY, 0, 1)
+REG32(XHC_BME, 0x48)
+ FIELD(XHC_BME, XHC_BME, 0, 1)
+REG32(REG_CTRL, 0x60)
+ FIELD(REG_CTRL, SLVERR_ENABLE, 0, 1)
+REG32(IR_STATUS, 0x64)
+ FIELD(IR_STATUS, HOST_SYS_ERR, 1, 1)
+ FIELD(IR_STATUS, ADDR_DEC_ERR, 0, 1)
+REG32(IR_MASK, 0x68)
+ FIELD(IR_MASK, HOST_SYS_ERR, 1, 1)
+ FIELD(IR_MASK, ADDR_DEC_ERR, 0, 1)
+REG32(IR_ENABLE, 0x6c)
+ FIELD(IR_ENABLE, HOST_SYS_ERR, 1, 1)
+ FIELD(IR_ENABLE, ADDR_DEC_ERR, 0, 1)
+REG32(IR_DISABLE, 0x70)
+ FIELD(IR_DISABLE, HOST_SYS_ERR, 1, 1)
+ FIELD(IR_DISABLE, ADDR_DEC_ERR, 0, 1)
+REG32(USB3, 0x78)
+
+static void ir_update_irq(VersalUsb2CtrlRegs *s)
+{
+ bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
+ qemu_set_irq(s->irq_ir, pending);
+}
+
+static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
+{
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
+ /*
+ * TODO: This should also clear USBSTS.HSE field in USB XHCI register.
+ * May be combine both the modules.
+ */
+ ir_update_irq(s);
+}
+
+static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
+{
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IR_MASK] &= ~val;
+ ir_update_irq(s);
+ return 0;
+}
+
+static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
+{
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
+ uint32_t val = val64;
+
+ s->regs[R_IR_MASK] |= val;
+ ir_update_irq(s);
+ return 0;
+}
+
+static const RegisterAccessInfo usb2_ctrl_regs_regs_info[] = {
+ { .name = "BUS_FILTER", .addr = A_BUS_FILTER,
+ .rsvd = 0xfffffff0,
+ },{ .name = "PORT", .addr = A_PORT,
+ .rsvd = 0xffffffe0,
+ },{ .name = "JITTER_ADJUST", .addr = A_JITTER_ADJUST,
+ .reset = 0x20,
+ .rsvd = 0xffffffc0,
+ },{ .name = "BIGENDIAN", .addr = A_BIGENDIAN,
+ .rsvd = 0xfffffffe,
+ },{ .name = "COHERENCY", .addr = A_COHERENCY,
+ .rsvd = 0xfffffffe,
+ },{ .name = "XHC_BME", .addr = A_XHC_BME,
+ .reset = 0x1,
+ .rsvd = 0xfffffffe,
+ },{ .name = "REG_CTRL", .addr = A_REG_CTRL,
+ .rsvd = 0xfffffffe,
+ },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
+ .rsvd = 0xfffffffc,
+ .w1c = 0x3,
+ .post_write = ir_status_postw,
+ },{ .name = "IR_MASK", .addr = A_IR_MASK,
+ .reset = 0x3,
+ .rsvd = 0xfffffffc,
+ .ro = 0x3,
+ },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
+ .rsvd = 0xfffffffc,
+ .pre_write = ir_enable_prew,
+ },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
+ .rsvd = 0xfffffffc,
+ .pre_write = ir_disable_prew,
+ },{ .name = "USB3", .addr = A_USB3,
+ }
+};
+
+static void usb2_ctrl_regs_reset_init(Object *obj, ResetType type)
+{
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+}
+
+static void usb2_ctrl_regs_reset_hold(Object *obj)
+{
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
+
+ ir_update_irq(s);
+}
+
+static const MemoryRegionOps usb2_ctrl_regs_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void usb2_ctrl_regs_init(Object *obj)
+{
+ VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ RegisterInfoArray *reg_array;
+
+ memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
+ USB2_REGS_R_MAX * 4);
+ reg_array =
+ register_init_block32(DEVICE(obj), usb2_ctrl_regs_regs_info,
+ ARRAY_SIZE(usb2_ctrl_regs_regs_info),
+ s->regs_info, s->regs,
+ &usb2_ctrl_regs_ops,
+ XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG,
+ USB2_REGS_R_MAX * 4);
+ memory_region_add_subregion(&s->iomem,
+ 0x0,
+ ®_array->mem);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq_ir);
+}
+
+static const VMStateDescription vmstate_usb2_ctrl_regs = {
+ .name = TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, VersalUsb2CtrlRegs, USB2_REGS_R_MAX),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static void usb2_ctrl_regs_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+ rc->phases.enter = usb2_ctrl_regs_reset_init;
+ rc->phases.hold = usb2_ctrl_regs_reset_hold;
+ dc->vmsd = &vmstate_usb2_ctrl_regs;
+}
+
+static const TypeInfo usb2_ctrl_regs_info = {
+ .name = TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(VersalUsb2CtrlRegs),
+ .class_init = usb2_ctrl_regs_class_init,
+ .instance_init = usb2_ctrl_regs_init,
+};
+
+static void usb2_ctrl_regs_register_types(void)
+{
+ type_register_static(&usb2_ctrl_regs_info);
+}
+
+type_init(usb2_ctrl_regs_register_types)
diff --git a/include/hw/misc/xlnx-versal-usb2-ctrl-regs.h b/include/hw/misc/xlnx-versal-usb2-ctrl-regs.h
new file mode 100644
index 0000000..975a717
--- /dev/null
+++ b/include/hw/misc/xlnx-versal-usb2-ctrl-regs.h
@@ -0,0 +1,45 @@
+/*
+ * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for
+ * USB2.0 controller
+ *
+ * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal <fnu.vikram@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef _XLNX_USB2_REGS_H_
+#define _XLNX_USB2_REGS_H_
+
+#define TYPE_XILINX_VERSAL_USB2_CTRL_REGS "xlnx.versal-usb2-ctrl-regs"
+
+#define XILINX_VERSAL_USB2_CTRL_REGS(obj) \
+ OBJECT_CHECK(VersalUsb2CtrlRegs, (obj), TYPE_XILINX_VERSAL_USB2_CTRL_REGS)
+
+#define USB2_REGS_R_MAX ((0x78 / 4) + 1)
+
+typedef struct VersalUsb2CtrlRegs {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ qemu_irq irq_ir;
+
+ uint32_t regs[USB2_REGS_R_MAX];
+ RegisterInfo regs_info[USB2_REGS_R_MAX];
+} VersalUsb2CtrlRegs;
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v12 2/3] usb: Add DWC3 model
2020-10-22 12:17 [PATCH v12 0/3] Add Versal usb model Sai Pavan Boddu
2020-10-22 12:17 ` [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module Sai Pavan Boddu
@ 2020-10-22 12:17 ` Sai Pavan Boddu
2020-10-22 12:17 ` [PATCH v12 3/3] Versal: Connect DWC3 controller with virt-versal Sai Pavan Boddu
2020-10-23 9:27 ` [PATCH v12 0/3] Add Versal usb model Edgar E. Iglesias
3 siblings, 0 replies; 12+ messages in thread
From: Sai Pavan Boddu @ 2020-10-22 12:17 UTC (permalink / raw)
To: Peter Maydell, Markus Armbruster,
'Marc-André Lureau',
Paolo Bonzini, Gerd Hoffmann, Edgar Iglesias,
Francisco Eduardo Iglesias
Cc: Eduardo Habkost, Vikram Garhwal, qemu-devel, Paul Zimmerman,
Sai Pavan Boddu, Alistair Francis, Ying Fang,
'Philippe Mathieu-Daudé'
From: Vikram Garhwal <fnu.vikram@xilinx.com>
This patch adds skeleton model of dwc3 usb controller attached to
xhci-sysbus device. It defines global register space of DWC3 controller,
global registers control the AXI/AHB interfaces properties, external FIFO
support and event count support. All of which are unimplemented at
present,we are only supporting core reset and read of ID register.
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
hw/usb/Kconfig | 6 +
hw/usb/hcd-dwc3.c | 666 ++++++++++++++++++++++++++++++++++++++++++++++
hw/usb/meson.build | 1 +
include/hw/usb/hcd-dwc3.h | 55 ++++
4 files changed, 728 insertions(+)
create mode 100644 hw/usb/hcd-dwc3.c
create mode 100644 include/hw/usb/hcd-dwc3.h
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index 4dd2ba9..f5762f0 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -116,3 +116,9 @@ config IMX_USBPHY
bool
default y
depends on USB
+
+config USB_DWC3
+ bool
+ default y if USB_XHCI_SYSBUS
+ select USB
+ select REGISTER
diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c
new file mode 100644
index 0000000..775b7a7
--- /dev/null
+++ b/hw/usb/hcd-dwc3.c
@@ -0,0 +1,666 @@
+/*
+ * QEMU model of the USB DWC3 host controller emulation.
+ *
+ * This model defines global register space of DWC3 controller. Global
+ * registers control the AXI/AHB interfaces properties, external FIFO support
+ * and event count support. All of which are unimplemented at present. We are
+ * only supporting core reset and read of ID register.
+ *
+ * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal<fnu.vikram@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qom/object.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/usb/hcd-dwc3.h"
+#include "qapi/error.h"
+
+#ifndef USB_DWC3_ERR_DEBUG
+#define USB_DWC3_ERR_DEBUG 0
+#endif
+
+#define HOST_MODE 1
+#define FIFO_LEN 0x1000
+
+REG32(GSBUSCFG0, 0x00)
+ FIELD(GSBUSCFG0, DATRDREQINFO, 28, 4)
+ FIELD(GSBUSCFG0, DESRDREQINFO, 24, 4)
+ FIELD(GSBUSCFG0, DATWRREQINFO, 20, 4)
+ FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4)
+ FIELD(GSBUSCFG0, RESERVED_15_12, 12, 4)
+ FIELD(GSBUSCFG0, DATBIGEND, 11, 1)
+ FIELD(GSBUSCFG0, DESBIGEND, 10, 1)
+ FIELD(GSBUSCFG0, RESERVED_9_8, 8, 2)
+ FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1)
+ FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1)
+ FIELD(GSBUSCFG0, INCR64BRSTENA, 5, 1)
+ FIELD(GSBUSCFG0, INCR32BRSTENA, 4, 1)
+ FIELD(GSBUSCFG0, INCR16BRSTENA, 3, 1)
+ FIELD(GSBUSCFG0, INCR8BRSTENA, 2, 1)
+ FIELD(GSBUSCFG0, INCR4BRSTENA, 1, 1)
+ FIELD(GSBUSCFG0, INCRBRSTENA, 0, 1)
+REG32(GSBUSCFG1, 0x04)
+ FIELD(GSBUSCFG1, RESERVED_31_13, 13, 19)
+ FIELD(GSBUSCFG1, EN1KPAGE, 12, 1)
+ FIELD(GSBUSCFG1, PIPETRANSLIMIT, 8, 4)
+ FIELD(GSBUSCFG1, RESERVED_7_0, 0, 8)
+REG32(GTXTHRCFG, 0x08)
+ FIELD(GTXTHRCFG, RESERVED_31, 31, 1)
+ FIELD(GTXTHRCFG, RESERVED_30, 30, 1)
+ FIELD(GTXTHRCFG, USBTXPKTCNTSEL, 29, 1)
+ FIELD(GTXTHRCFG, RESERVED_28, 28, 1)
+ FIELD(GTXTHRCFG, USBTXPKTCNT, 24, 4)
+ FIELD(GTXTHRCFG, USBMAXTXBURSTSIZE, 16, 8)
+ FIELD(GTXTHRCFG, RESERVED_15, 15, 1)
+ FIELD(GTXTHRCFG, RESERVED_14, 14, 1)
+ FIELD(GTXTHRCFG, RESERVED_13_11, 11, 3)
+ FIELD(GTXTHRCFG, RESERVED_10_0, 0, 11)
+REG32(GRXTHRCFG, 0x0c)
+ FIELD(GRXTHRCFG, RESERVED_31_30, 30, 2)
+ FIELD(GRXTHRCFG, USBRXPKTCNTSEL, 29, 1)
+ FIELD(GRXTHRCFG, RESERVED_28, 28, 1)
+ FIELD(GRXTHRCFG, USBRXPKTCNT, 24, 4)
+ FIELD(GRXTHRCFG, USBMAXRXBURSTSIZE, 19, 5)
+ FIELD(GRXTHRCFG, RESERVED_18_16, 16, 3)
+ FIELD(GRXTHRCFG, RESERVED_15, 15, 1)
+ FIELD(GRXTHRCFG, RESERVED_14_13, 13, 2)
+ FIELD(GRXTHRCFG, RESVISOCOUTSPC, 0, 13)
+REG32(GCTL, 0x10)
+ FIELD(GCTL, PWRDNSCALE, 19, 13)
+ FIELD(GCTL, MASTERFILTBYPASS, 18, 1)
+ FIELD(GCTL, BYPSSETADDR, 17, 1)
+ FIELD(GCTL, U2RSTECN, 16, 1)
+ FIELD(GCTL, FRMSCLDWN, 14, 2)
+ FIELD(GCTL, PRTCAPDIR, 12, 2)
+ FIELD(GCTL, CORESOFTRESET, 11, 1)
+ FIELD(GCTL, U1U2TIMERSCALE, 9, 1)
+ FIELD(GCTL, DEBUGATTACH, 8, 1)
+ FIELD(GCTL, RAMCLKSEL, 6, 2)
+ FIELD(GCTL, SCALEDOWN, 4, 2)
+ FIELD(GCTL, DISSCRAMBLE, 3, 1)
+ FIELD(GCTL, U2EXIT_LFPS, 2, 1)
+ FIELD(GCTL, GBLHIBERNATIONEN, 1, 1)
+ FIELD(GCTL, DSBLCLKGTNG, 0, 1)
+REG32(GPMSTS, 0x14)
+REG32(GSTS, 0x18)
+ FIELD(GSTS, CBELT, 20, 12)
+ FIELD(GSTS, RESERVED_19_12, 12, 8)
+ FIELD(GSTS, SSIC_IP, 11, 1)
+ FIELD(GSTS, OTG_IP, 10, 1)
+ FIELD(GSTS, BC_IP, 9, 1)
+ FIELD(GSTS, ADP_IP, 8, 1)
+ FIELD(GSTS, HOST_IP, 7, 1)
+ FIELD(GSTS, DEVICE_IP, 6, 1)
+ FIELD(GSTS, CSRTIMEOUT, 5, 1)
+ FIELD(GSTS, BUSERRADDRVLD, 4, 1)
+ FIELD(GSTS, RESERVED_3_2, 2, 2)
+ FIELD(GSTS, CURMOD, 0, 2)
+REG32(GUCTL1, 0x1c)
+ FIELD(GUCTL1, RESUME_OPMODE_HS_HOST, 10, 1)
+REG32(GSNPSID, 0x20)
+REG32(GGPIO, 0x24)
+ FIELD(GGPIO, GPO, 16, 16)
+ FIELD(GGPIO, GPI, 0, 16)
+REG32(GUID, 0x28)
+REG32(GUCTL, 0x2c)
+ FIELD(GUCTL, REFCLKPER, 22, 10)
+ FIELD(GUCTL, NOEXTRDL, 21, 1)
+ FIELD(GUCTL, RESERVED_20_18, 18, 3)
+ FIELD(GUCTL, SPRSCTRLTRANSEN, 17, 1)
+ FIELD(GUCTL, RESBWHSEPS, 16, 1)
+ FIELD(GUCTL, RESERVED_15, 15, 1)
+ FIELD(GUCTL, USBHSTINAUTORETRYEN, 14, 1)
+ FIELD(GUCTL, ENOVERLAPCHK, 13, 1)
+ FIELD(GUCTL, EXTCAPSUPPTEN, 12, 1)
+ FIELD(GUCTL, INSRTEXTRFSBODI, 11, 1)
+ FIELD(GUCTL, DTCT, 9, 2)
+ FIELD(GUCTL, DTFT, 0, 9)
+REG32(GBUSERRADDRLO, 0x30)
+REG32(GBUSERRADDRHI, 0x34)
+REG32(GHWPARAMS0, 0x40)
+ FIELD(GHWPARAMS0, GHWPARAMS0_31_24, 24, 8)
+ FIELD(GHWPARAMS0, GHWPARAMS0_23_16, 16, 8)
+ FIELD(GHWPARAMS0, GHWPARAMS0_15_8, 8, 8)
+ FIELD(GHWPARAMS0, GHWPARAMS0_7_6, 6, 2)
+ FIELD(GHWPARAMS0, GHWPARAMS0_5_3, 3, 3)
+ FIELD(GHWPARAMS0, GHWPARAMS0_2_0, 0, 3)
+REG32(GHWPARAMS1, 0x44)
+ FIELD(GHWPARAMS1, GHWPARAMS1_31, 31, 1)
+ FIELD(GHWPARAMS1, GHWPARAMS1_30, 30, 1)
+ FIELD(GHWPARAMS1, GHWPARAMS1_29, 29, 1)
+ FIELD(GHWPARAMS1, GHWPARAMS1_28, 28, 1)
+ FIELD(GHWPARAMS1, GHWPARAMS1_27, 27, 1)
+ FIELD(GHWPARAMS1, GHWPARAMS1_26, 26, 1)
+ FIELD(GHWPARAMS1, GHWPARAMS1_25_24, 24, 2)
+ FIELD(GHWPARAMS1, GHWPARAMS1_23, 23, 1)
+ FIELD(GHWPARAMS1, GHWPARAMS1_22_21, 21, 2)
+ FIELD(GHWPARAMS1, GHWPARAMS1_20_15, 15, 6)
+ FIELD(GHWPARAMS1, GHWPARAMS1_14_12, 12, 3)
+ FIELD(GHWPARAMS1, GHWPARAMS1_11_9, 9, 3)
+ FIELD(GHWPARAMS1, GHWPARAMS1_8_6, 6, 3)
+ FIELD(GHWPARAMS1, GHWPARAMS1_5_3, 3, 3)
+ FIELD(GHWPARAMS1, GHWPARAMS1_2_0, 0, 3)
+REG32(GHWPARAMS2, 0x48)
+REG32(GHWPARAMS3, 0x4c)
+ FIELD(GHWPARAMS3, GHWPARAMS3_31, 31, 1)
+ FIELD(GHWPARAMS3, GHWPARAMS3_30_23, 23, 8)
+ FIELD(GHWPARAMS3, GHWPARAMS3_22_18, 18, 5)
+ FIELD(GHWPARAMS3, GHWPARAMS3_17_12, 12, 6)
+ FIELD(GHWPARAMS3, GHWPARAMS3_11, 11, 1)
+ FIELD(GHWPARAMS3, GHWPARAMS3_10, 10, 1)
+ FIELD(GHWPARAMS3, GHWPARAMS3_9_8, 8, 2)
+ FIELD(GHWPARAMS3, GHWPARAMS3_7_6, 6, 2)
+ FIELD(GHWPARAMS3, GHWPARAMS3_5_4, 4, 2)
+ FIELD(GHWPARAMS3, GHWPARAMS3_3_2, 2, 2)
+ FIELD(GHWPARAMS3, GHWPARAMS3_1_0, 0, 2)
+REG32(GHWPARAMS4, 0x50)
+ FIELD(GHWPARAMS4, GHWPARAMS4_31_28, 28, 4)
+ FIELD(GHWPARAMS4, GHWPARAMS4_27_24, 24, 4)
+ FIELD(GHWPARAMS4, GHWPARAMS4_23, 23, 1)
+ FIELD(GHWPARAMS4, GHWPARAMS4_22, 22, 1)
+ FIELD(GHWPARAMS4, GHWPARAMS4_21, 21, 1)
+ FIELD(GHWPARAMS4, GHWPARAMS4_20_17, 17, 4)
+ FIELD(GHWPARAMS4, GHWPARAMS4_16_13, 13, 4)
+ FIELD(GHWPARAMS4, GHWPARAMS4_12, 12, 1)
+ FIELD(GHWPARAMS4, GHWPARAMS4_11, 11, 1)
+ FIELD(GHWPARAMS4, GHWPARAMS4_10_9, 9, 2)
+ FIELD(GHWPARAMS4, GHWPARAMS4_8_7, 7, 2)
+ FIELD(GHWPARAMS4, GHWPARAMS4_6, 6, 1)
+ FIELD(GHWPARAMS4, GHWPARAMS4_5_0, 0, 6)
+REG32(GHWPARAMS5, 0x54)
+ FIELD(GHWPARAMS5, GHWPARAMS5_31_28, 28, 4)
+ FIELD(GHWPARAMS5, GHWPARAMS5_27_22, 22, 6)
+ FIELD(GHWPARAMS5, GHWPARAMS5_21_16, 16, 6)
+ FIELD(GHWPARAMS5, GHWPARAMS5_15_10, 10, 6)
+ FIELD(GHWPARAMS5, GHWPARAMS5_9_4, 4, 6)
+ FIELD(GHWPARAMS5, GHWPARAMS5_3_0, 0, 4)
+REG32(GHWPARAMS6, 0x58)
+ FIELD(GHWPARAMS6, GHWPARAMS6_31_16, 16, 16)
+ FIELD(GHWPARAMS6, BUSFLTRSSUPPORT, 15, 1)
+ FIELD(GHWPARAMS6, BCSUPPORT, 14, 1)
+ FIELD(GHWPARAMS6, OTG_SS_SUPPORT, 13, 1)
+ FIELD(GHWPARAMS6, ADPSUPPORT, 12, 1)
+ FIELD(GHWPARAMS6, HNPSUPPORT, 11, 1)
+ FIELD(GHWPARAMS6, SRPSUPPORT, 10, 1)
+ FIELD(GHWPARAMS6, GHWPARAMS6_9_8, 8, 2)
+ FIELD(GHWPARAMS6, GHWPARAMS6_7, 7, 1)
+ FIELD(GHWPARAMS6, GHWPARAMS6_6, 6, 1)
+ FIELD(GHWPARAMS6, GHWPARAMS6_5_0, 0, 6)
+REG32(GHWPARAMS7, 0x5c)
+ FIELD(GHWPARAMS7, GHWPARAMS7_31_16, 16, 16)
+ FIELD(GHWPARAMS7, GHWPARAMS7_15_0, 0, 16)
+REG32(GDBGFIFOSPACE, 0x60)
+ FIELD(GDBGFIFOSPACE, SPACE_AVAILABLE, 16, 16)
+ FIELD(GDBGFIFOSPACE, RESERVED_15_9, 9, 7)
+ FIELD(GDBGFIFOSPACE, FIFO_QUEUE_SELECT, 0, 9)
+REG32(GUCTL2, 0x9c)
+ FIELD(GUCTL2, RESERVED_31_26, 26, 6)
+ FIELD(GUCTL2, EN_HP_PM_TIMER, 19, 7)
+ FIELD(GUCTL2, NOLOWPWRDUR, 15, 4)
+ FIELD(GUCTL2, RST_ACTBITLATER, 14, 1)
+ FIELD(GUCTL2, RESERVED_13, 13, 1)
+ FIELD(GUCTL2, DISABLECFC, 11, 1)
+REG32(GUSB2PHYCFG, 0x100)
+ FIELD(GUSB2PHYCFG, U2_FREECLK_EXISTS, 30, 1)
+ FIELD(GUSB2PHYCFG, ULPI_LPM_WITH_OPMODE_CHK, 29, 1)
+ FIELD(GUSB2PHYCFG, RESERVED_25, 25, 1)
+ FIELD(GUSB2PHYCFG, LSTRD, 22, 3)
+ FIELD(GUSB2PHYCFG, LSIPD, 19, 3)
+ FIELD(GUSB2PHYCFG, ULPIEXTVBUSINDIACTOR, 18, 1)
+ FIELD(GUSB2PHYCFG, ULPIEXTVBUSDRV, 17, 1)
+ FIELD(GUSB2PHYCFG, RESERVED_16, 16, 1)
+ FIELD(GUSB2PHYCFG, ULPIAUTORES, 15, 1)
+ FIELD(GUSB2PHYCFG, RESERVED_14, 14, 1)
+ FIELD(GUSB2PHYCFG, USBTRDTIM, 10, 4)
+ FIELD(GUSB2PHYCFG, XCVRDLY, 9, 1)
+ FIELD(GUSB2PHYCFG, ENBLSLPM, 8, 1)
+ FIELD(GUSB2PHYCFG, PHYSEL, 7, 1)
+ FIELD(GUSB2PHYCFG, SUSPENDUSB20, 6, 1)
+ FIELD(GUSB2PHYCFG, FSINTF, 5, 1)
+ FIELD(GUSB2PHYCFG, ULPI_UTMI_SEL, 4, 1)
+ FIELD(GUSB2PHYCFG, PHYIF, 3, 1)
+ FIELD(GUSB2PHYCFG, TOUTCAL, 0, 3)
+REG32(GUSB2I2CCTL, 0x140)
+REG32(GUSB2PHYACC_ULPI, 0x180)
+ FIELD(GUSB2PHYACC_ULPI, RESERVED_31_27, 27, 5)
+ FIELD(GUSB2PHYACC_ULPI, DISUIPIDRVR, 26, 1)
+ FIELD(GUSB2PHYACC_ULPI, NEWREGREQ, 25, 1)
+ FIELD(GUSB2PHYACC_ULPI, VSTSDONE, 24, 1)
+ FIELD(GUSB2PHYACC_ULPI, VSTSBSY, 23, 1)
+ FIELD(GUSB2PHYACC_ULPI, REGWR, 22, 1)
+ FIELD(GUSB2PHYACC_ULPI, REGADDR, 16, 6)
+ FIELD(GUSB2PHYACC_ULPI, EXTREGADDR, 8, 8)
+ FIELD(GUSB2PHYACC_ULPI, REGDATA, 0, 8)
+REG32(GTXFIFOSIZ0, 0x200)
+ FIELD(GTXFIFOSIZ0, TXFSTADDR_N, 16, 16)
+ FIELD(GTXFIFOSIZ0, TXFDEP_N, 0, 16)
+REG32(GTXFIFOSIZ1, 0x204)
+ FIELD(GTXFIFOSIZ1, TXFSTADDR_N, 16, 16)
+ FIELD(GTXFIFOSIZ1, TXFDEP_N, 0, 16)
+REG32(GTXFIFOSIZ2, 0x208)
+ FIELD(GTXFIFOSIZ2, TXFSTADDR_N, 16, 16)
+ FIELD(GTXFIFOSIZ2, TXFDEP_N, 0, 16)
+REG32(GTXFIFOSIZ3, 0x20c)
+ FIELD(GTXFIFOSIZ3, TXFSTADDR_N, 16, 16)
+ FIELD(GTXFIFOSIZ3, TXFDEP_N, 0, 16)
+REG32(GTXFIFOSIZ4, 0x210)
+ FIELD(GTXFIFOSIZ4, TXFSTADDR_N, 16, 16)
+ FIELD(GTXFIFOSIZ4, TXFDEP_N, 0, 16)
+REG32(GTXFIFOSIZ5, 0x214)
+ FIELD(GTXFIFOSIZ5, TXFSTADDR_N, 16, 16)
+ FIELD(GTXFIFOSIZ5, TXFDEP_N, 0, 16)
+REG32(GRXFIFOSIZ0, 0x280)
+ FIELD(GRXFIFOSIZ0, RXFSTADDR_N, 16, 16)
+ FIELD(GRXFIFOSIZ0, RXFDEP_N, 0, 16)
+REG32(GRXFIFOSIZ1, 0x284)
+ FIELD(GRXFIFOSIZ1, RXFSTADDR_N, 16, 16)
+ FIELD(GRXFIFOSIZ1, RXFDEP_N, 0, 16)
+REG32(GRXFIFOSIZ2, 0x288)
+ FIELD(GRXFIFOSIZ2, RXFSTADDR_N, 16, 16)
+ FIELD(GRXFIFOSIZ2, RXFDEP_N, 0, 16)
+REG32(GEVNTADRLO_0, 0x300)
+REG32(GEVNTADRHI_0, 0x304)
+REG32(GEVNTSIZ_0, 0x308)
+ FIELD(GEVNTSIZ_0, EVNTINTRPTMASK, 31, 1)
+ FIELD(GEVNTSIZ_0, RESERVED_30_16, 16, 15)
+ FIELD(GEVNTSIZ_0, EVENTSIZ, 0, 16)
+REG32(GEVNTCOUNT_0, 0x30c)
+ FIELD(GEVNTCOUNT_0, EVNT_HANDLER_BUSY, 31, 1)
+ FIELD(GEVNTCOUNT_0, RESERVED_30_16, 16, 15)
+ FIELD(GEVNTCOUNT_0, EVNTCOUNT, 0, 16)
+REG32(GEVNTADRLO_1, 0x310)
+REG32(GEVNTADRHI_1, 0x314)
+REG32(GEVNTSIZ_1, 0x318)
+ FIELD(GEVNTSIZ_1, EVNTINTRPTMASK, 31, 1)
+ FIELD(GEVNTSIZ_1, RESERVED_30_16, 16, 15)
+ FIELD(GEVNTSIZ_1, EVENTSIZ, 0, 16)
+REG32(GEVNTCOUNT_1, 0x31c)
+ FIELD(GEVNTCOUNT_1, EVNT_HANDLER_BUSY, 31, 1)
+ FIELD(GEVNTCOUNT_1, RESERVED_30_16, 16, 15)
+ FIELD(GEVNTCOUNT_1, EVNTCOUNT, 0, 16)
+REG32(GEVNTADRLO_2, 0x320)
+REG32(GEVNTADRHI_2, 0x324)
+REG32(GEVNTSIZ_2, 0x328)
+ FIELD(GEVNTSIZ_2, EVNTINTRPTMASK, 31, 1)
+ FIELD(GEVNTSIZ_2, RESERVED_30_16, 16, 15)
+ FIELD(GEVNTSIZ_2, EVENTSIZ, 0, 16)
+REG32(GEVNTCOUNT_2, 0x32c)
+ FIELD(GEVNTCOUNT_2, EVNT_HANDLER_BUSY, 31, 1)
+ FIELD(GEVNTCOUNT_2, RESERVED_30_16, 16, 15)
+ FIELD(GEVNTCOUNT_2, EVNTCOUNT, 0, 16)
+REG32(GEVNTADRLO_3, 0x330)
+REG32(GEVNTADRHI_3, 0x334)
+REG32(GEVNTSIZ_3, 0x338)
+ FIELD(GEVNTSIZ_3, EVNTINTRPTMASK, 31, 1)
+ FIELD(GEVNTSIZ_3, RESERVED_30_16, 16, 15)
+ FIELD(GEVNTSIZ_3, EVENTSIZ, 0, 16)
+REG32(GEVNTCOUNT_3, 0x33c)
+ FIELD(GEVNTCOUNT_3, EVNT_HANDLER_BUSY, 31, 1)
+ FIELD(GEVNTCOUNT_3, RESERVED_30_16, 16, 15)
+ FIELD(GEVNTCOUNT_3, EVNTCOUNT, 0, 16)
+REG32(GHWPARAMS8, 0x500)
+REG32(GTXFIFOPRIDEV, 0x510)
+ FIELD(GTXFIFOPRIDEV, RESERVED_31_N, 6, 26)
+ FIELD(GTXFIFOPRIDEV, GTXFIFOPRIDEV, 0, 6)
+REG32(GTXFIFOPRIHST, 0x518)
+ FIELD(GTXFIFOPRIHST, RESERVED_31_16, 3, 29)
+ FIELD(GTXFIFOPRIHST, GTXFIFOPRIHST, 0, 3)
+REG32(GRXFIFOPRIHST, 0x51c)
+ FIELD(GRXFIFOPRIHST, RESERVED_31_16, 3, 29)
+ FIELD(GRXFIFOPRIHST, GRXFIFOPRIHST, 0, 3)
+REG32(GDMAHLRATIO, 0x524)
+ FIELD(GDMAHLRATIO, RESERVED_31_13, 13, 19)
+ FIELD(GDMAHLRATIO, HSTRXFIFO, 8, 5)
+ FIELD(GDMAHLRATIO, RESERVED_7_5, 5, 3)
+ FIELD(GDMAHLRATIO, HSTTXFIFO, 0, 5)
+REG32(GFLADJ, 0x530)
+ FIELD(GFLADJ, GFLADJ_REFCLK_240MHZDECR_PLS1, 31, 1)
+ FIELD(GFLADJ, GFLADJ_REFCLK_240MHZ_DECR, 24, 7)
+ FIELD(GFLADJ, GFLADJ_REFCLK_LPM_SEL, 23, 1)
+ FIELD(GFLADJ, RESERVED_22, 22, 1)
+ FIELD(GFLADJ, GFLADJ_REFCLK_FLADJ, 8, 14)
+ FIELD(GFLADJ, GFLADJ_30MHZ_SDBND_SEL, 7, 1)
+ FIELD(GFLADJ, GFLADJ_30MHZ, 0, 6)
+
+static void reset_csr(USBDWC3 * s)
+{
+ int i = 0;
+ /*
+ * We reset all CSR regs except GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUID,
+ * GUSB2PHYCFGn registers and GUSB3PIPECTLn registers. We will skip PHY
+ * register as we don't implement them.
+ */
+ for (i = 0; i < USB_DWC3_R_MAX; i++) {
+ switch (i) {
+ case R_GCTL:
+ break;
+ case R_GSTS:
+ break;
+ case R_GSNPSID:
+ break;
+ case R_GGPIO:
+ break;
+ case R_GUID:
+ break;
+ case R_GUCTL:
+ break;
+ case R_GHWPARAMS0...R_GHWPARAMS7:
+ break;
+ case R_GHWPARAMS8:
+ break;
+ default:
+ register_reset(&s->regs_info[i]);
+ break;
+ }
+ }
+
+ xhci_sysbus_reset(DEVICE(&s->sysbus_xhci));
+}
+
+static void usb_dwc3_gctl_postw(RegisterInfo *reg, uint64_t val64)
+{
+ USBDWC3 *s = USB_DWC3(reg->opaque);
+
+ if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) {
+ reset_csr(s);
+ }
+}
+
+static void usb_dwc3_guid_postw(RegisterInfo *reg, uint64_t val64)
+{
+ USBDWC3 *s = USB_DWC3(reg->opaque);
+
+ s->regs[R_GUID] = s->cfg.dwc_usb3_user;
+}
+
+static const RegisterAccessInfo usb_dwc3_regs_info[] = {
+ { .name = "GSBUSCFG0", .addr = A_GSBUSCFG0,
+ .ro = 0xf300,
+ .unimp = 0xffffffff,
+ },{ .name = "GSBUSCFG1", .addr = A_GSBUSCFG1,
+ .reset = 0x300,
+ .ro = 0xffffe0ff,
+ .unimp = 0xffffffff,
+ },{ .name = "GTXTHRCFG", .addr = A_GTXTHRCFG,
+ .ro = 0xd000ffff,
+ .unimp = 0xffffffff,
+ },{ .name = "GRXTHRCFG", .addr = A_GRXTHRCFG,
+ .ro = 0xd007e000,
+ .unimp = 0xffffffff,
+ },{ .name = "GCTL", .addr = A_GCTL,
+ .reset = 0x30c13004, .post_write = usb_dwc3_gctl_postw,
+ },{ .name = "GPMSTS", .addr = A_GPMSTS,
+ .ro = 0xfffffff,
+ .unimp = 0xffffffff,
+ },{ .name = "GSTS", .addr = A_GSTS,
+ .reset = 0x7e800000,
+ .ro = 0xffffffcf,
+ .w1c = 0x30,
+ .unimp = 0xffffffff,
+ },{ .name = "GUCTL1", .addr = A_GUCTL1,
+ .reset = 0x198a,
+ .ro = 0x7800,
+ .unimp = 0xffffffff,
+ },{ .name = "GSNPSID", .addr = A_GSNPSID,
+ .reset = 0x5533330a,
+ .ro = 0xffffffff,
+ },{ .name = "GGPIO", .addr = A_GGPIO,
+ .ro = 0xffff,
+ .unimp = 0xffffffff,
+ },{ .name = "GUID", .addr = A_GUID,
+ .reset = 0x12345678, .post_write = usb_dwc3_guid_postw,
+ },{ .name = "GUCTL", .addr = A_GUCTL,
+ .reset = 0x0c808010,
+ .ro = 0x1c8000,
+ .unimp = 0xffffffff,
+ },{ .name = "GBUSERRADDRLO", .addr = A_GBUSERRADDRLO,
+ .ro = 0xffffffff,
+ },{ .name = "GBUSERRADDRHI", .addr = A_GBUSERRADDRHI,
+ .ro = 0xffffffff,
+ },{ .name = "GHWPARAMS0", .addr = A_GHWPARAMS0,
+ .ro = 0xffffffff,
+ .reset = 0x40204048,
+ },{ .name = "GHWPARAMS1", .addr = A_GHWPARAMS1,
+ .ro = 0xffffffff,
+ .reset = 0x222493b,
+ },{ .name = "GHWPARAMS2", .addr = A_GHWPARAMS2,
+ .ro = 0xffffffff,
+ .reset = 0x12345678,
+ },{ .name = "GHWPARAMS3", .addr = A_GHWPARAMS3,
+ .ro = 0xffffffff,
+ .reset = 0x618c088,
+ },{ .name = "GHWPARAMS4", .addr = A_GHWPARAMS4,
+ .ro = 0xffffffff,
+ .reset = 0x47822004,
+ },{ .name = "GHWPARAMS5", .addr = A_GHWPARAMS5,
+ .ro = 0xffffffff,
+ .reset = 0x4202088,
+ },{ .name = "GHWPARAMS6", .addr = A_GHWPARAMS6,
+ .ro = 0xffffffff,
+ .reset = 0x7850c20,
+ },{ .name = "GHWPARAMS7", .addr = A_GHWPARAMS7,
+ .ro = 0xffffffff,
+ .reset = 0x0,
+ },{ .name = "GDBGFIFOSPACE", .addr = A_GDBGFIFOSPACE,
+ .reset = 0xa0000,
+ .ro = 0xfffffe00,
+ .unimp = 0xffffffff,
+ },{ .name = "GUCTL2", .addr = A_GUCTL2,
+ .reset = 0x40d,
+ .ro = 0x2000,
+ .unimp = 0xffffffff,
+ },{ .name = "GUSB2PHYCFG", .addr = A_GUSB2PHYCFG,
+ .reset = 0x40102410,
+ .ro = 0x1e014030,
+ .unimp = 0xffffffff,
+ },{ .name = "GUSB2I2CCTL", .addr = A_GUSB2I2CCTL,
+ .ro = 0xffffffff,
+ .unimp = 0xffffffff,
+ },{ .name = "GUSB2PHYACC_ULPI", .addr = A_GUSB2PHYACC_ULPI,
+ .ro = 0xfd000000,
+ .unimp = 0xffffffff,
+ },{ .name = "GTXFIFOSIZ0", .addr = A_GTXFIFOSIZ0,
+ .reset = 0x2c7000a,
+ .unimp = 0xffffffff,
+ },{ .name = "GTXFIFOSIZ1", .addr = A_GTXFIFOSIZ1,
+ .reset = 0x2d10103,
+ .unimp = 0xffffffff,
+ },{ .name = "GTXFIFOSIZ2", .addr = A_GTXFIFOSIZ2,
+ .reset = 0x3d40103,
+ .unimp = 0xffffffff,
+ },{ .name = "GTXFIFOSIZ3", .addr = A_GTXFIFOSIZ3,
+ .reset = 0x4d70083,
+ .unimp = 0xffffffff,
+ },{ .name = "GTXFIFOSIZ4", .addr = A_GTXFIFOSIZ4,
+ .reset = 0x55a0083,
+ .unimp = 0xffffffff,
+ },{ .name = "GTXFIFOSIZ5", .addr = A_GTXFIFOSIZ5,
+ .reset = 0x5dd0083,
+ .unimp = 0xffffffff,
+ },{ .name = "GRXFIFOSIZ0", .addr = A_GRXFIFOSIZ0,
+ .reset = 0x1c20105,
+ .unimp = 0xffffffff,
+ },{ .name = "GRXFIFOSIZ1", .addr = A_GRXFIFOSIZ1,
+ .reset = 0x2c70000,
+ .unimp = 0xffffffff,
+ },{ .name = "GRXFIFOSIZ2", .addr = A_GRXFIFOSIZ2,
+ .reset = 0x2c70000,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTADRLO_0", .addr = A_GEVNTADRLO_0,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTADRHI_0", .addr = A_GEVNTADRHI_0,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTSIZ_0", .addr = A_GEVNTSIZ_0,
+ .ro = 0x7fff0000,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTCOUNT_0", .addr = A_GEVNTCOUNT_0,
+ .ro = 0x7fff0000,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTADRLO_1", .addr = A_GEVNTADRLO_1,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTADRHI_1", .addr = A_GEVNTADRHI_1,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTSIZ_1", .addr = A_GEVNTSIZ_1,
+ .ro = 0x7fff0000,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTCOUNT_1", .addr = A_GEVNTCOUNT_1,
+ .ro = 0x7fff0000,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTADRLO_2", .addr = A_GEVNTADRLO_2,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTADRHI_2", .addr = A_GEVNTADRHI_2,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTSIZ_2", .addr = A_GEVNTSIZ_2,
+ .ro = 0x7fff0000,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTCOUNT_2", .addr = A_GEVNTCOUNT_2,
+ .ro = 0x7fff0000,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTADRLO_3", .addr = A_GEVNTADRLO_3,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTADRHI_3", .addr = A_GEVNTADRHI_3,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTSIZ_3", .addr = A_GEVNTSIZ_3,
+ .ro = 0x7fff0000,
+ .unimp = 0xffffffff,
+ },{ .name = "GEVNTCOUNT_3", .addr = A_GEVNTCOUNT_3,
+ .ro = 0x7fff0000,
+ .unimp = 0xffffffff,
+ },{ .name = "GHWPARAMS8", .addr = A_GHWPARAMS8,
+ .ro = 0xffffffff,
+ .reset = 0x478,
+ },{ .name = "GTXFIFOPRIDEV", .addr = A_GTXFIFOPRIDEV,
+ .ro = 0xffffffc0,
+ .unimp = 0xffffffff,
+ },{ .name = "GTXFIFOPRIHST", .addr = A_GTXFIFOPRIHST,
+ .ro = 0xfffffff8,
+ .unimp = 0xffffffff,
+ },{ .name = "GRXFIFOPRIHST", .addr = A_GRXFIFOPRIHST,
+ .ro = 0xfffffff8,
+ .unimp = 0xffffffff,
+ },{ .name = "GDMAHLRATIO", .addr = A_GDMAHLRATIO,
+ .ro = 0xffffe0e0,
+ .unimp = 0xffffffff,
+ },{ .name = "GFLADJ", .addr = A_GFLADJ,
+ .reset = 0xc83f020,
+ .rsvd = 0x40,
+ .ro = 0x400040,
+ .unimp = 0xffffffff,
+ }
+};
+
+static void usb_dwc3_reset(DeviceState *dev)
+{
+ USBDWC3 *s = USB_DWC3(dev);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+
+ /*
+ * Device Configuration
+ */
+ s->regs[R_GHWPARAMS0] |= s->cfg.mode;
+ xhci_sysbus_reset(DEVICE(&s->sysbus_xhci));
+}
+
+static const MemoryRegionOps usb_dwc3_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void usb_dwc3_realize(DeviceState *dev, Error **errp)
+{
+ USBDWC3 *s = USB_DWC3(dev);
+ Error *err = NULL;
+
+ sysbus_realize(SYS_BUS_DEVICE(&s->sysbus_xhci), &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+}
+
+static void usb_dwc3_init(Object *obj)
+{
+ USBDWC3 *s = USB_DWC3(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ RegisterInfoArray *reg_array;
+
+ memory_region_init(&s->iomem, obj, TYPE_USB_DWC3, USB_DWC3_R_MAX * 4);
+ reg_array =
+ register_init_block32(DEVICE(obj), usb_dwc3_regs_info,
+ ARRAY_SIZE(usb_dwc3_regs_info),
+ s->regs_info, s->regs,
+ &usb_dwc3_ops,
+ USB_DWC3_ERR_DEBUG,
+ USB_DWC3_R_MAX * 4);
+ memory_region_add_subregion(&s->iomem,
+ 0x0,
+ ®_array->mem);
+ sysbus_init_mmio(sbd, &s->iomem);
+ object_initialize_child(obj, "dwc3-xhci", &s->sysbus_xhci,
+ TYPE_XHCI_SYSBUS);
+ qdev_alias_all_properties(DEVICE(&s->sysbus_xhci), obj);
+
+ s->cfg.mode = HOST_MODE;
+}
+
+static Property usb_dwc3_properties[] = {
+ DEFINE_PROP_UINT32("DWC_USB3_USERID", USBDWC3, cfg.dwc_usb3_user,
+ 0x12345678),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void usb_dwc3_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = usb_dwc3_reset;
+ dc->realize = usb_dwc3_realize;
+ device_class_set_props(dc, usb_dwc3_properties);
+}
+
+static const TypeInfo usb_dwc3_info = {
+ .name = TYPE_USB_DWC3,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(USBDWC3),
+ .class_init = usb_dwc3_class_init,
+ .instance_init = usb_dwc3_init,
+};
+
+static void usb_dwc3_register_types(void)
+{
+ type_register_static(&usb_dwc3_info);
+}
+
+type_init(usb_dwc3_register_types)
diff --git a/hw/usb/meson.build b/hw/usb/meson.build
index 934e4fa..962fbc0 100644
--- a/hw/usb/meson.build
+++ b/hw/usb/meson.build
@@ -26,6 +26,7 @@ softmmu_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: files('hcd-xhci-sysbus.c
softmmu_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c'))
softmmu_ss.add(when: 'CONFIG_USB_MUSB', if_true: files('hcd-musb.c'))
softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c'))
+softmmu_ss.add(when: 'CONFIG_USB_DWC3', if_true: files('hcd-dwc3.c'))
softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c'))
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c'))
diff --git a/include/hw/usb/hcd-dwc3.h b/include/hw/usb/hcd-dwc3.h
new file mode 100644
index 0000000..586968d
--- /dev/null
+++ b/include/hw/usb/hcd-dwc3.h
@@ -0,0 +1,55 @@
+/*
+ * QEMU model of the USB DWC3 host controller emulation.
+ *
+ * Copyright (c) 2020 Xilinx Inc.
+ *
+ * Written by Vikram Garhwal<fnu.vikram@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#ifndef HCD_DWC3_H
+#define HCD_DWC3_H
+
+#include "hw/usb/hcd-xhci.h"
+#include "hw/usb/hcd-xhci-sysbus.h"
+
+#define TYPE_USB_DWC3 "usb_dwc3"
+
+#define USB_DWC3(obj) \
+ OBJECT_CHECK(USBDWC3, (obj), TYPE_USB_DWC3)
+
+#define USB_DWC3_R_MAX ((0x530 / 4) + 1)
+
+typedef struct USBDWC3 {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ MemoryRegion fifos;
+ XHCISysbusState sysbus_xhci;
+
+ uint32_t regs[USB_DWC3_R_MAX];
+ RegisterInfo regs_info[USB_DWC3_R_MAX];
+
+ struct {
+ uint8_t mode;
+ uint32_t dwc_usb3_user;
+ } cfg;
+
+} USBDWC3;
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v12 3/3] Versal: Connect DWC3 controller with virt-versal
2020-10-22 12:17 [PATCH v12 0/3] Add Versal usb model Sai Pavan Boddu
2020-10-22 12:17 ` [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module Sai Pavan Boddu
2020-10-22 12:17 ` [PATCH v12 2/3] usb: Add DWC3 model Sai Pavan Boddu
@ 2020-10-22 12:17 ` Sai Pavan Boddu
2020-10-26 16:05 ` Peter Maydell
2020-10-23 9:27 ` [PATCH v12 0/3] Add Versal usb model Edgar E. Iglesias
3 siblings, 1 reply; 12+ messages in thread
From: Sai Pavan Boddu @ 2020-10-22 12:17 UTC (permalink / raw)
To: Peter Maydell, Markus Armbruster,
'Marc-André Lureau',
Paolo Bonzini, Gerd Hoffmann, Edgar Iglesias,
Francisco Eduardo Iglesias
Cc: Eduardo Habkost, Vikram Garhwal, qemu-devel, Paul Zimmerman,
Sai Pavan Boddu, Alistair Francis, Ying Fang,
'Philippe Mathieu-Daudé'
From: Vikram Garhwal <fnu.vikram@xilinx.com>
Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its placed
in iou of lpd domain and configure it as dual port host controller. Add the
respective guest dts nodes for "xlnx-versal-virt" machine.
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
hw/arm/xlnx-versal-virt.c | 58 ++++++++++++++++++++++++++++++++++++++++++++
hw/arm/xlnx-versal.c | 34 ++++++++++++++++++++++++++
include/hw/arm/xlnx-versal.h | 14 +++++++++++
3 files changed, 106 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 03e2320..f0ac5ba 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -39,6 +39,8 @@ struct VersalVirt {
uint32_t ethernet_phy[2];
uint32_t clk_125Mhz;
uint32_t clk_25Mhz;
+ uint32_t usb;
+ uint32_t dwc;
} phandle;
struct arm_boot_info binfo;
@@ -66,6 +68,8 @@ static void fdt_create(VersalVirt *s)
s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
+ s->phandle.usb = qemu_fdt_alloc_phandle(s->fdt);
+ s->phandle.dwc = qemu_fdt_alloc_phandle(s->fdt);
/* Create /chosen node for load_dtb. */
qemu_fdt_add_subnode(s->fdt, "/chosen");
@@ -148,6 +152,59 @@ static void fdt_add_timer_nodes(VersalVirt *s)
compat, sizeof(compat));
}
+static void fdt_add_usb_xhci_nodes(VersalVirt *s)
+{
+ const char clocknames[] = "bus_clk\0ref_clk";
+ char *name = g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS);
+ const char compat[] = "xlnx,versal-dwc3";
+
+ qemu_fdt_add_subnode(s->fdt, name);
+ qemu_fdt_setprop(s->fdt, name, "compatible",
+ compat, sizeof(compat));
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+ 2, MM_USB2_CTRL_REGS,
+ 2, MM_USB2_CTRL_REGS_SIZE);
+ qemu_fdt_setprop(s->fdt, name, "clock-names",
+ clocknames, sizeof(clocknames));
+ qemu_fdt_setprop_cells(s->fdt, name, "clocks",
+ s->phandle.clk_25Mhz, s->phandle.clk_125Mhz);
+ qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0);
+ qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2);
+ qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2);
+ qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb);
+ g_free(name);
+
+ {
+ const char irq_name[] = "dwc_usb3";
+ const char compat[] = "snps,dwc3";
+
+ name = g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32,
+ MM_USB2_CTRL_REGS, MM_USB_XHCI_0);
+ qemu_fdt_add_subnode(s->fdt, name);
+ qemu_fdt_setprop(s->fdt, name, "compatible",
+ compat, sizeof(compat));
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+ 2, MM_USB_XHCI_0, 2, MM_USB_XHCI_0_SIZE);
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
+ irq_name, sizeof(irq_name));
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0,
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+ qemu_fdt_setprop_cell(s->fdt, name,
+ "snps,quirk-frame-length-adjustment", 0x20);
+ qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1);
+ qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host");
+ qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy");
+ qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0);
+ qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0);
+ qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0);
+ qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0);
+ qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc);
+ qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed");
+ g_free(name);
+ }
+}
+
static void fdt_add_uart_nodes(VersalVirt *s)
{
uint64_t addrs[] = { MM_UART1, MM_UART0 };
@@ -515,6 +572,7 @@ static void versal_virt_init(MachineState *machine)
fdt_add_gic_nodes(s);
fdt_add_timer_nodes(s);
fdt_add_zdma_nodes(s);
+ fdt_add_usb_xhci_nodes(s);
fdt_add_sd_nodes(s);
fdt_add_rtc_node(s);
fdt_add_cpu_nodes(s, psci_conduit);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 12ba6c4..ddf43db 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -145,6 +145,39 @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
}
}
+static void versal_create_usbs(Versal *s, qemu_irq *pic)
+{
+ DeviceState *dev, *xhci_dev;
+ MemoryRegion *mr;
+
+ object_initialize_child(OBJECT(s), "dwc3-0", &s->lpd.iou.usb.dwc3,
+ TYPE_USB_DWC3);
+ dev = DEVICE(&s->lpd.iou.usb.dwc3);
+ xhci_dev = DEVICE(&s->lpd.iou.usb.dwc3.sysbus_xhci);
+
+ object_property_set_link(OBJECT(xhci_dev), "dma", OBJECT(&s->mr_ps),
+ &error_abort);
+ qdev_prop_set_uint32(xhci_dev, "intrs", 1);
+ qdev_prop_set_uint32(xhci_dev, "slots", 2);
+
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0_DWC3_GLOBAL, mr);
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(xhci_dev), 0);
+ memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0, mr);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(xhci_dev), 0, pic[VERSAL_USB0_IRQ_0]);
+
+ object_initialize_child(OBJECT(s), "usb2ctrl-0", &s->lpd.iou.usb.ctrl,
+ TYPE_XILINX_VERSAL_USB2_CTRL_REGS);
+ dev = DEVICE(&s->lpd.iou.usb.ctrl);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr);
+}
+
static void versal_create_gems(Versal *s, qemu_irq *pic)
{
int i;
@@ -333,6 +366,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
versal_create_apu_cpus(s);
versal_create_apu_gic(s, pic);
versal_create_uarts(s, pic);
+ versal_create_usbs(s, pic);
versal_create_gems(s, pic);
versal_create_admas(s, pic);
versal_create_sds(s, pic);
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 8ce8e63..e0a6c66 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -21,6 +21,8 @@
#include "hw/net/cadence_gem.h"
#include "hw/rtc/xlnx-zynqmp-rtc.h"
#include "qom/object.h"
+#include "hw/usb/hcd-dwc3.h"
+#include "hw/misc/xlnx-versal-usb2-ctrl-regs.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
@@ -59,6 +61,10 @@ struct Versal {
PL011State uart[XLNX_VERSAL_NR_UARTS];
CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
+ struct {
+ USBDWC3 dwc3;
+ VersalUsb2CtrlRegs ctrl;
+ } usb;
} iou;
} lpd;
@@ -88,6 +94,7 @@ struct Versal {
#define VERSAL_UART0_IRQ_0 18
#define VERSAL_UART1_IRQ_0 19
+#define VERSAL_USB0_IRQ_0 22
#define VERSAL_GEM0_IRQ_0 56
#define VERSAL_GEM0_WAKE_IRQ_0 57
#define VERSAL_GEM1_IRQ_0 58
@@ -125,6 +132,13 @@ struct Versal {
#define MM_OCM 0xfffc0000U
#define MM_OCM_SIZE 0x40000
+#define MM_USB2_CTRL_REGS 0xFF9D0000
+#define MM_USB2_CTRL_REGS_SIZE 0x10000
+
+#define MM_USB_XHCI_0 0xFE200000
+#define MM_USB_XHCI_0_SIZE 0x10000
+#define MM_USB_XHCI_0_DWC3_GLOBAL (MM_USB_XHCI_0 + 0xC100)
+
#define MM_TOP_DDR 0x0
#define MM_TOP_DDR_SIZE 0x80000000U
#define MM_TOP_DDR_2 0x800000000ULL
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v12 0/3] Add Versal usb model
2020-10-22 12:17 [PATCH v12 0/3] Add Versal usb model Sai Pavan Boddu
` (2 preceding siblings ...)
2020-10-22 12:17 ` [PATCH v12 3/3] Versal: Connect DWC3 controller with virt-versal Sai Pavan Boddu
@ 2020-10-23 9:27 ` Edgar E. Iglesias
3 siblings, 0 replies; 12+ messages in thread
From: Edgar E. Iglesias @ 2020-10-23 9:27 UTC (permalink / raw)
To: Sai Pavan Boddu
Cc: Francisco Eduardo Iglesias, Peter Maydell, Eduardo Habkost,
Vikram Garhwal, Markus Armbruster, qemu-devel, Sai Pavan Boddu,
Edgar Iglesias, Alistair Francis, Gerd Hoffmann,
'Marc-André Lureau',
Ying Fang, Paolo Bonzini, Paul Zimmerman,
'Philippe Mathieu-Daudé'
On Thu, Oct 22, 2020 at 05:47:33PM +0530, Sai Pavan Boddu wrote:
> This patch series attempts to make 'hcd-xhci' an independent model so it can be used by both pci and system-bus interface.
On the series:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Changes for V2:
> Make XHCIState non-qom
> Use container_of functions for retriving pci device instance
> Initialize the AddressSpace pointer in PATCH 1/3 itself Changes for V3:
> Convert XHCIState to TYPE_DEVICE and register as a child of XHCIPciState.
> Changes for V4:
> Add DWC3 usb controller
> Add versal, usb2-reg module
> Connect sysbus xhci to versal virt board Changes for V5:
> Add extra info about dwc3 and usb2_regs devices in commit messages
> Use only one irq for versal usb controller
> Mark the unimplemented registers in dwc3 controller
> Rebase the patches over master.
> Move few mispalced contents from patch 2/7 to 3/7.
> Fix the author names in the header.
> Move the inclusion of "sysemu/dma.h" from patch 1/7 to 3/7 Changes for V6:
> Fixed style issue in patch 7/7
> Renamed usb2_reg model to VersalUsb2CtrlReg
> Fixed author in headers
> Changes for V7:
> Create a usb structure to keep things clean
> Remove the repeated patch in the series i.e 5/7 Changes for V8:
> Fix vmstate sturcts to support cross version migration.
> Changes for V9:
> Added recommended changes to fix vmstate migration.
> Fixed commit message on 3/7.
> Changes for V10:
> use vmstate_post_load avaialble in VMStateDescription
> tested vmstate cross migration.
> Changes for V11:
> Removed the patches which got accepted
> Changed object name "USB2Reg" -> "ctrl"
> Updated Subject line on cover letter.
> Changes for V12:
> Use reset class for usb2-ctrl-regs module
> Move the few register update to realize
> Marked registers which are unimplemented in regapi model
>
>
> Sai Pavan Boddu (1):
> misc: Add versal-usb2-ctrl-regs module
>
> Vikram Garhwal (2):
> usb: Add DWC3 model
> Versal: Connect DWC3 controller with virt-versal
>
> hw/arm/xlnx-versal-virt.c | 58 +++
> hw/arm/xlnx-versal.c | 34 ++
> hw/misc/meson.build | 1 +
> hw/misc/xlnx-versal-usb2-ctrl-regs.c | 229 +++++++++
> hw/usb/Kconfig | 6 +
> hw/usb/hcd-dwc3.c | 666 +++++++++++++++++++++++++++
> hw/usb/meson.build | 1 +
> include/hw/arm/xlnx-versal.h | 14 +
> include/hw/misc/xlnx-versal-usb2-ctrl-regs.h | 45 ++
> include/hw/usb/hcd-dwc3.h | 55 +++
> 10 files changed, 1109 insertions(+)
> create mode 100644 hw/misc/xlnx-versal-usb2-ctrl-regs.c
> create mode 100644 hw/usb/hcd-dwc3.c
> create mode 100644 include/hw/misc/xlnx-versal-usb2-ctrl-regs.h
> create mode 100644 include/hw/usb/hcd-dwc3.h
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
2020-10-22 12:17 ` [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module Sai Pavan Boddu
@ 2020-10-26 16:02 ` Peter Maydell
2020-10-26 17:28 ` Sai Pavan Boddu
0 siblings, 1 reply; 12+ messages in thread
From: Peter Maydell @ 2020-10-26 16:02 UTC (permalink / raw)
To: Sai Pavan Boddu
Cc: Francisco Eduardo Iglesias, Eduardo Habkost, Vikram Garhwal,
Markus Armbruster, QEMU Developers, Sai Pavan Boddu,
Edgar Iglesias, Alistair Francis, Gerd Hoffmann, Paolo Bonzini,
Ying Fang, Marc-André Lureau, Paul Zimmerman,
Philippe Mathieu-Daudé
On Thu, 22 Oct 2020 at 13:11, Sai Pavan Boddu
<sai.pavan.boddu@xilinx.com> wrote:
>
> This module emulates control registers of versal usb2 controller, this is added
> just to make guest happy. In general this module would control the phy-reset
> signal from usb controller, data coherency of the transactions, signals
> the host system errors received from controller.
>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
> ---
> hw/misc/meson.build | 1 +
> hw/misc/xlnx-versal-usb2-ctrl-regs.c | 229 +++++++++++++++++++++++++++
> include/hw/misc/xlnx-versal-usb2-ctrl-regs.h | 45 ++++++
This seems a bit odd. If it's a USB device (or part of a USB
device) then it should be under hw/usb, shouldn't it?
> +static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
> +{
> + VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
> + /*
> + * TODO: This should also clear USBSTS.HSE field in USB XHCI register.
> + * May be combine both the modules.
> + */
What does the hardware for this look like? You've modelled
it as two completely separate devices (this one and the
TYPE_USB_DWC3) but would it be closer to the hardware
structure to have a top-level device which has-a DWC3 ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v12 3/3] Versal: Connect DWC3 controller with virt-versal
2020-10-22 12:17 ` [PATCH v12 3/3] Versal: Connect DWC3 controller with virt-versal Sai Pavan Boddu
@ 2020-10-26 16:05 ` Peter Maydell
2020-10-26 19:28 ` Sai Pavan Boddu
0 siblings, 1 reply; 12+ messages in thread
From: Peter Maydell @ 2020-10-26 16:05 UTC (permalink / raw)
To: Sai Pavan Boddu
Cc: Francisco Eduardo Iglesias, Eduardo Habkost, Vikram Garhwal,
Markus Armbruster, QEMU Developers, Sai Pavan Boddu,
Edgar Iglesias, Alistair Francis, Gerd Hoffmann, Paolo Bonzini,
Ying Fang, Marc-André Lureau, Paul Zimmerman,
Philippe Mathieu-Daudé
On Thu, 22 Oct 2020 at 13:11, Sai Pavan Boddu
<sai.pavan.boddu@xilinx.com> wrote:
>
> From: Vikram Garhwal <fnu.vikram@xilinx.com>
>
> Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its placed
> in iou of lpd domain and configure it as dual port host controller. Add the
> respective guest dts nodes for "xlnx-versal-virt" machine.
>
> Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> +static void versal_create_usbs(Versal *s, qemu_irq *pic)
> +{
> + DeviceState *dev, *xhci_dev;
> + MemoryRegion *mr;
> +
> + object_initialize_child(OBJECT(s), "dwc3-0", &s->lpd.iou.usb.dwc3,
> + TYPE_USB_DWC3);
> + dev = DEVICE(&s->lpd.iou.usb.dwc3);
> + xhci_dev = DEVICE(&s->lpd.iou.usb.dwc3.sysbus_xhci);
If you find yourself fishing around in the internals of
another device, especially to this depth, then something's
probably not right in the structure of that device.
> +
> + object_property_set_link(OBJECT(xhci_dev), "dma", OBJECT(&s->mr_ps),
> + &error_abort);
> + qdev_prop_set_uint32(xhci_dev, "intrs", 1);
> + qdev_prop_set_uint32(xhci_dev, "slots", 2);
> +
> + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
> +
> + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
> + memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0_DWC3_GLOBAL, mr);
> + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(xhci_dev), 0);
> + memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0, mr);
For instance, rather than having to find the xhci device and
map its memory regions and connect its IRQs directly, the
usb-dwc3 device could provide and pass through those MRs and
IRQs, so that board code is only wiring up what the usb-dwc3
provides and doesn't need to know about its internals.
thanks
-- PMM
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
2020-10-26 16:02 ` Peter Maydell
@ 2020-10-26 17:28 ` Sai Pavan Boddu
2020-10-28 12:58 ` Sai Pavan Boddu
0 siblings, 1 reply; 12+ messages in thread
From: Sai Pavan Boddu @ 2020-10-26 17:28 UTC (permalink / raw)
To: Peter Maydell
Cc: Francisco Eduardo Iglesias, Eduardo Habkost, Vikram Garhwal,
Markus Armbruster, QEMU Developers, Edgar Iglesias,
Alistair Francis, Gerd Hoffmann, Paolo Bonzini, Ying Fang,
Marc-André Lureau, Paul Zimmerman,
Philippe Mathieu-Daudé
Hi Peter,
> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Monday, October 26, 2020 9:33 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>
> Cc: Markus Armbruster <armbru@redhat.com>; Marc-André Lureau
> <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> Gerd Hoffmann <kraxel@redhat.com>; Edgar Iglesias <edgari@xilinx.com>;
> Francisco Eduardo Iglesias <figlesia@xilinx.com>; QEMU Developers <qemu-
> devel@nongnu.org>; Alistair Francis <alistair.francis@wdc.com>; Eduardo
> Habkost <ehabkost@redhat.com>; Ying Fang <fangying1@huawei.com>;
> Philippe Mathieu-Daudé <philmd@redhat.com>; Vikram Garhwal
> <fnuv@xilinx.com>; Paul Zimmerman <pauldzim@gmail.com>; Sai Pavan Boddu
> <saipava@xilinx.com>
> Subject: Re: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
>
> On Thu, 22 Oct 2020 at 13:11, Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> wrote:
> >
> > This module emulates control registers of versal usb2 controller, this
> > is added just to make guest happy. In general this module would
> > control the phy-reset signal from usb controller, data coherency of
> > the transactions, signals the host system errors received from controller.
> >
> > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> > Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
> > ---
> > hw/misc/meson.build | 1 +
> > hw/misc/xlnx-versal-usb2-ctrl-regs.c | 229
> +++++++++++++++++++++++++++
> > include/hw/misc/xlnx-versal-usb2-ctrl-regs.h | 45 ++++++
>
> This seems a bit odd. If it's a USB device (or part of a USB
> device) then it should be under hw/usb, shouldn't it?
[Sai Pavan Boddu] This is a top level wrapper over hcd-dwc3 device, which is specific to versal soc. It's mostly dummy which controls the phy-reset and does frame length adjustments. It was added just to make guest happy, that is the reason it has been added to misc devices.
>
> > +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) {
> > + VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
> > + /*
> > + * TODO: This should also clear USBSTS.HSE field in USB XHCI register.
> > + * May be combine both the modules.
> > + */
>
> What does the hardware for this look like? You've modelled it as two
> completely separate devices (this one and the
> TYPE_USB_DWC3) but would it be closer to the hardware structure to have a
> top-level device which has-a DWC3 ?
[Sai Pavan Boddu] Yes, we can look at it such way. But as its specific to versal SOC, we have crafted it out and stitched them in SOC file.
Regards,
Sai Pavan
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v12 3/3] Versal: Connect DWC3 controller with virt-versal
2020-10-26 16:05 ` Peter Maydell
@ 2020-10-26 19:28 ` Sai Pavan Boddu
0 siblings, 0 replies; 12+ messages in thread
From: Sai Pavan Boddu @ 2020-10-26 19:28 UTC (permalink / raw)
To: Peter Maydell
Cc: Francisco Eduardo Iglesias, Eduardo Habkost, Vikram Garhwal,
Markus Armbruster, QEMU Developers, Edgar Iglesias,
Alistair Francis, Gerd Hoffmann, Paolo Bonzini, Ying Fang,
Marc-André Lureau, Paul Zimmerman,
Philippe Mathieu-Daudé
Hi Peter
> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Monday, October 26, 2020 9:35 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>
> Cc: Markus Armbruster <armbru@redhat.com>; Marc-André Lureau
> <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> Gerd Hoffmann <kraxel@redhat.com>; Edgar Iglesias <edgari@xilinx.com>;
> Francisco Eduardo Iglesias <figlesia@xilinx.com>; QEMU Developers <qemu-
> devel@nongnu.org>; Alistair Francis <alistair.francis@wdc.com>; Eduardo
> Habkost <ehabkost@redhat.com>; Ying Fang <fangying1@huawei.com>;
> Philippe Mathieu-Daudé <philmd@redhat.com>; Vikram Garhwal
> <fnuv@xilinx.com>; Paul Zimmerman <pauldzim@gmail.com>; Sai Pavan Boddu
> <saipava@xilinx.com>
> Subject: Re: [PATCH v12 3/3] Versal: Connect DWC3 controller with virt-versal
>
> On Thu, 22 Oct 2020 at 13:11, Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> wrote:
> >
> > From: Vikram Garhwal <fnu.vikram@xilinx.com>
> >
> > Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its
> > placed in iou of lpd domain and configure it as dual port host
> > controller. Add the respective guest dts nodes for "xlnx-versal-virt" machine.
> >
> > Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
> > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
>
>
> > +static void versal_create_usbs(Versal *s, qemu_irq *pic) {
> > + DeviceState *dev, *xhci_dev;
> > + MemoryRegion *mr;
> > +
> > + object_initialize_child(OBJECT(s), "dwc3-0", &s->lpd.iou.usb.dwc3,
> > + TYPE_USB_DWC3);
> > + dev = DEVICE(&s->lpd.iou.usb.dwc3);
> > + xhci_dev = DEVICE(&s->lpd.iou.usb.dwc3.sysbus_xhci);
>
> If you find yourself fishing around in the internals of another device, especially
> to this depth, then something's probably not right in the structure of that
> device.
[Sai Pavan Boddu] Yeah, it look pretty long. But, "s->lpd.iou.usb" defines soc domains for us.
Ex. Usb is part of low-power domain(i.e lpd) in IOU module.
And " dwc3.sysbus_xhci ", is specific to usb and is result of parenting dwc3 to xhci.
>
> > +
> > + object_property_set_link(OBJECT(xhci_dev), "dma", OBJECT(&s->mr_ps),
> > + &error_abort);
> > + qdev_prop_set_uint32(xhci_dev, "intrs", 1);
> > + qdev_prop_set_uint32(xhci_dev, "slots", 2);
> > +
> > + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
> > +
> > + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
> > + memory_region_add_subregion(&s->mr_ps,
> MM_USB_XHCI_0_DWC3_GLOBAL, mr);
> > + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(xhci_dev), 0);
> > + memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0, mr);
>
> For instance, rather than having to find the xhci device and map its memory
> regions and connect its IRQs directly, the
> usb-dwc3 device could provide and pass through those MRs and IRQs, so that
> board code is only wiring up what the usb-dwc3 provides and doesn't need to
> know about its internals.
[Sai Pavan Boddu] Yes, xhci registers can be mapped internally. We can make those changes.
Regards,
Sai Pavan
>
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
2020-10-26 17:28 ` Sai Pavan Boddu
@ 2020-10-28 12:58 ` Sai Pavan Boddu
2020-10-28 13:14 ` Peter Maydell
0 siblings, 1 reply; 12+ messages in thread
From: Sai Pavan Boddu @ 2020-10-28 12:58 UTC (permalink / raw)
To: Peter Maydell
Cc: Francisco Eduardo Iglesias, Eduardo Habkost, Vikram Garhwal,
Markus Armbruster, QEMU Developers, Edgar Iglesias,
Alistair Francis, Gerd Hoffmann, Paolo Bonzini, Ying Fang,
Marc-André Lureau, Paul Zimmerman,
Philippe Mathieu-Daudé
Hi Peter,
> -----Original Message-----
> From: Sai Pavan Boddu
> Sent: Monday, October 26, 2020 10:59 PM
> To: Peter Maydell <peter.maydell@linaro.org>
> Cc: Markus Armbruster <armbru@redhat.com>; Marc-André Lureau
> <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> Gerd Hoffmann <kraxel@redhat.com>; Edgar Iglesias <edgari@xilinx.com>;
> Francisco Eduardo Iglesias <figlesia@xilinx.com>; QEMU Developers <qemu-
> devel@nongnu.org>; Alistair Francis <alistair.francis@wdc.com>; Eduardo
> Habkost <ehabkost@redhat.com>; Ying Fang <fangying1@huawei.com>;
> Philippe Mathieu-Daudé <philmd@redhat.com>; Vikram Garhwal
> <fnuv@xilinx.com>; Paul Zimmerman <pauldzim@gmail.com>
> Subject: RE: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
>
> Hi Peter,
>
> > -----Original Message-----
> > From: Peter Maydell <peter.maydell@linaro.org>
> > Sent: Monday, October 26, 2020 9:33 PM
> > To: Sai Pavan Boddu <saipava@xilinx.com>
> > Cc: Markus Armbruster <armbru@redhat.com>; Marc-André Lureau
> > <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> > Gerd Hoffmann <kraxel@redhat.com>; Edgar Iglesias <edgari@xilinx.com>;
> > Francisco Eduardo Iglesias <figlesia@xilinx.com>; QEMU Developers
> > <qemu- devel@nongnu.org>; Alistair Francis <alistair.francis@wdc.com>;
> > Eduardo Habkost <ehabkost@redhat.com>; Ying Fang
> > <fangying1@huawei.com>; Philippe Mathieu-Daudé <philmd@redhat.com>;
> > Vikram Garhwal <fnuv@xilinx.com>; Paul Zimmerman
> <pauldzim@gmail.com>;
> > Sai Pavan Boddu <saipava@xilinx.com>
> > Subject: Re: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
> >
> > On Thu, 22 Oct 2020 at 13:11, Sai Pavan Boddu
> > <sai.pavan.boddu@xilinx.com>
> > wrote:
> > >
> > > This module emulates control registers of versal usb2 controller,
> > > this is added just to make guest happy. In general this module would
> > > control the phy-reset signal from usb controller, data coherency of
> > > the transactions, signals the host system errors received from controller.
> > >
> > > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> > > Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
> > > ---
> > > hw/misc/meson.build | 1 +
> > > hw/misc/xlnx-versal-usb2-ctrl-regs.c | 229
> > +++++++++++++++++++++++++++
> > > include/hw/misc/xlnx-versal-usb2-ctrl-regs.h | 45 ++++++
> >
> > This seems a bit odd. If it's a USB device (or part of a USB
> > device) then it should be under hw/usb, shouldn't it?
> [Sai Pavan Boddu] This is a top level wrapper over hcd-dwc3 device, which is
> specific to versal soc. It's mostly dummy which controls the phy-reset and does
> frame length adjustments. It was added just to make guest happy, that is the
> reason it has been added to misc devices.
> >
> > > +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) {
> > > + VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg-
> >opaque);
> > > + /*
> > > + * TODO: This should also clear USBSTS.HSE field in USB XHCI register.
> > > + * May be combine both the modules.
> > > + */
> >
> > What does the hardware for this look like? You've modelled it as two
> > completely separate devices (this one and the
> > TYPE_USB_DWC3) but would it be closer to the hardware structure to
> > have a top-level device which has-a DWC3 ?
> [Sai Pavan Boddu] Yes, we can look at it such way. But as its specific to versal
> SOC, we have crafted it out and stitched them in SOC file.
>
> Regards,
> Sai Pavan
[Sai Pavan Boddu] I would be sending V13 without doing any changes with this patch and addressing other comments, Please review over V13.
Thanks,
Sai Pavan
> >
> > thanks
> > -- PMM
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
2020-10-28 12:58 ` Sai Pavan Boddu
@ 2020-10-28 13:14 ` Peter Maydell
2020-10-28 13:50 ` Sai Pavan Boddu
0 siblings, 1 reply; 12+ messages in thread
From: Peter Maydell @ 2020-10-28 13:14 UTC (permalink / raw)
To: Sai Pavan Boddu
Cc: Francisco Eduardo Iglesias, Eduardo Habkost, Vikram Garhwal,
Markus Armbruster, QEMU Developers, Edgar Iglesias,
Alistair Francis, Gerd Hoffmann, Paolo Bonzini, Ying Fang,
Marc-André Lureau, Paul Zimmerman,
Philippe Mathieu-Daudé
On Wed, 28 Oct 2020 at 12:58, Sai Pavan Boddu <saipava@xilinx.com> wrote:
>
> Hi Peter,
>
> > -----Original Message-----
> > From: Sai Pavan Boddu
> > Sent: Monday, October 26, 2020 10:59 PM
> > To: Peter Maydell <peter.maydell@linaro.org>
> > Cc: Markus Armbruster <armbru@redhat.com>; Marc-André Lureau
> > <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> > Gerd Hoffmann <kraxel@redhat.com>; Edgar Iglesias <edgari@xilinx.com>;
> > Francisco Eduardo Iglesias <figlesia@xilinx.com>; QEMU Developers <qemu-
> > devel@nongnu.org>; Alistair Francis <alistair.francis@wdc.com>; Eduardo
> > Habkost <ehabkost@redhat.com>; Ying Fang <fangying1@huawei.com>;
> > Philippe Mathieu-Daudé <philmd@redhat.com>; Vikram Garhwal
> > <fnuv@xilinx.com>; Paul Zimmerman <pauldzim@gmail.com>
> > Subject: RE: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
> >
> > Hi Peter,
> >
> > > -----Original Message-----
> > > From: Peter Maydell <peter.maydell@linaro.org>
> > > Sent: Monday, October 26, 2020 9:33 PM
> > > To: Sai Pavan Boddu <saipava@xilinx.com>
> > > Cc: Markus Armbruster <armbru@redhat.com>; Marc-André Lureau
> > > <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> > > Gerd Hoffmann <kraxel@redhat.com>; Edgar Iglesias <edgari@xilinx.com>;
> > > Francisco Eduardo Iglesias <figlesia@xilinx.com>; QEMU Developers
> > > <qemu- devel@nongnu.org>; Alistair Francis <alistair.francis@wdc.com>;
> > > Eduardo Habkost <ehabkost@redhat.com>; Ying Fang
> > > <fangying1@huawei.com>; Philippe Mathieu-Daudé <philmd@redhat.com>;
> > > Vikram Garhwal <fnuv@xilinx.com>; Paul Zimmerman
> > <pauldzim@gmail.com>;
> > > Sai Pavan Boddu <saipava@xilinx.com>
> > > Subject: Re: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
> > >
> > > On Thu, 22 Oct 2020 at 13:11, Sai Pavan Boddu
> > > <sai.pavan.boddu@xilinx.com>
> > > wrote:
> > > >
> > > > This module emulates control registers of versal usb2 controller,
> > > > this is added just to make guest happy. In general this module would
> > > > control the phy-reset signal from usb controller, data coherency of
> > > > the transactions, signals the host system errors received from controller.
> > > >
> > > > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> > > > Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
> > > > ---
> > > > hw/misc/meson.build | 1 +
> > > > hw/misc/xlnx-versal-usb2-ctrl-regs.c | 229
> > > +++++++++++++++++++++++++++
> > > > include/hw/misc/xlnx-versal-usb2-ctrl-regs.h | 45 ++++++
> > >
> > > This seems a bit odd. If it's a USB device (or part of a USB
> > > device) then it should be under hw/usb, shouldn't it?
> > [Sai Pavan Boddu] This is a top level wrapper over hcd-dwc3 device, which is
> > specific to versal soc. It's mostly dummy which controls the phy-reset and does
> > frame length adjustments. It was added just to make guest happy, that is the
> > reason it has been added to misc devices.
> > >
> > > > +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) {
> > > > + VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg-
> > >opaque);
> > > > + /*
> > > > + * TODO: This should also clear USBSTS.HSE field in USB XHCI register.
> > > > + * May be combine both the modules.
> > > > + */
> > >
> > > What does the hardware for this look like? You've modelled it as two
> > > completely separate devices (this one and the
> > > TYPE_USB_DWC3) but would it be closer to the hardware structure to
> > > have a top-level device which has-a DWC3 ?
> > [Sai Pavan Boddu] Yes, we can look at it such way. But as its specific to versal
> > SOC, we have crafted it out and stitched them in SOC file.
> >
> > Regards,
> > Sai Pavan
> [Sai Pavan Boddu] I would be sending V13 without doing any changes with this patch and addressing other comments, Please review over V13.
You have my review comments above. I think the way you've structured
this isn't really the best way to do it.
thanks
-- PMM
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
2020-10-28 13:14 ` Peter Maydell
@ 2020-10-28 13:50 ` Sai Pavan Boddu
0 siblings, 0 replies; 12+ messages in thread
From: Sai Pavan Boddu @ 2020-10-28 13:50 UTC (permalink / raw)
To: Peter Maydell
Cc: Francisco Eduardo Iglesias, Eduardo Habkost, Vikram Garhwal,
Markus Armbruster, QEMU Developers, Edgar Iglesias,
Alistair Francis, Gerd Hoffmann, Paolo Bonzini, Ying Fang,
Marc-André Lureau, Paul Zimmerman,
Philippe Mathieu-Daudé
Hi Peter,
> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: Wednesday, October 28, 2020 6:44 PM
> To: Sai Pavan Boddu <saipava@xilinx.com>
> Cc: Markus Armbruster <armbru@redhat.com>; Marc-André Lureau
> <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> Gerd Hoffmann <kraxel@redhat.com>; Edgar Iglesias <edgari@xilinx.com>;
> Francisco Eduardo Iglesias <figlesia@xilinx.com>; QEMU Developers <qemu-
> devel@nongnu.org>; Alistair Francis <alistair.francis@wdc.com>; Eduardo
> Habkost <ehabkost@redhat.com>; Ying Fang <fangying1@huawei.com>;
> Philippe Mathieu-Daudé <philmd@redhat.com>; Vikram Garhwal
> <fnuv@xilinx.com>; Paul Zimmerman <pauldzim@gmail.com>
> Subject: Re: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
>
> On Wed, 28 Oct 2020 at 12:58, Sai Pavan Boddu <saipava@xilinx.com> wrote:
> >
> > Hi Peter,
> >
> > > -----Original Message-----
> > > From: Sai Pavan Boddu
> > > Sent: Monday, October 26, 2020 10:59 PM
> > > To: Peter Maydell <peter.maydell@linaro.org>
> > > Cc: Markus Armbruster <armbru@redhat.com>; Marc-André Lureau
> > > <marcandre.lureau@redhat.com>; Paolo Bonzini <pbonzini@redhat.com>;
> > > Gerd Hoffmann <kraxel@redhat.com>; Edgar Iglesias
> > > <edgari@xilinx.com>; Francisco Eduardo Iglesias
> > > <figlesia@xilinx.com>; QEMU Developers <qemu- devel@nongnu.org>;
> > > Alistair Francis <alistair.francis@wdc.com>; Eduardo Habkost
> > > <ehabkost@redhat.com>; Ying Fang <fangying1@huawei.com>; Philippe
> > > Mathieu-Daudé <philmd@redhat.com>; Vikram Garhwal
> <fnuv@xilinx.com>;
> > > Paul Zimmerman <pauldzim@gmail.com>
> > > Subject: RE: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module
> > >
> > > Hi Peter,
> > >
> > > > -----Original Message-----
> > > > From: Peter Maydell <peter.maydell@linaro.org>
> > > > Sent: Monday, October 26, 2020 9:33 PM
> > > > To: Sai Pavan Boddu <saipava@xilinx.com>
> > > > Cc: Markus Armbruster <armbru@redhat.com>; Marc-André Lureau
> > > > <marcandre.lureau@redhat.com>; Paolo Bonzini
> > > > <pbonzini@redhat.com>; Gerd Hoffmann <kraxel@redhat.com>; Edgar
> > > > Iglesias <edgari@xilinx.com>; Francisco Eduardo Iglesias
> > > > <figlesia@xilinx.com>; QEMU Developers
> > > > <qemu- devel@nongnu.org>; Alistair Francis
> > > > <alistair.francis@wdc.com>; Eduardo Habkost <ehabkost@redhat.com>;
> > > > Ying Fang <fangying1@huawei.com>; Philippe Mathieu-Daudé
> > > > <philmd@redhat.com>; Vikram Garhwal <fnuv@xilinx.com>; Paul
> > > > Zimmerman
> > > <pauldzim@gmail.com>;
> > > > Sai Pavan Boddu <saipava@xilinx.com>
> > > > Subject: Re: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs
> > > > module
> > > >
> > > > On Thu, 22 Oct 2020 at 13:11, Sai Pavan Boddu
> > > > <sai.pavan.boddu@xilinx.com>
> > > > wrote:
> > > > >
> > > > > This module emulates control registers of versal usb2
> > > > > controller, this is added just to make guest happy. In general
> > > > > this module would control the phy-reset signal from usb
> > > > > controller, data coherency of the transactions, signals the host system
> errors received from controller.
> > > > >
> > > > > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> > > > > Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
> > > > > ---
> > > > > hw/misc/meson.build | 1 +
> > > > > hw/misc/xlnx-versal-usb2-ctrl-regs.c | 229
> > > > +++++++++++++++++++++++++++
> > > > > include/hw/misc/xlnx-versal-usb2-ctrl-regs.h | 45 ++++++
> > > >
> > > > This seems a bit odd. If it's a USB device (or part of a USB
> > > > device) then it should be under hw/usb, shouldn't it?
> > > [Sai Pavan Boddu] This is a top level wrapper over hcd-dwc3 device,
> > > which is specific to versal soc. It's mostly dummy which controls
> > > the phy-reset and does frame length adjustments. It was added just
> > > to make guest happy, that is the reason it has been added to misc devices.
> > > >
> > > > > +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) {
> > > > > + VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg-
> > > >opaque);
> > > > > + /*
> > > > > + * TODO: This should also clear USBSTS.HSE field in USB XHCI
> register.
> > > > > + * May be combine both the modules.
> > > > > + */
> > > >
> > > > What does the hardware for this look like? You've modelled it as
> > > > two completely separate devices (this one and the
> > > > TYPE_USB_DWC3) but would it be closer to the hardware structure to
> > > > have a top-level device which has-a DWC3 ?
> > > [Sai Pavan Boddu] Yes, we can look at it such way. But as its
> > > specific to versal SOC, we have crafted it out and stitched them in SOC file.
> > >
> > > Regards,
> > > Sai Pavan
> > [Sai Pavan Boddu] I would be sending V13 without doing any changes with
> this patch and addressing other comments, Please review over V13.
>
> You have my review comments above. I think the way you've structured this
> isn't really the best way to do it.
[Sai Pavan Boddu] Ok, I would move this into USB folder as its related.
But this device is not like a top level module of DWC3 model, is used for handling phy-reset signal & power management of usb port.
It's not a good idea to embedded this device into DWC3 module.
Anyway, I would attempt to create a subsystem by making dwc3 and usb2-ctrl-regs child of one device.
Regards,
Sai Pavan
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-10-28 13:51 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-22 12:17 [PATCH v12 0/3] Add Versal usb model Sai Pavan Boddu
2020-10-22 12:17 ` [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module Sai Pavan Boddu
2020-10-26 16:02 ` Peter Maydell
2020-10-26 17:28 ` Sai Pavan Boddu
2020-10-28 12:58 ` Sai Pavan Boddu
2020-10-28 13:14 ` Peter Maydell
2020-10-28 13:50 ` Sai Pavan Boddu
2020-10-22 12:17 ` [PATCH v12 2/3] usb: Add DWC3 model Sai Pavan Boddu
2020-10-22 12:17 ` [PATCH v12 3/3] Versal: Connect DWC3 controller with virt-versal Sai Pavan Boddu
2020-10-26 16:05 ` Peter Maydell
2020-10-26 19:28 ` Sai Pavan Boddu
2020-10-23 9:27 ` [PATCH v12 0/3] Add Versal usb model Edgar E. Iglesias
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