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* [Bug 1885350] [NEW] RISCV dynamic rounding mode is not behaving correctly
@ 2020-06-27  5:47 Mina Magdy
  2020-06-27 11:08 ` [Bug 1885350] " Mina Magdy
                   ` (7 more replies)
  0 siblings, 8 replies; 9+ messages in thread
From: Mina Magdy @ 2020-06-27  5:47 UTC (permalink / raw)
  To: qemu-devel

Public bug reported:

Hello,

I’ve gone through the RISC-V code in latest QEMU release
(qemu-5.0.0-rc2) and when checking the Floating point encodings I found
the rounding mode is only updated if the opcode field “rm” is changed
“ctx->frm == rm”. But according to RISC-V Volume I: Unprivileged ISA,
there’s a dynamic mode when rm=7 where the rounding mode is set with frm
value.

So for the same rm value (=7) and when changing frm value seeking
different rounding modes, and according to the below code, the rounding
mode won’t be updated. Please correct me if I got this implementation
wrong.

static void gen_set_rm(DisasContext *ctx, int rm)
{
    TCGv_i32 t0;
    if (ctx->frm == rm) {
        return;
    }
    ctx->frm = rm;
    t0 = tcg_const_i32(rm);
    gen_helper_set_rounding_mode(cpu_env, t0);
    tcg_temp_free_i32(t0);
}


My testcase:
I set statically the rm field in the instruction to 7 and before this execution I changed the value of frm field in fcsr register. For the 1st time it worked (according to the code above, the rm is updated so the round mode will also be updated). But when changing fcsr register an re-execute the instruction, there's no difference and the rounding mode is the same like the previous frm value.

** Affects: qemu
     Importance: Undecided
         Status: New

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https://bugs.launchpad.net/bugs/1885350

Title:
  RISCV dynamic rounding mode is not behaving correctly

Status in QEMU:
  New

Bug description:
  Hello,

  I’ve gone through the RISC-V code in latest QEMU release
  (qemu-5.0.0-rc2) and when checking the Floating point encodings I
  found the rounding mode is only updated if the opcode field “rm” is
  changed “ctx->frm == rm”. But according to RISC-V Volume I:
  Unprivileged ISA, there’s a dynamic mode when rm=7 where the rounding
  mode is set with frm value.

  So for the same rm value (=7) and when changing frm value seeking
  different rounding modes, and according to the below code, the
  rounding mode won’t be updated. Please correct me if I got this
  implementation wrong.

  static void gen_set_rm(DisasContext *ctx, int rm)
  {
      TCGv_i32 t0;
      if (ctx->frm == rm) {
          return;
      }
      ctx->frm = rm;
      t0 = tcg_const_i32(rm);
      gen_helper_set_rounding_mode(cpu_env, t0);
      tcg_temp_free_i32(t0);
  }

  
  My testcase:
  I set statically the rm field in the instruction to 7 and before this execution I changed the value of frm field in fcsr register. For the 1st time it worked (according to the code above, the rm is updated so the round mode will also be updated). But when changing fcsr register an re-execute the instruction, there's no difference and the rounding mode is the same like the previous frm value.

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^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-07-17  4:28 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-27  5:47 [Bug 1885350] [NEW] RISCV dynamic rounding mode is not behaving correctly Mina Magdy
2020-06-27 11:08 ` [Bug 1885350] " Mina Magdy
2020-06-30 17:34 ` Alistair Francis
2020-06-30 20:43 ` Alistair Francis
2020-06-30 20:59 ` Mina Magdy
2020-11-19 20:21 ` Alistair Francis
2020-12-22  0:53 ` Alistair Francis
2021-05-17 18:58 ` Thomas Huth
2021-07-17  4:17 ` Launchpad Bug Tracker

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