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From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com,
	richard.henderson@linaro.org, bcain@quicinc.com
Subject: [PATCH v4 13/26] Hexagon (target/hexagon) cleanup ternary operators in semantics
Date: Thu,  8 Apr 2021 20:07:41 -0500	[thread overview]
Message-ID: <1617930474-31979-14-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1617930474-31979-1-git-send-email-tsimpson@quicinc.com>

Change  (cond ? (res = x) : (res = y)) to res = (cond ? x : y)

This makes the semnatics easier to for idef-parser to deal with

The following instructions are impacted
    C2_any8
    C2_all8
    C2_mux
    C2_muxii
    C2_muxir
    C2_muxri

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/imported/compare.idef | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/hexagon/imported/compare.idef b/target/hexagon/imported/compare.idef
index 3551467..abd016f 100644
--- a/target/hexagon/imported/compare.idef
+++ b/target/hexagon/imported/compare.idef
@@ -198,11 +198,11 @@ Q6INSN(C4_or_orn,"Pd4=or(Ps4,or(Pt4,!Pu4))",ATTRIBS(A_CRSLOT23),
 
 Q6INSN(C2_any8,"Pd4=any8(Ps4)",ATTRIBS(A_CRSLOT23),
 "Logical ANY of low 8 predicate bits",
-{ PsV ? (PdV=0xff) : (PdV=0x00); })
+{ PdV = (PsV ? 0xff : 0x00); })
 
 Q6INSN(C2_all8,"Pd4=all8(Ps4)",ATTRIBS(A_CRSLOT23),
 "Logical ALL of low 8 predicate bits",
-{ (PsV==0xff) ? (PdV=0xff) : (PdV=0x00); })
+{ PdV = (PsV == 0xff ? 0xff : 0x00); })
 
 Q6INSN(C2_vitpack,"Rd32=vitpack(Ps4,Pt4)",ATTRIBS(),
 "Pack the odd and even bits of two predicate registers",
@@ -212,7 +212,7 @@ Q6INSN(C2_vitpack,"Rd32=vitpack(Ps4,Pt4)",ATTRIBS(),
 
 Q6INSN(C2_mux,"Rd32=mux(Pu4,Rs32,Rt32)",ATTRIBS(),
 "Scalar MUX",
-{ (fLSBOLD(PuV)) ? (RdV=RsV):(RdV=RtV); })
+{ RdV = (fLSBOLD(PuV) ? RsV : RtV); })
 
 
 Q6INSN(C2_cmovenewit,"if (Pu4.new) Rd32=#s12",ATTRIBS(A_ARCHV2),
@@ -269,18 +269,18 @@ Q6INSN(C2_ccombinewf,"if (!Pu4) Rdd32=combine(Rs32,Rt32)",ATTRIBS(A_ARCHV2),
 
 Q6INSN(C2_muxii,"Rd32=mux(Pu4,#s8,#S8)",ATTRIBS(A_ARCHV2),
 "Scalar MUX immediates",
-{ fIMMEXT(siV); (fLSBOLD(PuV)) ? (RdV=siV):(RdV=SiV); })
+{ fIMMEXT(siV); RdV = (fLSBOLD(PuV) ? siV : SiV); })
 
 
 
 Q6INSN(C2_muxir,"Rd32=mux(Pu4,Rs32,#s8)",ATTRIBS(A_ARCHV2),
 "Scalar MUX register immediate",
-{ fIMMEXT(siV); (fLSBOLD(PuV)) ? (RdV=RsV):(RdV=siV); })
+{ fIMMEXT(siV); RdV = (fLSBOLD(PuV) ? RsV : siV); })
 
 
 Q6INSN(C2_muxri,"Rd32=mux(Pu4,#s8,Rs32)",ATTRIBS(A_ARCHV2),
 "Scalar MUX register immediate",
-{ fIMMEXT(siV); (fLSBOLD(PuV)) ? (RdV=siV):(RdV=RsV); })
+{ fIMMEXT(siV); RdV = (fLSBOLD(PuV) ? siV : RsV); })
 
 
 
-- 
2.7.4



  parent reply	other threads:[~2021-04-09  1:20 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-09  1:07 [PATCH v4 00/26] Hexagon (target/hexagon) update Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 01/26] Hexagon (target/hexagon) TCG generation cleanup Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 02/26] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 03/26] Hexagon (target/hexagon) remove unnecessary inline directives Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 04/26] Hexagon (target/hexagon) use env_archcpu and env_cpu Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 05/26] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 06/26] Hexagon (target/hexagon) decide if pred has been written at TCG gen time Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 07/26] Hexagon (target/hexagon) change variables from int to bool when appropriate Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 08/26] Hexagon (target/hexagon) remove unused carry_from_add64 function Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 09/26] Hexagon (target/hexagon) change type of softfloat_roundingmodes Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 10/26] Hexagon (target/hexagon) use softfloat default NaN and tininess Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 11/26] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 12/26] Hexagon (target/hexagon) use softfloat for float-to-int conversions Taylor Simpson
2021-04-09  1:07 ` Taylor Simpson [this message]
2021-04-09  1:07 ` [PATCH v4 14/26] Hexagon (target/hexagon) cleanup reg_field_info definition Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 15/26] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 16/26] Hexagon (target/hexagon) compile all debug code Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 17/26] Hexagon (target/hexagon) add F2_sfrecipa instruction Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 18/26] Hexagon (target/hexagon) add F2_sfinvsqrta Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 19/26] Hexagon (target/hexagon) add A5_ACS (vacsh) Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 20/26] Hexagon (target/hexagon) add A6_vminub_RdP Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 21/26] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 22/26] Hexagon (target/hexagon) circular addressing Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 23/26] Hexagon (target/hexagon) bit reverse (brev) addressing Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 24/26] Hexagon (target/hexagon) load and unpack bytes instructions Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 25/26] Hexagon (target/hexagon) load into shifted register instructions Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 26/26] Hexagon (target/hexagon) CABAC decode bin Taylor Simpson
2021-04-27 16:27 ` [PATCH v4 00/26] Hexagon (target/hexagon) update Richard Henderson
2021-04-28 21:12 ` Richard Henderson
2021-04-28 23:20   ` Taylor Simpson
2021-04-28 23:53     ` Richard Henderson

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