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From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com,
	richard.henderson@linaro.org, bcain@quicinc.com
Subject: [PATCH v4 02/26] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair
Date: Thu,  8 Apr 2021 20:07:30 -0500	[thread overview]
Message-ID: <1617930474-31979-3-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1617930474-31979-1-git-send-email-tsimpson@quicinc.com>

Similar to previous cleanup of gen_log_predicated_reg_write

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/genptr.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 87f5d92..07d970f 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -69,36 +69,35 @@ static inline void gen_log_reg_write(int rnum, TCGv val)
 static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
 {
     TCGv val32 = tcg_temp_new();
-    TCGv one = tcg_const_tl(1);
     TCGv zero = tcg_const_tl(0);
     TCGv slot_mask = tcg_temp_new();
 
     tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
     /* Low word */
     tcg_gen_extrl_i64_i32(val32, val);
-    tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
-                       val32, hex_new_value[rnum]);
-#if HEX_DEBUG
-    /* Do this so HELPER(debug_commit_end) will know */
-    tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum],
+    tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum],
                        slot_mask, zero,
-                       one, hex_reg_written[rnum]);
-#endif
-
+                       val32, hex_new_value[rnum]);
     /* High word */
     tcg_gen_extrh_i64_i32(val32, val);
     tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
                        slot_mask, zero,
                        val32, hex_new_value[rnum + 1]);
 #if HEX_DEBUG
-    /* Do this so HELPER(debug_commit_end) will know */
-    tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum + 1],
-                       slot_mask, zero,
-                       one, hex_reg_written[rnum + 1]);
+    /*
+     * Do this so HELPER(debug_commit_end) will know
+     *
+     * Note that slot_mask indicates the value is not written
+     * (i.e., slot was cancelled), so we create a true/false value before
+     * or'ing with hex_reg_written[rnum].
+     */
+    tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
+    tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
+    tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1],
+                  slot_mask);
 #endif
 
     tcg_temp_free(val32);
-    tcg_temp_free(one);
     tcg_temp_free(zero);
     tcg_temp_free(slot_mask);
 }
-- 
2.7.4



  parent reply	other threads:[~2021-04-09  1:19 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-09  1:07 [PATCH v4 00/26] Hexagon (target/hexagon) update Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 01/26] Hexagon (target/hexagon) TCG generation cleanup Taylor Simpson
2021-04-09  1:07 ` Taylor Simpson [this message]
2021-04-09  1:07 ` [PATCH v4 03/26] Hexagon (target/hexagon) remove unnecessary inline directives Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 04/26] Hexagon (target/hexagon) use env_archcpu and env_cpu Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 05/26] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 06/26] Hexagon (target/hexagon) decide if pred has been written at TCG gen time Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 07/26] Hexagon (target/hexagon) change variables from int to bool when appropriate Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 08/26] Hexagon (target/hexagon) remove unused carry_from_add64 function Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 09/26] Hexagon (target/hexagon) change type of softfloat_roundingmodes Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 10/26] Hexagon (target/hexagon) use softfloat default NaN and tininess Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 11/26] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 12/26] Hexagon (target/hexagon) use softfloat for float-to-int conversions Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 13/26] Hexagon (target/hexagon) cleanup ternary operators in semantics Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 14/26] Hexagon (target/hexagon) cleanup reg_field_info definition Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 15/26] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 16/26] Hexagon (target/hexagon) compile all debug code Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 17/26] Hexagon (target/hexagon) add F2_sfrecipa instruction Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 18/26] Hexagon (target/hexagon) add F2_sfinvsqrta Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 19/26] Hexagon (target/hexagon) add A5_ACS (vacsh) Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 20/26] Hexagon (target/hexagon) add A6_vminub_RdP Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 21/26] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 22/26] Hexagon (target/hexagon) circular addressing Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 23/26] Hexagon (target/hexagon) bit reverse (brev) addressing Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 24/26] Hexagon (target/hexagon) load and unpack bytes instructions Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 25/26] Hexagon (target/hexagon) load into shifted register instructions Taylor Simpson
2021-04-09  1:07 ` [PATCH v4 26/26] Hexagon (target/hexagon) CABAC decode bin Taylor Simpson
2021-04-27 16:27 ` [PATCH v4 00/26] Hexagon (target/hexagon) update Richard Henderson
2021-04-28 21:12 ` Richard Henderson
2021-04-28 23:20   ` Taylor Simpson
2021-04-28 23:53     ` Richard Henderson

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