From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com,
richard.henderson@linaro.org, bcain@quicinc.com
Subject: [PATCH v4 19/26] Hexagon (target/hexagon) add A5_ACS (vacsh)
Date: Thu, 8 Apr 2021 20:07:47 -0500 [thread overview]
Message-ID: <1617930474-31979-20-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1617930474-31979-1-git-send-email-tsimpson@quicinc.com>
Rxx32,Pe4 = vacsh(Rss32, Rtt32)
Add compare and select elements of two vectors
Test cases in tests/tcg/hexagon/multi_result.c
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/gen_tcg.h | 5 +++
target/hexagon/helper.h | 2 +
target/hexagon/imported/alu.idef | 19 ++++++++++
target/hexagon/imported/encode_pp.def | 1 +
target/hexagon/op_helper.c | 33 +++++++++++++++++
tests/tcg/hexagon/multi_result.c | 69 +++++++++++++++++++++++++++++++++++
6 files changed, 129 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index d78e7b8..93310c5 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -199,6 +199,11 @@
* Mathematical operations with more than one definition require
* special handling
*/
+#define fGEN_TCG_A5_ACS(SHORTCODE) \
+ do { \
+ gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \
+ gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV); \
+ } while (0)
/*
* Approximate reciprocal
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index cb7508f..3824ae0 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -26,6 +26,8 @@ DEF_HELPER_2(commit_store, void, env, int)
DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32)
DEF_HELPER_3(sfrecipa, i64, env, f32, f32)
DEF_HELPER_2(sfinvsqrta, i64, env, f32)
+DEF_HELPER_4(vacsh_val, s64, env, s64, s64, s64)
+DEF_HELPER_FLAGS_4(vacsh_pred, TCG_CALL_NO_RWG_SE, s32, env, s64, s64, s64)
/* Floating point */
DEF_HELPER_2(conv_sf2df, f64, env, f32)
diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu.idef
index 45cc529..e8cc52c 100644
--- a/target/hexagon/imported/alu.idef
+++ b/target/hexagon/imported/alu.idef
@@ -1240,6 +1240,25 @@ MINMAX(uw,WORD,UWORD,2)
#undef VMINORMAX3
+Q6INSN(A5_ACS,"Rxx32,Pe4=vacsh(Rss32,Rtt32)",ATTRIBS(),
+"Add Compare and Select elements of two vectors, record the maximums and the decisions ",
+{
+ fHIDE(int i;)
+ fHIDE(int xv;)
+ fHIDE(int sv;)
+ fHIDE(int tv;)
+ for (i = 0; i < 4; i++) {
+ xv = (int) fGETHALF(i,RxxV);
+ sv = (int) fGETHALF(i,RssV);
+ tv = (int) fGETHALF(i,RttV);
+ xv = xv + tv; //assumes 17bit datapath
+ sv = sv - tv; //assumes 17bit datapath
+ fSETBIT(i*2, PeV, (xv > sv));
+ fSETBIT(i*2+1,PeV, (xv > sv));
+ fSETHALF(i, RxxV, fSATH(fMAX(xv,sv)));
+ }
+})
+
/**********************************************/
/* Vector Min/Max */
/**********************************************/
diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/imported/encode_pp.def
index 18fe45d..87e0426 100644
--- a/target/hexagon/imported/encode_pp.def
+++ b/target/hexagon/imported/encode_pp.def
@@ -1017,6 +1017,7 @@ MPY_ENC(M7_dcmpyiwc_acc, "1010","xxxxx","1","0","1","0","10")
+MPY_ENC(A5_ACS, "1010","xxxxx","0","1","0","1","ee")
/*
*/
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index a25fb98..f9fb655 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -347,6 +347,39 @@ uint64_t HELPER(sfinvsqrta)(CPUHexagonState *env, float32 RsV)
return ((uint64_t)RdV << 32) | PeV;
}
+int64_t HELPER(vacsh_val)(CPUHexagonState *env,
+ int64_t RxxV, int64_t RssV, int64_t RttV)
+{
+ for (int i = 0; i < 4; i++) {
+ int xv = sextract64(RxxV, i * 16, 16);
+ int sv = sextract64(RssV, i * 16, 16);
+ int tv = sextract64(RttV, i * 16, 16);
+ int max;
+ xv = xv + tv;
+ sv = sv - tv;
+ max = xv > sv ? xv : sv;
+ /* Note that fSATH can set the OVF bit in usr */
+ RxxV = deposit64(RxxV, i * 16, 16, fSATH(max));
+ }
+ return RxxV;
+}
+
+int32_t HELPER(vacsh_pred)(CPUHexagonState *env,
+ int64_t RxxV, int64_t RssV, int64_t RttV)
+{
+ int32_t PeV = 0;
+ for (int i = 0; i < 4; i++) {
+ int xv = sextract64(RxxV, i * 16, 16);
+ int sv = sextract64(RssV, i * 16, 16);
+ int tv = sextract64(RttV, i * 16, 16);
+ xv = xv + tv;
+ sv = sv - tv;
+ PeV = deposit32(PeV, i * 2, 1, (xv > sv));
+ PeV = deposit32(PeV, i * 2 + 1, 1, (xv > sv));
+ }
+ return PeV;
+}
+
/*
* mem_noshuf
* Section 5.5 of the Hexagon V67 Programmer's Reference Manual
diff --git a/tests/tcg/hexagon/multi_result.c b/tests/tcg/hexagon/multi_result.c
index 67aa462..c21148f 100644
--- a/tests/tcg/hexagon/multi_result.c
+++ b/tests/tcg/hexagon/multi_result.c
@@ -45,8 +45,41 @@ static int sfinvsqrta(int Rs, int *pred_result)
return result;
}
+static long long vacsh(long long Rxx, long long Rss, long long Rtt,
+ int *pred_result, int *ovf_result)
+{
+ long long result = Rxx;
+ int predval;
+ int usr;
+
+ /*
+ * This instruction can set bit 0 (OVF/overflow) in usr
+ * Clear the bit first, then return that bit to the caller
+ */
+ asm volatile("r2 = usr\n\t"
+ "r2 = clrbit(r2, #0)\n\t" /* clear overflow bit */
+ "usr = r2\n\t"
+ "%0,p0 = vacsh(%3, %4)\n\t"
+ "%1 = p0\n\t"
+ "%2 = usr\n\t"
+ : "+r"(result), "=r"(predval), "=r"(usr)
+ : "r"(Rss), "r"(Rtt)
+ : "r2", "p0", "usr");
+ *pred_result = predval;
+ *ovf_result = (usr & 1);
+ return result;
+}
+
int err;
+static void check_ll(long long val, long long expect)
+{
+ if (val != expect) {
+ printf("ERROR: 0x%016llx != 0x%016llx\n", val, expect);
+ err++;
+ }
+}
+
static void check(int val, int expect)
{
if (val != expect) {
@@ -87,10 +120,46 @@ static void test_sfinvsqrta()
check_p(pred_result, 0x0);
}
+static void test_vacsh()
+{
+ long long res64;
+ int pred_result;
+ int ovf_result;
+
+ res64 = vacsh(0x0004000300020001LL,
+ 0x0001000200030004LL,
+ 0x0000000000000000LL, &pred_result, &ovf_result);
+ check_ll(res64, 0x0004000300030004LL);
+ check_p(pred_result, 0xf0);
+ check(ovf_result, 0);
+
+ res64 = vacsh(0x0004000300020001LL,
+ 0x0001000200030004LL,
+ 0x000affff000d0000LL, &pred_result, &ovf_result);
+ check_ll(res64, 0x000e0003000f0004LL);
+ check_p(pred_result, 0xcc);
+ check(ovf_result, 0);
+
+ res64 = vacsh(0x00047fff00020001LL,
+ 0x00017fff00030004LL,
+ 0x000a0fff000d0000LL, &pred_result, &ovf_result);
+ check_ll(res64, 0x000e7fff000f0004LL);
+ check_p(pred_result, 0xfc);
+ check(ovf_result, 1);
+
+ res64 = vacsh(0x0004000300020001LL,
+ 0x0001000200030009LL,
+ 0x000affff000d0001LL, &pred_result, &ovf_result);
+ check_ll(res64, 0x000e0003000f0008LL);
+ check_p(pred_result, 0xcc);
+ check(ovf_result, 0);
+}
+
int main()
{
test_sfrecipa();
test_sfinvsqrta();
+ test_vacsh();
puts(err ? "FAIL" : "PASS");
return err;
--
2.7.4
next prev parent reply other threads:[~2021-04-09 1:16 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-09 1:07 [PATCH v4 00/26] Hexagon (target/hexagon) update Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 01/26] Hexagon (target/hexagon) TCG generation cleanup Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 02/26] Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 03/26] Hexagon (target/hexagon) remove unnecessary inline directives Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 04/26] Hexagon (target/hexagon) use env_archcpu and env_cpu Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 05/26] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 06/26] Hexagon (target/hexagon) decide if pred has been written at TCG gen time Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 07/26] Hexagon (target/hexagon) change variables from int to bool when appropriate Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 08/26] Hexagon (target/hexagon) remove unused carry_from_add64 function Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 09/26] Hexagon (target/hexagon) change type of softfloat_roundingmodes Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 10/26] Hexagon (target/hexagon) use softfloat default NaN and tininess Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 11/26] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 12/26] Hexagon (target/hexagon) use softfloat for float-to-int conversions Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 13/26] Hexagon (target/hexagon) cleanup ternary operators in semantics Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 14/26] Hexagon (target/hexagon) cleanup reg_field_info definition Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 15/26] Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 16/26] Hexagon (target/hexagon) compile all debug code Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 17/26] Hexagon (target/hexagon) add F2_sfrecipa instruction Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 18/26] Hexagon (target/hexagon) add F2_sfinvsqrta Taylor Simpson
2021-04-09 1:07 ` Taylor Simpson [this message]
2021-04-09 1:07 ` [PATCH v4 20/26] Hexagon (target/hexagon) add A6_vminub_RdP Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 21/26] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 22/26] Hexagon (target/hexagon) circular addressing Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 23/26] Hexagon (target/hexagon) bit reverse (brev) addressing Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 24/26] Hexagon (target/hexagon) load and unpack bytes instructions Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 25/26] Hexagon (target/hexagon) load into shifted register instructions Taylor Simpson
2021-04-09 1:07 ` [PATCH v4 26/26] Hexagon (target/hexagon) CABAC decode bin Taylor Simpson
2021-04-27 16:27 ` [PATCH v4 00/26] Hexagon (target/hexagon) update Richard Henderson
2021-04-28 21:12 ` Richard Henderson
2021-04-28 23:20 ` Taylor Simpson
2021-04-28 23:53 ` Richard Henderson
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