[Bug 1905297] [NEW] Zynq7000 UART clock reset initialization

[Bug 1905297] [NEW] Zynq7000 UART clock reset initialization

[Michael Peter]

Public bug reported:

Hello,

we have come across a strange behavior in the Zynq7000 model of Qemu
that seems to have been  introduced between 5.0.0 and 5.1.0.


The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
implemented in QEMU.

Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
upon reset. Some investigation revealed that the cause for that is that the corresponding
clocks are not properly initialized.

Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
UART clocks [2]. The last of them [3] triggers the faulty behavior.

Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
underlying device release issue runs much deeper, so it is only meant to identify the issue.


[1] hw/misc/zynq_slcr.c
      static void zynq_slcr_reset_init(Object *obj, ResetType type)
       s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
[2] 38867cb7ec90..5b49a34c6800
[3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
      Author: Damien Hedde <damien.hedde@greensocs.com>
      Date:   Mon Apr 6 15:52:50 2020 +0200

** Affects: qemu
     Importance: Undecided
         Status: New

** Patch added: "0001-Initialize-Zynq7000-UART-clocks-on-reset.patch"
   https://bugs.launchpad.net/bugs/1905297/+attachment/5437267/+files/0001-Initialize-Zynq7000-UART-clocks-on-reset.patch

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Title:
  Zynq7000 UART clock reset initialization

Status in QEMU:
  New

Bug description:
  Hello,

  we have come across a strange behavior in the Zynq7000 model of Qemu
  that seems to have been  introduced between 5.0.0 and 5.1.0.

  
  The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
  the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
  implemented in QEMU.

  Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
  upon reset. Some investigation revealed that the cause for that is that the corresponding
  clocks are not properly initialized.

  Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
  UART clocks [2]. The last of them [3] triggers the faulty behavior.

  Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
  underlying device release issue runs much deeper, so it is only meant to identify the issue.


  [1] hw/misc/zynq_slcr.c
        static void zynq_slcr_reset_init(Object *obj, ResetType type)
         s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
  [2] 38867cb7ec90..5b49a34c6800
  [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
        Author: Damien Hedde <damien.hedde@greensocs.com>
        Date:   Mon Apr 6 15:52:50 2020 +0200

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Re: [Bug 1905297] [NEW] Zynq7000 UART clock reset initialization

[Philippe Mathieu-Daudé]

Hi Michael,

On 11/23/20 5:41 PM, Michael Peter wrote:
> Public bug reported:
> 
> Hello,
> 
> we have come across a strange behavior in the Zynq7000 model of Qemu
> that seems to have been  introduced between 5.0.0 and 5.1.0.
> 
> 
> The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
> the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
> implemented in QEMU.
> 
> Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
> upon reset. Some investigation revealed that the cause for that is that the corresponding
> clocks are not properly initialized.
> 
> Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
> UART clocks [2]. The last of them [3] triggers the faulty behavior.
> 
> Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
> underlying device release issue runs much deeper, so it is only meant to identify the issue.
> 
> 
> [1] hw/misc/zynq_slcr.c
>       static void zynq_slcr_reset_init(Object *obj, ResetType type)
>        s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
> [2] 38867cb7ec90..5b49a34c6800
> [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
>       Author: Damien Hedde <damien.hedde@greensocs.com>
>       Date:   Mon Apr 6 15:52:50 2020 +0200
> 
> ** Affects: qemu
>      Importance: Undecided
>          Status: New
> 
> ** Patch added: "0001-Initialize-Zynq7000-UART-clocks-on-reset.patch"
>    https://bugs.launchpad.net/bugs/1905297/+attachment/5437267/+files/0001-Initialize-Zynq7000-UART-clocks-on-reset.patch
> 

Can you post your patch to the mailing list
please? See:
https://wiki.qemu.org/Contribute/SubmitAPatch#Do_not_send_as_an_attachment

Note, you must sign your patch with a Signed-off-by:
line, see:
https://wiki.qemu.org/Contribute/SubmitAPatch#Patch_emails_must_include_a_Signed-off-by:_line

Regards,

Phil.

Re: [Bug 1905297] [NEW] Zynq7000 UART clock reset initialization

[Philippe Mathieu-Daudé]

Hi Michael,

On 11/23/20 5:41 PM, Michael Peter wrote:
> Public bug reported:
> 
> Hello,
> 
> we have come across a strange behavior in the Zynq7000 model of Qemu
> that seems to have been  introduced between 5.0.0 and 5.1.0.
> 
> 
> The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
> the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
> implemented in QEMU.
> 
> Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
> upon reset. Some investigation revealed that the cause for that is that the corresponding
> clocks are not properly initialized.
> 
> Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
> UART clocks [2]. The last of them [3] triggers the faulty behavior.
> 
> Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
> underlying device release issue runs much deeper, so it is only meant to identify the issue.
> 
> 
> [1] hw/misc/zynq_slcr.c
>       static void zynq_slcr_reset_init(Object *obj, ResetType type)
>        s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
> [2] 38867cb7ec90..5b49a34c6800
> [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
>       Author: Damien Hedde <damien.hedde@greensocs.com>
>       Date:   Mon Apr 6 15:52:50 2020 +0200
> 
> ** Affects: qemu
>      Importance: Undecided
>          Status: New
> 
> ** Patch added: "0001-Initialize-Zynq7000-UART-clocks-on-reset.patch"
>    https://bugs.launchpad.net/bugs/1905297/+attachment/5437267/+files/0001-Initialize-Zynq7000-UART-clocks-on-reset.patch
> 

Can you post your patch to the mailing list
please? See:
https://wiki.qemu.org/Contribute/SubmitAPatch#Do_not_send_as_an_attachment

Note, you must sign your patch with a Signed-off-by:
line, see:
https://wiki.qemu.org/Contribute/SubmitAPatch#Patch_emails_must_include_a_Signed-off-by:_line

Regards,

Phil.

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Title:
  Zynq7000 UART clock reset initialization

Status in QEMU:
  New

Bug description:
  Hello,

  we have come across a strange behavior in the Zynq7000 model of Qemu
  that seems to have been  introduced between 5.0.0 and 5.1.0.

  
  The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
  the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
  implemented in QEMU.

  Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
  upon reset. Some investigation revealed that the cause for that is that the corresponding
  clocks are not properly initialized.

  Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
  UART clocks [2]. The last of them [3] triggers the faulty behavior.

  Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
  underlying device release issue runs much deeper, so it is only meant to identify the issue.


  [1] hw/misc/zynq_slcr.c
        static void zynq_slcr_reset_init(Object *obj, ResetType type)
         s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
  [2] 38867cb7ec90..5b49a34c6800
  [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
        Author: Damien Hedde <damien.hedde@greensocs.com>
        Date:   Mon Apr 6 15:52:50 2020 +0200

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[Bug 1905297] Re: Zynq7000 UART clock reset initialization

[Michael Peter]

Hi Phil,

thanks for your advise and patience.

I created a new patch (this time with a sign-off) and sent it to qemu-
devel@nongnu.org.

Since I have to use a corporate email system, I hope that the formatting
is not gone.

Best regards,

Michael

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Title:
  Zynq7000 UART clock reset initialization

Status in QEMU:
  New

Bug description:
  Hello,

  we have come across a strange behavior in the Zynq7000 model of Qemu
  that seems to have been  introduced between 5.0.0 and 5.1.0.

  
  The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
  the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
  implemented in QEMU.

  Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
  upon reset. Some investigation revealed that the cause for that is that the corresponding
  clocks are not properly initialized.

  Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
  UART clocks [2]. The last of them [3] triggers the faulty behavior.

  Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
  underlying device release issue runs much deeper, so it is only meant to identify the issue.


  [1] hw/misc/zynq_slcr.c
        static void zynq_slcr_reset_init(Object *obj, ResetType type)
         s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
  [2] 38867cb7ec90..5b49a34c6800
  [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
        Author: Damien Hedde <damien.hedde@greensocs.com>
        Date:   Mon Apr 6 15:52:50 2020 +0200

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[Bug 1905297] Re: Zynq7000 UART clock reset initialization

[Thomas Huth]

Has this been fixed in QEMU v6.0?

** Changed in: qemu
       Status: New => Incomplete

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Title:
  Zynq7000 UART clock reset initialization

Status in QEMU:
  Incomplete

Bug description:
  Hello,

  we have come across a strange behavior in the Zynq7000 model of Qemu
  that seems to have been  introduced between 5.0.0 and 5.1.0.

  
  The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
  the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
  implemented in QEMU.

  Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
  upon reset. Some investigation revealed that the cause for that is that the corresponding
  clocks are not properly initialized.

  Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
  UART clocks [2]. The last of them [3] triggers the faulty behavior.

  Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
  underlying device release issue runs much deeper, so it is only meant to identify the issue.


  [1] hw/misc/zynq_slcr.c
        static void zynq_slcr_reset_init(Object *obj, ResetType type)
         s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
  [2] 38867cb7ec90..5b49a34c6800
  [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
        Author: Damien Hedde <damien.hedde@greensocs.com>
        Date:   Mon Apr 6 15:52:50 2020 +0200

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[Bug 1905297] Re: Zynq7000 UART clock reset initialization

[Launchpad Bug Tracker]

[Expired for QEMU because there has been no activity for 60 days.]

** Changed in: qemu
       Status: Incomplete => Expired

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Title:
  Zynq7000 UART clock reset initialization

Status in QEMU:
  Expired

Bug description:
  Hello,

  we have come across a strange behavior in the Zynq7000 model of Qemu
  that seems to have been  introduced between 5.0.0 and 5.1.0.

  
  The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
  the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
  implemented in QEMU.

  Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
  upon reset. Some investigation revealed that the cause for that is that the corresponding
  clocks are not properly initialized.

  Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
  UART clocks [2]. The last of them [3] triggers the faulty behavior.

  Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
  underlying device release issue runs much deeper, so it is only meant to identify the issue.


  [1] hw/misc/zynq_slcr.c
        static void zynq_slcr_reset_init(Object *obj, ResetType type)
         s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
  [2] 38867cb7ec90..5b49a34c6800
  [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
        Author: Damien Hedde <damien.hedde@greensocs.com>
        Date:   Mon Apr 6 15:52:50 2020 +0200

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[Bug 1905297] Re: Zynq7000 UART clock reset initialization

[Floyd42]

Any update?

** Changed in: qemu
       Status: Expired => Incomplete

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Title:
  Zynq7000 UART clock reset initialization

Status in QEMU:
  Incomplete

Bug description:
  Hello,

  we have come across a strange behavior in the Zynq7000 model of Qemu
  that seems to have been  introduced between 5.0.0 and 5.1.0.

  
  The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
  the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
  implemented in QEMU.

  Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
  upon reset. Some investigation revealed that the cause for that is that the corresponding
  clocks are not properly initialized.

  Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
  UART clocks [2]. The last of them [3] triggers the faulty behavior.

  Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
  underlying device release issue runs much deeper, so it is only meant to identify the issue.


  [1] hw/misc/zynq_slcr.c
        static void zynq_slcr_reset_init(Object *obj, ResetType type)
         s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
  [2] 38867cb7ec90..5b49a34c6800
  [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
        Author: Damien Hedde <damien.hedde@greensocs.com>
        Date:   Mon Apr 6 15:52:50 2020 +0200

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[Bug 1905297] Re: Zynq7000 UART clock reset initialization

[Thomas Huth]

I guess the patch has never been sent to the qemu-devel mailing list and
thus was never considered for inclusion. Anyway, let's move this ticket
over to the new bug tracker at gitlab.com, maybe it gets more attention
there...

** Changed in: qemu
       Status: Incomplete => Expired

** Bug watch added: gitlab.com/qemu-project/qemu/-/issues #468
   https://gitlab.com/qemu-project/qemu/-/issues/468

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Title:
  Zynq7000 UART clock reset initialization

Status in QEMU:
  Expired

Bug description:
  Hello,

  we have come across a strange behavior in the Zynq7000 model of Qemu
  that seems to have been  introduced between 5.0.0 and 5.1.0.

  
  The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
  the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
  implemented in QEMU.

  Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
  upon reset. Some investigation revealed that the cause for that is that the corresponding
  clocks are not properly initialized.

  Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
  UART clocks [2]. The last of them [3] triggers the faulty behavior.

  Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
  underlying device release issue runs much deeper, so it is only meant to identify the issue.


  [1] hw/misc/zynq_slcr.c
        static void zynq_slcr_reset_init(Object *obj, ResetType type)
         s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
  [2] 38867cb7ec90..5b49a34c6800
  [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
        Author: Damien Hedde <damien.hedde@greensocs.com>
        Date:   Mon Apr 6 15:52:50 2020 +0200

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[Bug 1905297] Moved bug report

[Thomas Huth]

This is an automated cleanup. This bug report has been moved to QEMU's
new bug tracker on gitlab.com and thus gets marked as 'expired' now.
Please continue with the discussion here:

 https://gitlab.com/qemu-project/qemu/-/issues/468

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Title:
  Zynq7000 UART clock reset initialization

Status in QEMU:
  Expired

Bug description:
  Hello,

  we have come across a strange behavior in the Zynq7000 model of Qemu
  that seems to have been  introduced between 5.0.0 and 5.1.0.

  
  The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
  the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
  implemented in QEMU.

  Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
  upon reset. Some investigation revealed that the cause for that is that the corresponding
  clocks are not properly initialized.

  Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
  UART clocks [2]. The last of them [3] triggers the faulty behavior.

  Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
  underlying device release issue runs much deeper, so it is only meant to identify the issue.


  [1] hw/misc/zynq_slcr.c
        static void zynq_slcr_reset_init(Object *obj, ResetType type)
         s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
  [2] 38867cb7ec90..5b49a34c6800
  [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
        Author: Damien Hedde <damien.hedde@greensocs.com>
        Date:   Mon Apr 6 15:52:50 2020 +0200

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[Bug 1905297] Re: Zynq7000 UART clock reset initialization

[Philippe Mathieu-Daudé]

Michael your patch is still missing your Signed-off-tag. Can you re-attach it including it?
You can also use https://sr.ht/ to send the patch directly to the list.

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Title:
  Zynq7000 UART clock reset initialization

Status in QEMU:
  Expired

Bug description:
  Hello,

  we have come across a strange behavior in the Zynq7000 model of Qemu
  that seems to have been  introduced between 5.0.0 and 5.1.0.

  
  The reset values of the SLCR register, in particular those for UART_CLK_CTRL, are such that
  the UARTs should find functional clocks. Up to 5.0.0 this was also the behavior that was
  implemented in QEMU.

  Starting in 5.1.0, we found that - despite correct reset values [1] - the UARTs are non-functional
  upon reset. Some investigation revealed that the cause for that is that the corresponding
  clocks are not properly initialized.

  Between 5.0.0 and 5.1.0, there are three commits  that touch the Zynq
  UART clocks [2]. The last of them [3] triggers the faulty behavior.

  Attached is a patch that applies 5.2.0-rc2 and yields a functional UART. We surmise that the
  underlying device release issue runs much deeper, so it is only meant to identify the issue.


  [1] hw/misc/zynq_slcr.c
        static void zynq_slcr_reset_init(Object *obj, ResetType type)
         s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
  [2] 38867cb7ec90..5b49a34c6800
  [3] commit 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (refs/bisect/bad)
        Author: Damien Hedde <damien.hedde@greensocs.com>
        Date:   Mon Apr 6 15:52:50 2020 +0200

To manage notifications about this bug go to:
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