From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: sagark@eecs.berkeley.edu, palmer@sifive.com,
kbastian@mail.uni-paderborn.de
Cc: qemu-riscv@nongnu.org, peer.adelt@hni.uni-paderborn.de,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>
Subject: [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A insns to decodetree
Date: Wed, 23 Jan 2019 10:25:14 +0100 [thread overview]
Message-ID: <20190123092538.8004-12-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <20190123092538.8004-1-kbastian@mail.uni-paderborn.de>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
---
target/riscv/insn32-64.decode | 13 +++
target/riscv/insn_trans/trans_rva.inc.c | 58 ++++++++++
target/riscv/translate.c | 140 ------------------------
3 files changed, 71 insertions(+), 140 deletions(-)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 008f100546..0bee95c984 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -43,3 +43,16 @@ divw 0000001 ..... ..... 100 ..... 0111011 @r
divuw 0000001 ..... ..... 101 ..... 0111011 @r
remw 0000001 ..... ..... 110 ..... 0111011 @r
remuw 0000001 ..... ..... 111 ..... 0111011 @r
+
+# *** RV64A Standard Extension (in addition to RV32A) ***
+lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
+sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
+amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
+amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
+amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
+amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
+amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
+amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.inc.c
index ab6ccf0e90..11620e030e 100644
--- a/target/riscv/insn_trans/trans_rva.inc.c
+++ b/target/riscv/insn_trans/trans_rva.inc.c
@@ -147,3 +147,61 @@ static bool trans_amomaxu_w(DisasContext *ctx, arg_amomaxu_w *a)
{
return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TESL));
}
+
+#ifdef TARGET_RISCV64
+
+static bool trans_lr_d(DisasContext *ctx, arg_lr_d *a)
+{
+ return gen_lr(ctx, a, MO_ALIGN | MO_TEQ);
+}
+
+static bool trans_sc_d(DisasContext *ctx, arg_sc_d *a)
+{
+ return gen_sc(ctx, a, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoswap_d(DisasContext *ctx, arg_amoswap_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoadd_d(DisasContext *ctx, arg_amoadd_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoxor_d(DisasContext *ctx, arg_amoxor_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoand_d(DisasContext *ctx, arg_amoand_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amoor_d(DisasContext *ctx, arg_amoor_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomin_d(DisasContext *ctx, arg_amomin_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomax_d(DisasContext *ctx, arg_amomax_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amominu_d(DisasContext *ctx, arg_amominu_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN | MO_TEQ));
+}
+
+static bool trans_amomaxu_d(DisasContext *ctx, arg_amomaxu_d *a)
+{
+ return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN | MO_TEQ));
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 98180002ef..944836dd7c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,143 +711,6 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
tcg_temp_free(t0);
}
-static void gen_atomic(DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int rs2)
-{
- TCGv src1, src2, dat;
- TCGLabel *l1, *l2;
- TCGMemOp mop;
- bool aq, rl;
-
- /* Extract the size of the atomic operation. */
- switch (extract32(opc, 12, 3)) {
- case 2: /* 32-bit */
- mop = MO_ALIGN | MO_TESL;
- break;
-#if defined(TARGET_RISCV64)
- case 3: /* 64-bit */
- mop = MO_ALIGN | MO_TEQ;
- break;
-#endif
- default:
- gen_exception_illegal(ctx);
- return;
- }
- rl = extract32(opc, 25, 1);
- aq = extract32(opc, 26, 1);
-
- src1 = tcg_temp_new();
- src2 = tcg_temp_new();
-
- switch (MASK_OP_ATOMIC_NO_AQ_RL_SZ(opc)) {
- case OPC_RISC_LR:
- /* Put addr in load_res, data in load_val. */
- gen_get_gpr(src1, rs1);
- if (rl) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- }
- tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
- if (aq) {
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
- }
- tcg_gen_mov_tl(load_res, src1);
- gen_set_gpr(rd, load_val);
- break;
-
- case OPC_RISC_SC:
- l1 = gen_new_label();
- l2 = gen_new_label();
- dat = tcg_temp_new();
-
- gen_get_gpr(src1, rs1);
- tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
-
- gen_get_gpr(src2, rs2);
- /* Note that the TCG atomic primitives are SC,
- so we can ignore AQ/RL along this path. */
- tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
- ctx->mem_idx, mop);
- tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
- gen_set_gpr(rd, dat);
- tcg_gen_br(l2);
-
- gen_set_label(l1);
- /* Address comparion failure. However, we still need to
- provide the memory barrier implied by AQ/RL. */
- tcg_gen_mb(TCG_MO_ALL + aq * TCG_BAR_LDAQ + rl * TCG_BAR_STRL);
- tcg_gen_movi_tl(dat, 1);
- gen_set_gpr(rd, dat);
-
- gen_set_label(l2);
- tcg_temp_free(dat);
- break;
-
- case OPC_RISC_AMOSWAP:
- /* Note that the TCG atomic primitives are SC,
- so we can ignore AQ/RL along this path. */
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_xchg_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOADD:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_add_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOXOR:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_xor_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOAND:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_and_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOOR:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_or_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMIN:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_smin_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMAX:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_smax_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMINU:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_umin_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
- case OPC_RISC_AMOMAXU:
- gen_get_gpr(src1, rs1);
- gen_get_gpr(src2, rs2);
- tcg_gen_atomic_fetch_umax_tl(src2, src1, src2, ctx->mem_idx, mop);
- gen_set_gpr(rd, src2);
- break;
-
- default:
- gen_exception_illegal(ctx);
- break;
- }
-
- tcg_temp_free(src1);
- tcg_temp_free(src2);
-}
-
static void gen_set_rm(DisasContext *ctx, int rm)
{
TCGv_i32 t0;
@@ -1679,9 +1542,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2,
GET_STORE_IMM(ctx->opcode));
break;
- case OPC_RISC_ATOMIC:
- gen_atomic(ctx, MASK_OP_ATOMIC(ctx->opcode), rd, rs1, rs2);
- break;
case OPC_RISC_FMADD:
gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2,
GET_RS3(ctx->opcode), GET_RM(ctx->opcode));
--
2.20.1
next prev parent reply other threads:[~2019-01-23 9:26 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-23 9:25 [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-23 9:25 ` Bastian Koppelmann [this message]
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-25 22:23 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-25 22:23 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-25 22:25 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-25 22:27 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-25 22:28 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-25 22:29 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-31 17:50 ` [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree no-reply
2019-01-31 18:18 ` no-reply
2019-01-31 18:22 ` no-reply
2019-02-12 23:21 ` Palmer Dabbelt
2019-02-13 2:15 ` Palmer Dabbelt
2019-02-13 9:06 ` Bastian Koppelmann
2019-02-13 15:34 ` Palmer Dabbelt
2019-02-14 0:37 ` Palmer Dabbelt
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