From: Alistair <alistair23@gmail.com>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
sagark@eecs.berkeley.edu, palmer@sifive.com
Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch()
Date: Fri, 25 Jan 2019 14:23:14 -0800 [thread overview]
Message-ID: <e949c7da-043d-036c-ff44-44561c9680cb@gmail.com> (raw)
In-Reply-To: <20190123092538.8004-22-kbastian@mail.uni-paderborn.de>
On 1/23/19 1:25 AM, Bastian Koppelmann wrote:
> We now utilizes argument-sets of decodetree such that no manual
> decoding is necessary.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.inc.c | 46 +++++++++++++++++-------
> target/riscv/translate.c | 47 -------------------------
> 2 files changed, 33 insertions(+), 60 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
> index 3b3aff4803..0db1f79d20 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -72,41 +72,61 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
> return true;
> }
>
> -static bool trans_beq(DisasContext *ctx, arg_beq *a)
> +static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
> {
> - gen_branch(ctx->env, ctx, OPC_RISC_BEQ, a->rs1, a->rs2, a->imm);
> + TCGLabel *l = gen_new_label();
> + TCGv source1, source2;
> + source1 = tcg_temp_new();
> + source2 = tcg_temp_new();
> + gen_get_gpr(source1, a->rs1);
> + gen_get_gpr(source2, a->rs2);
> +
> + tcg_gen_brcond_tl(cond, source1, source2, l);
> + gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
> + gen_set_label(l); /* branch taken */
> +
> + if (!riscv_has_ext(ctx->env, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
> + /* misaligned */
> + gen_exception_inst_addr_mis(ctx);
> + } else {
> + gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
> + }
> + ctx->base.is_jmp = DISAS_NORETURN;
> +
> + tcg_temp_free(source1);
> + tcg_temp_free(source2);
> +
> return true;
> }
>
> +static bool trans_beq(DisasContext *ctx, arg_beq *a)
> +{
> + return gen_branch(ctx, a, TCG_COND_EQ);
> +}
> +
> static bool trans_bne(DisasContext *ctx, arg_bne *a)
> {
> - gen_branch(ctx->env, ctx, OPC_RISC_BNE, a->rs1, a->rs2, a->imm);
> - return true;
> + return gen_branch(ctx, a, TCG_COND_NE);
> }
>
> static bool trans_blt(DisasContext *ctx, arg_blt *a)
> {
> - gen_branch(ctx->env, ctx, OPC_RISC_BLT, a->rs1, a->rs2, a->imm);
> - return true;
> + return gen_branch(ctx, a, TCG_COND_LT);
> }
>
> static bool trans_bge(DisasContext *ctx, arg_bge *a)
> {
> - gen_branch(ctx->env, ctx, OPC_RISC_BGE, a->rs1, a->rs2, a->imm);
> - return true;
> + return gen_branch(ctx, a, TCG_COND_GE);
> }
>
> static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
> {
> - gen_branch(ctx->env, ctx, OPC_RISC_BLTU, a->rs1, a->rs2, a->imm);
> - return true;
> + return gen_branch(ctx, a, TCG_COND_LTU);
> }
>
> static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
> {
> -
> - gen_branch(ctx->env, ctx, OPC_RISC_BGEU, a->rs1, a->rs2, a->imm);
> - return true;
> + return gen_branch(ctx, a, TCG_COND_GEU);
> }
>
> static bool trans_lb(DisasContext *ctx, arg_lb *a)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 1f59b02c84..a0e96b94a9 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -489,53 +489,6 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> -static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> - int rs1, int rs2, target_long bimm)
> -{
> - TCGLabel *l = gen_new_label();
> - TCGv source1, source2;
> - source1 = tcg_temp_new();
> - source2 = tcg_temp_new();
> - gen_get_gpr(source1, rs1);
> - gen_get_gpr(source2, rs2);
> -
> - switch (opc) {
> - case OPC_RISC_BEQ:
> - tcg_gen_brcond_tl(TCG_COND_EQ, source1, source2, l);
> - break;
> - case OPC_RISC_BNE:
> - tcg_gen_brcond_tl(TCG_COND_NE, source1, source2, l);
> - break;
> - case OPC_RISC_BLT:
> - tcg_gen_brcond_tl(TCG_COND_LT, source1, source2, l);
> - break;
> - case OPC_RISC_BGE:
> - tcg_gen_brcond_tl(TCG_COND_GE, source1, source2, l);
> - break;
> - case OPC_RISC_BLTU:
> - tcg_gen_brcond_tl(TCG_COND_LTU, source1, source2, l);
> - break;
> - case OPC_RISC_BGEU:
> - tcg_gen_brcond_tl(TCG_COND_GEU, source1, source2, l);
> - break;
> - default:
> - gen_exception_illegal(ctx);
> - return;
> - }
> - tcg_temp_free(source1);
> - tcg_temp_free(source2);
> -
> - gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
> - gen_set_label(l); /* branch taken */
> - if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
> - /* misaligned */
> - gen_exception_inst_addr_mis(ctx);
> - } else {
> - gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm);
> - }
> - ctx->base.is_jmp = DISAS_NORETURN;
> -}
> -
> static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1,
> target_long imm)
> {
>
next prev parent reply other threads:[~2019-01-25 22:23 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-23 9:25 [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 01/35] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 03/35] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 04/35] target/riscv: Convert RV32I load/store " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 05/35] target/riscv: Convert RV64I " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 06/35] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 07/35] target/riscv: Convert RVXI fence " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 08/35] target/riscv: Convert RVXI csr " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 09/35] target/riscv: Convert RVXM " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 10/35] target/riscv: Convert RV32A " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 11/35] target/riscv: Convert RV64A " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 12/35] target/riscv: Convert RV32F " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 13/35] target/riscv: Convert RV64F " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 14/35] target/riscv: Convert RV32D " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 15/35] target/riscv: Convert RV64D " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 16/35] target/riscv: Convert RV priv " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 17/35] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 18/35] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 19/35] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 20/35] target/riscv: Remove gen_jalr() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 21/35] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2019-01-25 22:23 ` Alistair [this message]
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 22/35] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2019-01-25 22:23 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 23/35] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2019-01-25 22:25 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2019-01-25 22:27 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 26/35] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 27/35] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 28/35] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2019-01-25 22:28 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 29/35] target/riscv: Remove gen_system() Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 30/35] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2019-01-25 22:29 ` Alistair
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 31/35] target/riscv: Convert @cs_2 insns to share translation functions Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 33/35] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 34/35] target/riscv: Splice remaining compressed insn pairs " Bastian Koppelmann
2019-01-23 9:25 ` [Qemu-devel] [PATCH v6 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators Bastian Koppelmann
2019-01-31 17:50 ` [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree no-reply
2019-01-31 18:18 ` no-reply
2019-01-31 18:22 ` no-reply
2019-02-12 23:21 ` Palmer Dabbelt
2019-02-13 2:15 ` Palmer Dabbelt
2019-02-13 9:06 ` Bastian Koppelmann
2019-02-13 15:34 ` Palmer Dabbelt
2019-02-14 0:37 ` Palmer Dabbelt
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